Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T8,T9
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T8,T9
1	0	Covered	T8,T9,T12
1	1	Covered	T18,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T8,T9
0	1	Covered	T18,T12,T67
1	0	Covered	T12,T77,T245

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T40
0	1	Covered	T8,T9,T40
1	0	Covered	T262,T263

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T40
1	-	Covered	T8,T9,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T8,T9
DetectSt	168	Covered	T18,T8,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T9,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T8,T9
DebounceSt->IdleSt	163	Covered	T55,T243,T76
DetectSt->IdleSt	186	Covered	T18,T12,T67
DetectSt->StableSt	191	Covered	T8,T9,T40
IdleSt->DebounceSt	148	Covered	T18,T8,T9
StableSt->IdleSt	206	Covered	T8,T9,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T8,T9
0	1	Covered	T18,T8,T9
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T8,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T18,T8,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T243,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T18,T12,T67
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T40
DetectSt	-	-	-	-	0	0	-	Covered	T18,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T40
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T40
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	3124	0	0
CntIncr_A	9094833	105383	0	0
CntNoWrap_A	9094833	8424045	0	0
DetectStDropOut_A	9094833	435	0	0
DetectedOut_A	9094833	75178	0	0
DetectedPulseOut_A	9094833	851	0	0
DisabledIdleSt_A	9094833	7954860	0	0
DisabledNoDetection_A	9094833	7957048	0	0
EnterDebounceSt_A	9094833	1566	0	0
EnterDetectSt_A	9094833	1558	0	0
EnterStableSt_A	9094833	851	0	0
PulseIsPulse_A	9094833	851	0	0
StayInStableSt	9094833	74212	0	0
gen_high_event_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	729	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3124	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	46	0	0
T9	0	18	0	0
T12	0	20	0	0
T18	5116	28	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	56	0	0
T41	0	20	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	24	0	0
T68	0	50	0	0
T69	0	10	0	0
T70	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	105383	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	1541	0	0
T9	0	378	0	0
T12	0	1229	0	0
T18	5116	692	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	2016	0	0
T41	0	770	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	641	0	0
T68	0	1450	0	0
T69	0	305	0	0
T70	0	580	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8424045	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	435	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T12	0	5	0	0
T18	5116	14	0	0
T19	521	0	0	0
T25	495	0	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T55	0	1	0	0
T67	0	12	0	0
T96	0	13	0	0
T100	0	7	0	0
T245	0	6	0	0
T246	0	14	0	0
T247	0	21	0	0
T248	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	75178	0	0
T8	22334	2132	0	0
T9	26454	992	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	2057	0	0
T41	0	1234	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	3113	0	0
T69	0	83	0	0
T70	0	1673	0	0
T79	0	3019	0	0
T94	0	1494	0	0
T127	0	727	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	851	0	0
T8	22334	23	0	0
T9	26454	9	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	28	0	0
T41	0	10	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	25	0	0
T69	0	5	0	0
T70	0	10	0	0
T79	0	31	0	0
T94	0	6	0	0
T127	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7954860	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7957048	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1566	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	23	0	0
T9	0	9	0	0
T12	0	10	0	0
T18	5116	14	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	28	0	0
T41	0	10	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	12	0	0
T68	0	25	0	0
T69	0	5	0	0
T70	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1558	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	23	0	0
T9	0	9	0	0
T12	0	10	0	0
T18	5116	14	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	28	0	0
T41	0	10	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	12	0	0
T68	0	25	0	0
T69	0	5	0	0
T70	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	851	0	0
T8	22334	23	0	0
T9	26454	9	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	28	0	0
T41	0	10	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	25	0	0
T69	0	5	0	0
T70	0	10	0	0
T79	0	31	0	0
T94	0	6	0	0
T127	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	851	0	0
T8	22334	23	0	0
T9	26454	9	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	28	0	0
T41	0	10	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	25	0	0
T69	0	5	0	0
T70	0	10	0	0
T79	0	31	0	0
T94	0	6	0	0
T127	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	74212	0	0
T8	22334	2102	0	0
T9	26454	979	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	2027	0	0
T41	0	1224	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	3087	0	0
T69	0	78	0	0
T70	0	1661	0	0
T79	0	2979	0	0
T94	0	1488	0	0
T127	0	717	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	729	0	0
T8	22334	16	0	0
T9	26454	5	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	26	0	0
T41	0	10	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	24	0	0
T69	0	5	0	0
T70	0	8	0	0
T79	0	22	0	0
T94	0	6	0	0
T127	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T8,T9
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T8,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T9,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T32
1	0	Covered	T13,T14,T18
1	1	Covered	T8,T9,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T32
0	1	Covered	T264,T147,T265
1	0	Covered	T55,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T32
0	1	Covered	T8,T9,T32
1	0	Covered	T55,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T32
1	-	Covered	T8,T9,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T32
DetectSt	168	Covered	T8,T9,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T9,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T32
DebounceSt->IdleSt	163	Covered	T43,T31,T24
DetectSt->IdleSt	186	Covered	T264,T147,T55
DetectSt->StableSt	191	Covered	T8,T9,T32
IdleSt->DebounceSt	148	Covered	T8,T9,T32
StableSt->IdleSt	206	Covered	T8,T9,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T32
0	1	Covered	T8,T9,T32
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T32
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T31,T24
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T32
DetectSt	-	-	-	-	1	-	-	Covered	T264,T147,T55
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T32
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T32
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T32
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	897	0	0
CntIncr_A	9094833	49868	0	0
CntNoWrap_A	9094833	8426272	0	0
DetectStDropOut_A	9094833	30	0	0
DetectedOut_A	9094833	16395	0	0
DetectedPulseOut_A	9094833	391	0	0
DisabledIdleSt_A	9094833	8089929	0	0
DisabledNoDetection_A	9094833	8091657	0	0
EnterDebounceSt_A	9094833	472	0	0
EnterDetectSt_A	9094833	425	0	0
EnterStableSt_A	9094833	391	0	0
PulseIsPulse_A	9094833	391	0	0
StayInStableSt	9094833	15973	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	357	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	897	0	0
T8	22334	8	0	0
T9	26454	2	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	7	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	7	0	0
T32	0	6	0	0
T40	0	10	0	0
T43	0	24	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	6	0	0
T70	0	4	0	0
T74	0	17	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	49868	0	0
T8	22334	204	0	0
T9	26454	43	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	463	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	615	0	0
T32	0	351	0	0
T40	0	340	0	0
T43	0	865	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	282	0	0
T70	0	114	0	0
T74	0	962	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8426272	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	30	0	0
T39	949	0	0	0
T93	14737	0	0	0
T114	743	0	0	0
T115	526	0	0	0
T116	497	0	0	0
T117	502	0	0	0
T118	729	0	0	0
T119	96750	0	0	0
T147	0	4	0	0
T211	0	1	0	0
T264	20539	7	0	0
T265	0	6	0	0
T266	0	4	0	0
T267	0	8	0	0
T268	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	16395	0	0
T8	22334	257	0	0
T9	26454	77	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	64	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	110	0	0
T32	0	71	0	0
T40	0	236	0	0
T43	0	200	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	184	0	0
T70	0	589	0	0
T74	0	221	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	391	0	0
T8	22334	4	0	0
T9	26454	1	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	3	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	3	0	0
T32	0	3	0	0
T40	0	5	0	0
T43	0	11	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	3	0	0
T70	0	2	0	0
T74	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8089929	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8091657	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	472	0	0
T8	22334	4	0	0
T9	26454	1	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	4	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	4	0	0
T32	0	3	0	0
T40	0	5	0	0
T43	0	13	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	3	0	0
T70	0	2	0	0
T74	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	425	0	0
T8	22334	4	0	0
T9	26454	1	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	3	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	3	0	0
T32	0	3	0	0
T40	0	5	0	0
T43	0	11	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	3	0	0
T70	0	2	0	0
T74	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	391	0	0
T8	22334	4	0	0
T9	26454	1	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	3	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	3	0	0
T32	0	3	0	0
T40	0	5	0	0
T43	0	11	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	3	0	0
T70	0	2	0	0
T74	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	391	0	0
T8	22334	4	0	0
T9	26454	1	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	3	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	3	0	0
T32	0	3	0	0
T40	0	5	0	0
T43	0	11	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	3	0	0
T70	0	2	0	0
T74	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	15973	0	0
T8	22334	253	0	0
T9	26454	76	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	61	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	107	0	0
T32	0	68	0	0
T40	0	229	0	0
T43	0	189	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	181	0	0
T70	0	587	0	0
T74	0	213	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	357	0	0
T8	22334	4	0	0
T9	26454	1	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T24	0	3	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	3	0	0
T32	0	3	0	0
T40	0	3	0	0
T43	0	11	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	3	0	0
T70	0	2	0	0
T74	0	8	0	0