Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1435409641	11087	0	0
auto_block_debounce_ctl_rd_A	1435409641	2011	0	0
auto_block_out_ctl_rd_A	1435409641	3005	0	0
com_det_ctl_0_rd_A	1435409641	3323	0	0
com_det_ctl_1_rd_A	1435409641	3472	0	0
com_det_ctl_2_rd_A	1435409641	3411	0	0
com_det_ctl_3_rd_A	1435409641	3344	0	0
com_out_ctl_0_rd_A	1435409641	4430	0	0
com_out_ctl_1_rd_A	1435409641	4277	0	0
com_out_ctl_2_rd_A	1435409641	4534	0	0
com_out_ctl_3_rd_A	1435409641	4350	0	0
com_pre_det_ctl_0_rd_A	1435409641	1470	0	0
com_pre_det_ctl_1_rd_A	1435409641	1444	0	0
com_pre_det_ctl_2_rd_A	1435409641	1529	0	0
com_pre_det_ctl_3_rd_A	1435409641	1580	0	0
com_pre_sel_ctl_0_rd_A	1435409641	4715	0	0
com_pre_sel_ctl_1_rd_A	1435409641	4678	0	0
com_pre_sel_ctl_2_rd_A	1435409641	4769	0	0
com_pre_sel_ctl_3_rd_A	1435409641	4413	0	0
com_sel_ctl_0_rd_A	1435409641	4603	0	0
com_sel_ctl_1_rd_A	1435409641	4565	0	0
com_sel_ctl_2_rd_A	1435409641	4572	0	0
com_sel_ctl_3_rd_A	1435409641	4828	0	0
ec_rst_ctl_rd_A	1435409641	2645	0	0
intr_enable_rd_A	1435409641	2804	0	0
key_intr_ctl_rd_A	1435409641	5189	0	0
key_intr_debounce_ctl_rd_A	1435409641	1562	0	0
key_invert_ctl_rd_A	1435409641	7165	0	0
pin_allowed_ctl_rd_A	1435409641	7947	0	0
pin_out_ctl_rd_A	1435409641	5203	0	0
pin_out_value_rd_A	1435409641	5414	0	0
regwen_rd_A	1435409641	2338	0	0
ulp_ac_debounce_ctl_rd_A	1435409641	1731	0	0
ulp_ctl_rd_A	1435409641	1728	0	0
ulp_lid_debounce_ctl_rd_A	1435409641	1672	0	0
ulp_pwrb_debounce_ctl_rd_A	1435409641	1841	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	11087	0	0
T11	206945	5	0	0
T12	114953	0	0	0
T23	129055	0	0	0
T24	0	20	0	0
T28	19425	0	0	0
T36	46631	0	0	0
T38	0	2	0	0
T42	318855	0	0	0
T56	278121	0	0	0
T62	39514	0	0	0
T63	0	1	0	0
T72	0	4	0	0
T98	0	17	0	0
T122	0	7	0	0
T123	0	12	0	0
T136	193060	0	0	0
T146	0	6	0	0
T147	0	16	0	0
T151	202477	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	2011	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	26	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	28	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T119	0	5	0	0
T123	0	39	0	0
T187	0	15	0	0
T191	0	12	0	0
T211	0	18	0	0
T300	0	20	0	0
T301	0	16	0	0
T302	0	40	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	3005	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	30	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	14	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T119	0	2	0	0
T123	0	39	0	0
T186	0	12	0	0
T187	0	4	0	0
T191	0	12	0	0
T211	0	26	0	0
T300	0	3	0	0
T301	0	17	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	3323	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	46	0	0
T38	0	31	0	0
T40	449349	0	0	0
T41	806296	59	0	0
T43	815898	46	0	0
T63	0	11	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	38	0	0
T75	0	81	0	0
T90	60681	0	0	0
T97	0	28	0	0
T127	0	78	0	0
T247	0	21	0	0
T253	52608	0	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	3472	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	44	0	0
T38	0	27	0	0
T40	449349	0	0	0
T41	806296	45	0	0
T43	815898	25	0	0
T63	0	18	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	38	0	0
T75	0	58	0	0
T90	60681	0	0	0
T97	0	13	0	0
T127	0	78	0	0
T247	0	17	0	0
T253	52608	0	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	3411	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	32	0	0
T38	0	8	0	0
T40	449349	0	0	0
T41	806296	65	0	0
T43	815898	41	0	0
T63	0	18	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	53	0	0
T75	0	73	0	0
T90	60681	0	0	0
T97	0	31	0	0
T127	0	77	0	0
T247	0	15	0	0
T253	52608	0	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	3344	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	65	0	0
T38	0	22	0	0
T40	449349	0	0	0
T41	806296	73	0	0
T43	815898	34	0	0
T63	0	16	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	34	0	0
T75	0	93	0	0
T90	60681	0	0	0
T97	0	33	0	0
T127	0	68	0	0
T247	0	19	0	0
T253	52608	0	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4430	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	51	0	0
T38	0	15	0	0
T40	449349	0	0	0
T41	806296	66	0	0
T43	815898	43	0	0
T63	0	21	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	49	0	0
T75	0	61	0	0
T90	60681	0	0	0
T97	0	22	0	0
T127	0	65	0	0
T247	0	17	0	0
T253	52608	0	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4277	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	55	0	0
T38	0	33	0	0
T40	449349	0	0	0
T41	806296	69	0	0
T43	815898	45	0	0
T63	0	22	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	39	0	0
T75	0	90	0	0
T90	60681	0	0	0
T97	0	22	0	0
T127	0	68	0	0
T247	0	30	0	0
T253	52608	0	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4534	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	49	0	0
T38	0	26	0	0
T40	449349	0	0	0
T41	806296	66	0	0
T43	815898	60	0	0
T63	0	8	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	32	0	0
T75	0	85	0	0
T90	60681	0	0	0
T97	0	27	0	0
T127	0	71	0	0
T247	0	23	0	0
T253	52608	0	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4350	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	46	0	0
T38	0	8	0	0
T40	449349	0	0	0
T41	806296	53	0	0
T43	815898	32	0	0
T63	0	24	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	38	0	0
T75	0	67	0	0
T90	60681	0	0	0
T97	0	32	0	0
T127	0	71	0	0
T247	0	10	0	0
T253	52608	0	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1470	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	23	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	17	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T87	0	20	0	0
T123	0	21	0	0
T131	0	3	0	0
T187	0	3	0	0
T211	0	22	0	0
T258	0	18	0	0
T302	0	21	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0
T306	0	11	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1444	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	22	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	27	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T87	0	8	0	0
T123	0	20	0	0
T131	0	5	0	0
T187	0	12	0	0
T191	0	5	0	0
T211	0	11	0	0
T258	0	18	0	0
T302	0	23	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1529	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	11	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	22	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T87	0	17	0	0
T123	0	14	0	0
T131	0	15	0	0
T187	0	11	0	0
T191	0	1	0	0
T211	0	15	0	0
T258	0	7	0	0
T302	0	29	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1580	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	40	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	3	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T87	0	4	0	0
T123	0	29	0	0
T131	0	18	0	0
T187	0	14	0	0
T191	0	7	0	0
T211	0	15	0	0
T302	0	24	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0
T306	0	6	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4715	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	45	0	0
T38	0	37	0	0
T40	449349	0	0	0
T41	806296	63	0	0
T43	815898	38	0	0
T63	0	29	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	50	0	0
T75	0	67	0	0
T90	60681	0	0	0
T97	0	17	0	0
T127	0	76	0	0
T247	0	25	0	0
T253	52608	0	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4678	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	42	0	0
T38	0	14	0	0
T40	449349	0	0	0
T41	806296	55	0	0
T43	815898	44	0	0
T63	0	20	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	15	0	0
T75	0	80	0	0
T90	60681	0	0	0
T97	0	38	0	0
T127	0	73	0	0
T247	0	32	0	0
T253	52608	0	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4769	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	32	0	0
T38	0	18	0	0
T40	449349	0	0	0
T41	806296	49	0	0
T43	815898	69	0	0
T63	0	15	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	35	0	0
T75	0	76	0	0
T90	60681	0	0	0
T97	0	32	0	0
T127	0	68	0	0
T247	0	41	0	0
T253	52608	0	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4413	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	27	0	0
T38	0	21	0	0
T40	449349	0	0	0
T41	806296	43	0	0
T43	815898	30	0	0
T63	0	21	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	31	0	0
T75	0	70	0	0
T90	60681	0	0	0
T97	0	30	0	0
T127	0	87	0	0
T247	0	15	0	0
T253	52608	0	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4603	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	34	0	0
T38	0	20	0	0
T40	449349	0	0	0
T41	806296	76	0	0
T43	815898	37	0	0
T63	0	22	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	35	0	0
T75	0	45	0	0
T90	60681	0	0	0
T97	0	21	0	0
T127	0	77	0	0
T247	0	30	0	0
T253	52608	0	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4565	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	40	0	0
T38	0	17	0	0
T40	449349	0	0	0
T41	806296	52	0	0
T43	815898	32	0	0
T63	0	15	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	35	0	0
T75	0	62	0	0
T90	60681	0	0	0
T97	0	34	0	0
T127	0	67	0	0
T247	0	21	0	0
T253	52608	0	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4572	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	48	0	0
T38	0	24	0	0
T40	449349	0	0	0
T41	806296	66	0	0
T43	815898	28	0	0
T63	0	16	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	36	0	0
T75	0	74	0	0
T90	60681	0	0	0
T97	0	36	0	0
T127	0	90	0	0
T247	0	27	0	0
T253	52608	0	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	4828	0	0
T24	737148	0	0	0
T31	234671	0	0	0
T32	482505	43	0	0
T38	0	44	0	0
T40	449349	0	0	0
T41	806296	58	0	0
T43	815898	50	0	0
T63	0	29	0	0
T65	51018	0	0	0
T67	180793	0	0	0
T68	0	40	0	0
T75	0	60	0	0
T90	60681	0	0	0
T97	0	25	0	0
T127	0	88	0	0
T247	0	23	0	0
T253	52608	0	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	2645	0	0
T2	536896	0	0	0
T3	61906	0	0	0
T14	246436	5	0	0
T15	258633	0	0	0
T16	24812	0	0	0
T17	38518	0	0	0
T18	245569	4	0	0
T19	260636	1	0	0
T25	59425	0	0	0
T32	0	21	0	0
T38	0	22	0	0
T41	0	2	0	0
T43	0	43	0	0
T49	206568	0	0	0
T63	0	25	0	0
T68	0	15	0	0
T261	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	2804	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	21	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	20	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T75	0	2	0	0
T87	0	15	0	0
T123	0	85	0	0
T131	0	7	0	0
T187	0	59	0	0
T191	0	13	0	0
T211	0	57	0	0
T302	0	76	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	5189	0	0
T23	129055	0	0	0
T32	482505	0	0	0
T36	46631	10	0	0
T38	0	22	0	0
T40	449349	0	0	0
T42	318855	0	0	0
T43	815898	0	0	0
T56	278121	0	0	0
T62	39514	0	0	0
T63	0	7	0	0
T75	0	1	0	0
T78	0	3	0	0
T83	0	9	0	0
T123	0	15	0	0
T136	193060	0	0	0
T150	0	1	0	0
T151	202477	0	0	0
T191	0	7	0	0
T209	0	9	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1562	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	10	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	10	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T87	0	16	0	0
T123	0	27	0	0
T131	0	15	0	0
T187	0	17	0	0
T191	0	4	0	0
T211	0	14	0	0
T258	0	3	0	0
T302	0	31	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	7165	0	0
T10	172584	45	0	0
T11	206945	0	0	0
T12	114953	0	0	0
T23	129055	0	0	0
T26	177540	79	0	0
T28	19425	0	0	0
T36	46631	0	0	0
T38	0	210	0	0
T42	318855	0	0	0
T60	0	66	0	0
T62	39514	0	0	0
T63	0	69	0	0
T64	0	76	0	0
T123	0	24	0	0
T151	202477	0	0	0
T307	0	23	0	0
T308	0	57	0	0
T309	0	68	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	7947	0	0
T2	536896	0	0	0
T3	61906	0	0	0
T14	246436	174	0	0
T15	258633	0	0	0
T16	24812	0	0	0
T17	38518	0	0	0
T18	245569	0	0	0
T19	260636	0	0	0
T25	59425	0	0	0
T38	0	47	0	0
T49	206568	0	0	0
T60	0	135	0	0
T63	0	89	0	0
T117	0	86	0	0
T123	0	8	0	0
T179	0	76	0	0
T191	0	16	0	0
T310	0	70	0	0
T311	0	44	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	5203	0	0
T2	536896	0	0	0
T3	61906	0	0	0
T14	246436	91	0	0
T15	258633	0	0	0
T16	24812	0	0	0
T17	38518	0	0	0
T18	245569	0	0	0
T19	260636	0	0	0
T25	59425	0	0	0
T38	0	89	0	0
T49	206568	0	0	0
T60	0	110	0	0
T63	0	67	0	0
T117	0	95	0	0
T123	0	7	0	0
T179	0	61	0	0
T191	0	6	0	0
T310	0	57	0	0
T311	0	74	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	5414	0	0
T2	536896	0	0	0
T3	61906	0	0	0
T14	246436	138	0	0
T15	258633	0	0	0
T16	24812	0	0	0
T17	38518	0	0	0
T18	245569	0	0	0
T19	260636	0	0	0
T25	59425	0	0	0
T38	0	57	0	0
T49	206568	0	0	0
T60	0	130	0	0
T63	0	93	0	0
T117	0	75	0	0
T123	0	16	0	0
T179	0	77	0	0
T191	0	14	0	0
T310	0	52	0	0
T311	0	75	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	2338	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	18	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T63	216297	10	0	0
T68	549134	0	0	0
T74	904036	0	0	0
T87	0	6	0	0
T123	0	13	0	0
T131	0	13	0	0
T187	0	11	0	0
T191	0	6	0	0
T211	0	19	0	0
T302	0	35	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0
T306	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1731	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	38	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T58	0	14	0	0
T60	0	2	0	0
T63	216297	10	0	0
T68	549134	0	0	0
T71	0	8	0	0
T74	904036	0	0	0
T75	0	1	0	0
T123	0	13	0	0
T187	0	23	0	0
T190	0	6	0	0
T220	0	6	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1728	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	10	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T58	0	20	0	0
T60	0	3	0	0
T63	216297	20	0	0
T68	549134	0	0	0
T71	0	7	0	0
T74	904036	0	0	0
T75	0	9	0	0
T123	0	11	0	0
T190	0	3	0	0
T191	0	3	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0
T312	0	5	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1672	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	22	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T58	0	14	0	0
T60	0	4	0	0
T63	216297	11	0	0
T68	549134	0	0	0
T71	0	9	0	0
T74	904036	0	0	0
T75	0	4	0	0
T123	0	31	0	0
T190	0	10	0	0
T191	0	21	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0
T312	0	8	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435409641	1841	0	0
T33	63473	0	0	0
T37	65568	0	0	0
T38	0	33	0	0
T44	293384	0	0	0
T45	270103	0	0	0
T58	0	13	0	0
T60	0	4	0	0
T63	216297	15	0	0
T68	549134	0	0	0
T71	0	5	0	0
T74	904036	0	0	0
T123	0	44	0	0
T187	0	18	0	0
T190	0	7	0	0
T191	0	18	0	0
T303	253495	0	0	0
T304	61276	0	0	0
T305	105829	0	0	0
T312	0	4	0	0