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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.90 99.27 96.78 100.00 96.79 98.71 99.52 94.20


Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T29 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2288397478 Jul 01 10:33:20 AM PDT 24 Jul 01 10:33:28 AM PDT 24 2062829351 ps
T30 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2363480343 Jul 01 10:33:21 AM PDT 24 Jul 01 10:34:16 AM PDT 24 42522261779 ps
T20 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2740670887 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:30 AM PDT 24 4645625047 ps
T21 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.300237451 Jul 01 10:33:28 AM PDT 24 Jul 01 10:33:46 AM PDT 24 7120571141 ps
T275 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.726602921 Jul 01 10:33:20 AM PDT 24 Jul 01 10:34:38 AM PDT 24 63372428221 ps
T316 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3016377536 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:20 AM PDT 24 2088324279 ps
T797 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2805657221 Jul 01 10:33:26 AM PDT 24 Jul 01 10:33:29 AM PDT 24 2040542028 ps
T798 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2683155036 Jul 01 10:33:18 AM PDT 24 Jul 01 10:33:22 AM PDT 24 2042741978 ps
T799 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.709405082 Jul 01 10:33:25 AM PDT 24 Jul 01 10:33:28 AM PDT 24 2044106335 ps
T22 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2059610187 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:29 AM PDT 24 4603740990 ps
T269 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2984337091 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:28 AM PDT 24 2253623977 ps
T800 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3418327130 Jul 01 10:33:25 AM PDT 24 Jul 01 10:33:32 AM PDT 24 2015444049 ps
T276 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3454549167 Jul 01 10:33:18 AM PDT 24 Jul 01 10:33:26 AM PDT 24 10016939077 ps
T314 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3646452932 Jul 01 10:33:23 AM PDT 24 Jul 01 10:33:25 AM PDT 24 2118122515 ps
T277 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3720774132 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:20 AM PDT 24 7840869816 ps
T272 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.706783823 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:48 AM PDT 24 22336134869 ps
T273 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1142431045 Jul 01 10:33:22 AM PDT 24 Jul 01 10:33:53 AM PDT 24 42996716232 ps
T284 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2827846031 Jul 01 10:33:28 AM PDT 24 Jul 01 10:33:35 AM PDT 24 2033315529 ps
T801 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3778275043 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:31 AM PDT 24 2071278087 ps
T802 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2929218512 Jul 01 10:33:25 AM PDT 24 Jul 01 10:33:28 AM PDT 24 2050690024 ps
T330 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1827849718 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:22 AM PDT 24 4650227080 ps
T290 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2204370211 Jul 01 10:33:16 AM PDT 24 Jul 01 10:34:16 AM PDT 24 22210034819 ps
T317 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1318499159 Jul 01 10:33:28 AM PDT 24 Jul 01 10:33:35 AM PDT 24 2054117764 ps
T285 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.4023953918 Jul 01 10:33:10 AM PDT 24 Jul 01 10:35:01 AM PDT 24 42449097627 ps
T803 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4010381236 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:27 AM PDT 24 2134180049 ps
T293 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1891202250 Jul 01 10:33:25 AM PDT 24 Jul 01 10:34:27 AM PDT 24 22195473967 ps
T804 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1147660565 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:51 AM PDT 24 2039616601 ps
T278 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.144754616 Jul 01 10:33:22 AM PDT 24 Jul 01 10:33:26 AM PDT 24 2133800191 ps
T318 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2916260879 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:23 AM PDT 24 2047692114 ps
T282 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2633085303 Jul 01 10:33:43 AM PDT 24 Jul 01 10:33:52 AM PDT 24 2154756151 ps
T291 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2668886164 Jul 01 10:33:16 AM PDT 24 Jul 01 10:34:12 AM PDT 24 42393900407 ps
T805 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2248175474 Jul 01 10:33:18 AM PDT 24 Jul 01 10:33:22 AM PDT 24 2351590500 ps
T331 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3357188805 Jul 01 10:33:25 AM PDT 24 Jul 01 10:33:47 AM PDT 24 5381867489 ps
T288 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1768133542 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:28 AM PDT 24 2217503337 ps
T806 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3222266922 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:21 AM PDT 24 2064754690 ps
T807 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2250656986 Jul 01 10:33:36 AM PDT 24 Jul 01 10:33:45 AM PDT 24 4489637975 ps
T808 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1946251770 Jul 01 10:33:32 AM PDT 24 Jul 01 10:33:48 AM PDT 24 4587964833 ps
T809 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.4090752276 Jul 01 10:33:26 AM PDT 24 Jul 01 10:33:29 AM PDT 24 2033998617 ps
T810 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1564079221 Jul 01 10:33:44 AM PDT 24 Jul 01 10:33:48 AM PDT 24 2018702413 ps
T319 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.640578099 Jul 01 10:33:25 AM PDT 24 Jul 01 10:33:28 AM PDT 24 2175179446 ps
T811 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.786404704 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:29 AM PDT 24 2604441474 ps
T812 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.847902105 Jul 01 10:33:40 AM PDT 24 Jul 01 10:33:50 AM PDT 24 7499373916 ps
T813 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1937425900 Jul 01 10:33:40 AM PDT 24 Jul 01 10:33:43 AM PDT 24 2039000888 ps
T814 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2007783669 Jul 01 10:33:21 AM PDT 24 Jul 01 10:33:28 AM PDT 24 2015352585 ps
T289 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1803800392 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:27 AM PDT 24 23412133500 ps
T815 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2741069655 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:32 AM PDT 24 2057441732 ps
T816 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.330245028 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:23 AM PDT 24 8350203136 ps
T817 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4099919 Jul 01 10:33:31 AM PDT 24 Jul 01 10:33:33 AM PDT 24 2075653549 ps
T818 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4063295698 Jul 01 10:33:40 AM PDT 24 Jul 01 10:33:53 AM PDT 24 8634178893 ps
T320 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.227429457 Jul 01 10:33:20 AM PDT 24 Jul 01 10:33:26 AM PDT 24 6045896522 ps
T286 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1083501728 Jul 01 10:33:20 AM PDT 24 Jul 01 10:34:02 AM PDT 24 22271966596 ps
T819 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3632920447 Jul 01 10:33:43 AM PDT 24 Jul 01 10:33:49 AM PDT 24 2015279871 ps
T321 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2170138638 Jul 01 10:33:36 AM PDT 24 Jul 01 10:33:39 AM PDT 24 2087497775 ps
T287 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1081478543 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:22 AM PDT 24 2135975850 ps
T279 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2999862949 Jul 01 10:33:16 AM PDT 24 Jul 01 10:33:20 AM PDT 24 2079413314 ps
T820 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1667151473 Jul 01 10:33:22 AM PDT 24 Jul 01 10:33:29 AM PDT 24 2129677894 ps
T821 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.866782258 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:21 AM PDT 24 4035952577 ps
T822 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3548788505 Jul 01 10:33:16 AM PDT 24 Jul 01 10:33:19 AM PDT 24 2042531335 ps
T823 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3643806611 Jul 01 10:33:16 AM PDT 24 Jul 01 10:33:24 AM PDT 24 4814533297 ps
T349 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1498297630 Jul 01 10:33:26 AM PDT 24 Jul 01 10:33:53 AM PDT 24 42911990652 ps
T824 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1082319248 Jul 01 10:33:48 AM PDT 24 Jul 01 10:33:53 AM PDT 24 2022434597 ps
T825 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2234192089 Jul 01 10:33:31 AM PDT 24 Jul 01 10:33:33 AM PDT 24 2201244360 ps
T826 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.865134510 Jul 01 10:33:29 AM PDT 24 Jul 01 10:33:31 AM PDT 24 2265483753 ps
T827 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.506668089 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:19 AM PDT 24 2057636656 ps
T828 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2394972929 Jul 01 10:33:36 AM PDT 24 Jul 01 10:34:34 AM PDT 24 42652751625 ps
T322 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3710043385 Jul 01 10:33:23 AM PDT 24 Jul 01 10:33:30 AM PDT 24 2048542972 ps
T323 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3083044890 Jul 01 10:33:12 AM PDT 24 Jul 01 10:34:40 AM PDT 24 36133598561 ps
T283 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.281660468 Jul 01 10:33:12 AM PDT 24 Jul 01 10:33:23 AM PDT 24 2486851688 ps
T324 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.288592743 Jul 01 10:33:27 AM PDT 24 Jul 01 10:33:34 AM PDT 24 2059502389 ps
T829 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.282274360 Jul 01 10:33:49 AM PDT 24 Jul 01 10:33:55 AM PDT 24 2126894685 ps
T830 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4011524450 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:21 AM PDT 24 2697626850 ps
T831 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2789157287 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:31 AM PDT 24 2010471758 ps
T832 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3507606814 Jul 01 10:33:45 AM PDT 24 Jul 01 10:33:48 AM PDT 24 2038031555 ps
T833 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.469127136 Jul 01 10:33:45 AM PDT 24 Jul 01 10:33:52 AM PDT 24 2013360260 ps
T292 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1344793895 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:24 AM PDT 24 2048176759 ps
T280 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3757055541 Jul 01 10:33:29 AM PDT 24 Jul 01 10:33:37 AM PDT 24 2154421743 ps
T834 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1728568194 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:26 AM PDT 24 2109291509 ps
T835 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1747835357 Jul 01 10:33:32 AM PDT 24 Jul 01 10:33:36 AM PDT 24 2017154998 ps
T332 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1607243188 Jul 01 10:33:18 AM PDT 24 Jul 01 10:33:24 AM PDT 24 6088189668 ps
T836 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4249944850 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:31 AM PDT 24 2074623402 ps
T325 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.742406829 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:23 AM PDT 24 2109441929 ps
T837 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.747191064 Jul 01 10:33:31 AM PDT 24 Jul 01 10:33:37 AM PDT 24 2012192830 ps
T838 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1633928835 Jul 01 10:33:18 AM PDT 24 Jul 01 10:33:35 AM PDT 24 22487096774 ps
T839 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.837197268 Jul 01 10:33:18 AM PDT 24 Jul 01 10:33:27 AM PDT 24 2108330211 ps
T840 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1567288810 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:21 AM PDT 24 2012765093 ps
T841 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3839362078 Jul 01 10:33:30 AM PDT 24 Jul 01 10:33:41 AM PDT 24 9459687715 ps
T281 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.187668306 Jul 01 10:33:41 AM PDT 24 Jul 01 10:33:45 AM PDT 24 2100602345 ps
T842 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.846697845 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:20 AM PDT 24 2041767923 ps
T843 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.525204071 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:26 AM PDT 24 2036310681 ps
T844 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.381572902 Jul 01 10:33:26 AM PDT 24 Jul 01 10:33:33 AM PDT 24 2031064043 ps
T845 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2342563819 Jul 01 10:33:29 AM PDT 24 Jul 01 10:33:36 AM PDT 24 2049210990 ps
T846 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.680068037 Jul 01 10:33:09 AM PDT 24 Jul 01 10:33:12 AM PDT 24 2147964117 ps
T847 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3905577817 Jul 01 10:33:20 AM PDT 24 Jul 01 10:33:25 AM PDT 24 2216111102 ps
T326 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.496248873 Jul 01 10:33:25 AM PDT 24 Jul 01 10:33:27 AM PDT 24 2253701068 ps
T327 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.635923961 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:23 AM PDT 24 2035369718 ps
T848 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3698335520 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:27 AM PDT 24 2135851142 ps
T328 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1236603578 Jul 01 10:33:26 AM PDT 24 Jul 01 10:33:38 AM PDT 24 4011488193 ps
T849 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2680930817 Jul 01 10:33:32 AM PDT 24 Jul 01 10:33:39 AM PDT 24 2013747387 ps
T850 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3567738200 Jul 01 10:33:33 AM PDT 24 Jul 01 10:33:36 AM PDT 24 2036651303 ps
T851 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2049213849 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:28 AM PDT 24 5138411344 ps
T852 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3178380719 Jul 01 10:33:33 AM PDT 24 Jul 01 10:33:41 AM PDT 24 2110438592 ps
T853 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1875324243 Jul 01 10:33:12 AM PDT 24 Jul 01 10:33:20 AM PDT 24 3201935645 ps
T854 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2463453381 Jul 01 10:33:42 AM PDT 24 Jul 01 10:33:48 AM PDT 24 2011945786 ps
T855 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.356230572 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:23 AM PDT 24 2172907050 ps
T856 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3761809521 Jul 01 10:33:40 AM PDT 24 Jul 01 10:33:47 AM PDT 24 2038450277 ps
T857 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3180463308 Jul 01 10:33:12 AM PDT 24 Jul 01 10:33:25 AM PDT 24 4170770554 ps
T858 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3598836993 Jul 01 10:33:20 AM PDT 24 Jul 01 10:33:24 AM PDT 24 2031313334 ps
T859 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3986550116 Jul 01 10:33:25 AM PDT 24 Jul 01 10:34:24 AM PDT 24 42388208916 ps
T860 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.4065124081 Jul 01 10:33:27 AM PDT 24 Jul 01 10:33:33 AM PDT 24 2032030126 ps
T861 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3479689254 Jul 01 10:33:40 AM PDT 24 Jul 01 10:33:47 AM PDT 24 2014194122 ps
T329 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2642391951 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:44 AM PDT 24 45378307211 ps
T862 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3946411288 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:32 AM PDT 24 2041174415 ps
T863 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1828391488 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:50 AM PDT 24 42879132243 ps
T864 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2848321683 Jul 01 10:33:31 AM PDT 24 Jul 01 10:33:37 AM PDT 24 2013758133 ps
T865 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2767670764 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:20 AM PDT 24 2077574244 ps
T866 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1581485331 Jul 01 10:33:39 AM PDT 24 Jul 01 10:33:46 AM PDT 24 2010669279 ps
T867 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1462835902 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:51 AM PDT 24 42945915033 ps
T868 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1402180024 Jul 01 10:33:34 AM PDT 24 Jul 01 10:33:36 AM PDT 24 2079909937 ps
T869 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2098587117 Jul 01 10:33:17 AM PDT 24 Jul 01 10:34:13 AM PDT 24 22186341978 ps
T870 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.4017965055 Jul 01 10:33:23 AM PDT 24 Jul 01 10:33:28 AM PDT 24 8468829463 ps
T871 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1721912031 Jul 01 10:33:46 AM PDT 24 Jul 01 10:34:02 AM PDT 24 4938901196 ps
T872 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2276210958 Jul 01 10:33:42 AM PDT 24 Jul 01 10:33:45 AM PDT 24 2019859779 ps
T873 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3563184663 Jul 01 10:33:19 AM PDT 24 Jul 01 10:34:17 AM PDT 24 22180894657 ps
T874 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.57190290 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:21 AM PDT 24 2117233717 ps
T875 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1251196960 Jul 01 10:33:34 AM PDT 24 Jul 01 10:33:40 AM PDT 24 2012956780 ps
T876 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.498121398 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:19 AM PDT 24 2896744829 ps
T877 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1095849194 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:27 AM PDT 24 2091753694 ps
T878 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3771287303 Jul 01 10:33:19 AM PDT 24 Jul 01 10:33:33 AM PDT 24 4987826429 ps
T879 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1114311567 Jul 01 10:33:24 AM PDT 24 Jul 01 10:33:27 AM PDT 24 2040892349 ps
T880 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.245139581 Jul 01 10:33:17 AM PDT 24 Jul 01 10:33:21 AM PDT 24 2150467146 ps
T881 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2669660094 Jul 01 10:33:25 AM PDT 24 Jul 01 10:33:33 AM PDT 24 2135556754 ps
T882 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2320311400 Jul 01 10:33:16 AM PDT 24 Jul 01 10:33:26 AM PDT 24 2505958681 ps
T883 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1911973650 Jul 01 10:33:18 AM PDT 24 Jul 01 10:33:25 AM PDT 24 2064233347 ps
T884 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2986983257 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:15 AM PDT 24 2043168633 ps
T885 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.270707033 Jul 01 10:33:28 AM PDT 24 Jul 01 10:34:03 AM PDT 24 42513474161 ps
T886 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.671653838 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:53 AM PDT 24 2011861648 ps
T887 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.668456428 Jul 01 10:33:49 AM PDT 24 Jul 01 10:33:53 AM PDT 24 2083986313 ps
T888 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.81651646 Jul 01 10:33:49 AM PDT 24 Jul 01 10:33:57 AM PDT 24 2121866133 ps
T889 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.380838137 Jul 01 10:33:11 AM PDT 24 Jul 01 10:33:23 AM PDT 24 2889462845 ps
T890 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3347542813 Jul 01 10:33:43 AM PDT 24 Jul 01 10:33:49 AM PDT 24 2016076887 ps
T891 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.4153454383 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:20 AM PDT 24 2018290475 ps
T892 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1543816750 Jul 01 10:33:32 AM PDT 24 Jul 01 10:33:39 AM PDT 24 2032807664 ps
T893 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.975287181 Jul 01 10:33:29 AM PDT 24 Jul 01 10:33:35 AM PDT 24 2038001169 ps
T894 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1583042255 Jul 01 10:33:22 AM PDT 24 Jul 01 10:33:31 AM PDT 24 2018485547 ps
T895 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1702890884 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:17 AM PDT 24 2030921651 ps
T896 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3994494636 Jul 01 10:33:21 AM PDT 24 Jul 01 10:33:24 AM PDT 24 2220171728 ps
T897 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.4272487676 Jul 01 10:33:30 AM PDT 24 Jul 01 10:34:29 AM PDT 24 42602777691 ps
T898 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.575720637 Jul 01 10:33:31 AM PDT 24 Jul 01 10:33:37 AM PDT 24 2019285481 ps
T899 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.37118171 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:55 AM PDT 24 2014155703 ps
T900 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.4275406728 Jul 01 10:33:14 AM PDT 24 Jul 01 10:40:30 AM PDT 24 74779957484 ps
T901 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2508738662 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:23 AM PDT 24 5329709063 ps
T902 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2449385266 Jul 01 10:33:30 AM PDT 24 Jul 01 10:33:32 AM PDT 24 2134029165 ps
T903 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4202384055 Jul 01 10:33:10 AM PDT 24 Jul 01 10:33:30 AM PDT 24 20572636459 ps
T904 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1336329521 Jul 01 10:33:44 AM PDT 24 Jul 01 10:33:52 AM PDT 24 2043076108 ps
T905 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4020555645 Jul 01 10:33:15 AM PDT 24 Jul 01 10:33:24 AM PDT 24 4015329384 ps
T906 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.139493531 Jul 01 10:33:22 AM PDT 24 Jul 01 10:33:26 AM PDT 24 2022566528 ps
T907 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2297358435 Jul 01 10:33:41 AM PDT 24 Jul 01 10:33:44 AM PDT 24 2037315489 ps
T908 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3388778666 Jul 01 10:33:14 AM PDT 24 Jul 01 10:33:47 AM PDT 24 42896617303 ps
T909 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2358897692 Jul 01 10:33:16 AM PDT 24 Jul 01 10:33:24 AM PDT 24 2117593652 ps
T910 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.4011441390 Jul 01 10:33:42 AM PDT 24 Jul 01 10:33:48 AM PDT 24 2010333877 ps
T911 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4191773150 Jul 01 10:33:43 AM PDT 24 Jul 01 10:33:48 AM PDT 24 2016451060 ps
T912 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.356857030 Jul 01 10:33:30 AM PDT 24 Jul 01 10:33:32 AM PDT 24 2030311684 ps
T913 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3593350294 Jul 01 10:33:35 AM PDT 24 Jul 01 10:33:39 AM PDT 24 2027131235 ps
T914 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3148790313 Jul 01 10:33:13 AM PDT 24 Jul 01 10:33:20 AM PDT 24 2229252002 ps

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.462598817
Short name T3
Test name
Test status
Simulation time 4118656953617 ps
CPU time 79.86 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:49:15 AM PDT 24
Peak memory 201708 kb
Host smart-468f9def-9822-432e-bd05-5c1b8d1d081f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462598817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ultra_low_pwr.462598817
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2683939991
Short name T9
Test name
Test status
Simulation time 132272949586 ps
CPU time 84.71 seconds
Started Jul 01 10:48:13 AM PDT 24
Finished Jul 01 10:49:38 AM PDT 24
Peak memory 201792 kb
Host smart-467f1283-f0fa-45c9-ba49-08175c9914db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683939991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.2683939991
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.4127276789
Short name T11
Test name
Test status
Simulation time 42524110114 ps
CPU time 52.8 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:50:07 AM PDT 24
Peak memory 201928 kb
Host smart-7d095d08-e02e-4ef9-9b21-1d2890440b8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127276789 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.4127276789
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2965793469
Short name T38
Test name
Test status
Simulation time 746186941224 ps
CPU time 250.01 seconds
Started Jul 01 10:48:55 AM PDT 24
Finished Jul 01 10:53:05 AM PDT 24
Peak memory 213572 kb
Host smart-7bde7fd5-16d8-4833-b750-bbc77d28f7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965793469 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2965793469
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1175818728
Short name T147
Test name
Test status
Simulation time 260849274525 ps
CPU time 175.57 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:51:11 AM PDT 24
Peak memory 218364 kb
Host smart-79dcf446-fbc4-4ade-a9a9-3ce623cc6952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175818728 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1175818728
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.474208980
Short name T76
Test name
Test status
Simulation time 39427767294 ps
CPU time 26.86 seconds
Started Jul 01 10:47:39 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 201584 kb
Host smart-f1947ccd-844a-48e5-9047-7e283f12bb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474208980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.474208980
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3328122436
Short name T18
Test name
Test status
Simulation time 25581016041 ps
CPU time 63.22 seconds
Started Jul 01 10:49:24 AM PDT 24
Finished Jul 01 10:50:28 AM PDT 24
Peak memory 201820 kb
Host smart-69a47e25-c316-47f0-9043-292c57d70a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328122436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.3328122436
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1142431045
Short name T273
Test name
Test status
Simulation time 42996716232 ps
CPU time 29.94 seconds
Started Jul 01 10:33:22 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 202004 kb
Host smart-71e25d4f-4ce5-4b19-b403-7f940529d08a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142431045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.1142431045
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3051421578
Short name T24
Test name
Test status
Simulation time 77054726637 ps
CPU time 201.7 seconds
Started Jul 01 10:48:59 AM PDT 24
Finished Jul 01 10:52:22 AM PDT 24
Peak memory 218104 kb
Host smart-8fd9658a-b94e-433e-b866-56b15c942ceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051421578 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3051421578
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.2877972672
Short name T31
Test name
Test status
Simulation time 111748333340 ps
CPU time 63.91 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:49:28 AM PDT 24
Peak memory 201640 kb
Host smart-81cc871c-0e9c-4eab-9f27-e965961c523d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877972672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.2877972672
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3566088212
Short name T156
Test name
Test status
Simulation time 196123014124 ps
CPU time 97.49 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:49:32 AM PDT 24
Peak memory 210244 kb
Host smart-ae874814-1e38-4661-babd-23da4207ad2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566088212 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3566088212
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.1678459062
Short name T60
Test name
Test status
Simulation time 14003175336 ps
CPU time 34.55 seconds
Started Jul 01 10:48:37 AM PDT 24
Finished Jul 01 10:49:13 AM PDT 24
Peak memory 201700 kb
Host smart-94b0cf0e-2c3d-4ebd-baf7-b6f54371e101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678459062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.1678459062
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.1794577310
Short name T75
Test name
Test status
Simulation time 1456917838267 ps
CPU time 428.86 seconds
Started Jul 01 10:48:57 AM PDT 24
Finished Jul 01 10:56:07 AM PDT 24
Peak memory 201756 kb
Host smart-bd307e41-cfdc-4cf5-a813-65e8fae50bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794577310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.1794577310
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.307559177
Short name T85
Test name
Test status
Simulation time 4254094373 ps
CPU time 2.81 seconds
Started Jul 01 10:48:19 AM PDT 24
Finished Jul 01 10:48:23 AM PDT 24
Peak memory 201408 kb
Host smart-8c9a88a7-a9d2-40eb-98b8-0c019d979c74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307559177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctr
l_edge_detect.307559177
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.635237444
Short name T83
Test name
Test status
Simulation time 3254910738 ps
CPU time 8.4 seconds
Started Jul 01 10:48:46 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 201364 kb
Host smart-8f328948-dde3-4c52-adb0-9f5e4cd6b8d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635237444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctr
l_edge_detect.635237444
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.4005594761
Short name T227
Test name
Test status
Simulation time 2034063214 ps
CPU time 2.17 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:10 AM PDT 24
Peak memory 201484 kb
Host smart-355cd4a8-297d-40e5-a7f9-9ac6f53e8aa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005594761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.4005594761
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.4287126625
Short name T335
Test name
Test status
Simulation time 45902311273 ps
CPU time 30.62 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:47 AM PDT 24
Peak memory 201736 kb
Host smart-087e3bec-c242-4989-b577-049552548ad2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287126625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.4287126625
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3076435719
Short name T231
Test name
Test status
Simulation time 180831842379 ps
CPU time 110.94 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:51:47 AM PDT 24
Peak memory 215128 kb
Host smart-d0c23d9b-441a-4fbb-a92e-5e71cc6c046c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076435719 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3076435719
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.726602921
Short name T275
Test name
Test status
Simulation time 63372428221 ps
CPU time 75.61 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:34:38 AM PDT 24
Peak memory 202264 kb
Host smart-10c2bbf1-3c57-449f-92b5-f6dd6e468457
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726602921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_bit_bash.726602921
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3688922061
Short name T55
Test name
Test status
Simulation time 41746226158 ps
CPU time 102.82 seconds
Started Jul 01 10:47:59 AM PDT 24
Finished Jul 01 10:49:43 AM PDT 24
Peak memory 201584 kb
Host smart-9f3e1965-1dd8-4c4b-80e2-18290d8e9466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688922061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3688922061
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3615694639
Short name T127
Test name
Test status
Simulation time 91382091051 ps
CPU time 61.73 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 201788 kb
Host smart-ab807004-abab-454f-8f5c-56bbb15f18de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615694639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.3615694639
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2984337091
Short name T269
Test name
Test status
Simulation time 2253623977 ps
CPU time 4.86 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 202044 kb
Host smart-535e0cde-b19f-47de-8e7f-0f151802d594
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984337091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2984337091
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.3900142463
Short name T46
Test name
Test status
Simulation time 12195261855 ps
CPU time 32.32 seconds
Started Jul 01 10:47:46 AM PDT 24
Finished Jul 01 10:48:19 AM PDT 24
Peak memory 201608 kb
Host smart-65aae857-fc7e-4d6e-a5f7-f2c966799e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900142463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.3900142463
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.4040622450
Short name T128
Test name
Test status
Simulation time 151761253035 ps
CPU time 186.8 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 201808 kb
Host smart-dfbe6d0e-b238-4825-ad9a-a0f6918725fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040622450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.4040622450
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1209723952
Short name T187
Test name
Test status
Simulation time 661136024041 ps
CPU time 60.61 seconds
Started Jul 01 10:49:02 AM PDT 24
Finished Jul 01 10:50:03 AM PDT 24
Peak memory 209920 kb
Host smart-bdd8396a-0341-450c-b3a4-eef15259fdc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209723952 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.1209723952
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1997872267
Short name T177
Test name
Test status
Simulation time 30928980697 ps
CPU time 37.3 seconds
Started Jul 01 10:48:41 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 210136 kb
Host smart-a5436997-49db-4b93-9dfa-08e2df0180cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997872267 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1997872267
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.271791016
Short name T14
Test name
Test status
Simulation time 13691115681 ps
CPU time 7.12 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201732 kb
Host smart-eae54ad7-0ae5-4fad-bd53-7ea1890af99b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271791016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_st
ress_all.271791016
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.2771726372
Short name T120
Test name
Test status
Simulation time 22082706737 ps
CPU time 12.44 seconds
Started Jul 01 10:47:52 AM PDT 24
Finished Jul 01 10:48:11 AM PDT 24
Peak memory 221300 kb
Host smart-a71b952e-6425-4866-b9c8-9179a9cc780b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771726372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.2771726372
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3728211016
Short name T262
Test name
Test status
Simulation time 107328612714 ps
CPU time 275.03 seconds
Started Jul 01 10:48:28 AM PDT 24
Finished Jul 01 10:53:04 AM PDT 24
Peak memory 201752 kb
Host smart-35a3c2b1-e85d-4d68-82af-32617cbfb434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728211016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.3728211016
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3972916134
Short name T32
Test name
Test status
Simulation time 100520478920 ps
CPU time 125.73 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:50:20 AM PDT 24
Peak memory 201752 kb
Host smart-992a5b81-3d5f-492c-9edc-e7ad7d8d5a39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972916134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.3972916134
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3129556892
Short name T352
Test name
Test status
Simulation time 82382329510 ps
CPU time 54.85 seconds
Started Jul 01 10:48:55 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 201780 kb
Host smart-dada0f81-52d9-4ac4-bb51-c23c11c9c482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129556892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.3129556892
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.4065074268
Short name T347
Test name
Test status
Simulation time 66503432741 ps
CPU time 167.5 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:52:05 AM PDT 24
Peak memory 201776 kb
Host smart-5c3b8a12-6a20-45c2-95d5-addc08f6f8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065074268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.4065074268
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3454549167
Short name T276
Test name
Test status
Simulation time 10016939077 ps
CPU time 7.42 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 202172 kb
Host smart-c41deea7-59d7-408a-b0bc-eff3fa0eb205
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454549167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.3454549167
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2633734280
Short name T334
Test name
Test status
Simulation time 95237718112 ps
CPU time 112.6 seconds
Started Jul 01 10:50:04 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 201848 kb
Host smart-7a902372-fe31-4585-a746-8c2bd0f49a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633734280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.2633734280
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3864509238
Short name T192
Test name
Test status
Simulation time 104242429546 ps
CPU time 235.86 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:53:12 AM PDT 24
Peak memory 201904 kb
Host smart-2baef63b-7ab5-4ba7-b8eb-45b481949f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864509238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.3864509238
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1499574970
Short name T12
Test name
Test status
Simulation time 114953505964 ps
CPU time 31.54 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:51 AM PDT 24
Peak memory 201832 kb
Host smart-ffedf6da-7815-453a-98a9-cc6473d04a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499574970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.1499574970
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1224659334
Short name T157
Test name
Test status
Simulation time 544630408087 ps
CPU time 107.05 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:49:45 AM PDT 24
Peak memory 210224 kb
Host smart-6c732dac-e43b-418a-a87f-6c61b9fea3a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224659334 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1224659334
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1471529125
Short name T123
Test name
Test status
Simulation time 908126714900 ps
CPU time 61.77 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:50:22 AM PDT 24
Peak memory 214040 kb
Host smart-0e5b00ab-3443-42f1-8b83-3d2d1d0f48d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471529125 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1471529125
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3158049163
Short name T41
Test name
Test status
Simulation time 82274557320 ps
CPU time 204.8 seconds
Started Jul 01 10:49:38 AM PDT 24
Finished Jul 01 10:53:04 AM PDT 24
Peak memory 201856 kb
Host smart-fcb821f8-146f-41ac-9f20-2780295b1f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158049163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.3158049163
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.910526129
Short name T93
Test name
Test status
Simulation time 73683541326 ps
CPU time 197.37 seconds
Started Jul 01 10:48:45 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 201576 kb
Host smart-efd0db58-47f3-49d3-a885-20dcb1495f88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910526129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_combo_detect.910526129
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.899105945
Short name T346
Test name
Test status
Simulation time 70161721296 ps
CPU time 99.08 seconds
Started Jul 01 10:49:52 AM PDT 24
Finished Jul 01 10:51:32 AM PDT 24
Peak memory 201768 kb
Host smart-2a23b32e-d181-4cac-8a62-a240fc6ee509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899105945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_wi
th_pre_cond.899105945
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.3478950205
Short name T7
Test name
Test status
Simulation time 3578321137 ps
CPU time 10.31 seconds
Started Jul 01 10:49:28 AM PDT 24
Finished Jul 01 10:49:39 AM PDT 24
Peak memory 201500 kb
Host smart-13ab6035-4c9e-41ec-b759-60e0d7a9d8ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478950205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.3478950205
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.917881133
Short name T142
Test name
Test status
Simulation time 196270922434 ps
CPU time 244.9 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:52:31 AM PDT 24
Peak memory 201816 kb
Host smart-21e304b1-a95d-4a4e-8496-e64ca1b35f03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917881133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_combo_detect.917881133
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.3919874883
Short name T250
Test name
Test status
Simulation time 22973070606 ps
CPU time 14.99 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:40 AM PDT 24
Peak memory 201764 kb
Host smart-b322df6a-7d90-47f8-bb1f-df993a5bac0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919874883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.3919874883
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1250999954
Short name T382
Test name
Test status
Simulation time 64627376547 ps
CPU time 37.85 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:57 AM PDT 24
Peak memory 218288 kb
Host smart-a778cd64-5273-44b1-9384-c844c18472e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250999954 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1250999954
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2411935944
Short name T367
Test name
Test status
Simulation time 85883656492 ps
CPU time 53.09 seconds
Started Jul 01 10:48:27 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201764 kb
Host smart-9f82fa33-2b87-451c-95e4-79fc22c5e112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411935944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.2411935944
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3749127473
Short name T366
Test name
Test status
Simulation time 41643650689 ps
CPU time 57.05 seconds
Started Jul 01 10:49:24 AM PDT 24
Finished Jul 01 10:50:22 AM PDT 24
Peak memory 201792 kb
Host smart-2d9c5f23-3187-4d87-866c-8828d9253c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749127473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.3749127473
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1603391941
Short name T40
Test name
Test status
Simulation time 64192704339 ps
CPU time 13.02 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 201852 kb
Host smart-79c5aac8-9aef-4553-85e7-088c92e3c1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603391941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.1603391941
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1828391488
Short name T863
Test name
Test status
Simulation time 42879132243 ps
CPU time 31.81 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 202192 kb
Host smart-ece84d86-e81d-4fcd-897d-64e53510d8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828391488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.1828391488
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.1851053096
Short name T230
Test name
Test status
Simulation time 3445782353 ps
CPU time 9.5 seconds
Started Jul 01 10:48:09 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201640 kb
Host smart-1b007946-a341-4c23-a57e-6d019ca67457
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851053096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.1851053096
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1891202250
Short name T293
Test name
Test status
Simulation time 22195473967 ps
CPU time 60.05 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:34:27 AM PDT 24
Peak memory 202128 kb
Host smart-e83fc071-4d5f-4fe5-8acc-e2d006465c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891202250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1891202250
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1607243188
Short name T332
Test name
Test status
Simulation time 6088189668 ps
CPU time 4.23 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 201952 kb
Host smart-5f9cd031-97a6-4cf0-8b26-b9e810feab52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607243188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1607243188
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2994291726
Short name T42
Test name
Test status
Simulation time 3321545299 ps
CPU time 9.14 seconds
Started Jul 01 10:48:34 AM PDT 24
Finished Jul 01 10:48:43 AM PDT 24
Peak memory 201544 kb
Host smart-3f8ebc07-4baa-4cac-9b36-c1260450374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994291726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.2
994291726
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1796394757
Short name T191
Test name
Test status
Simulation time 29636640866 ps
CPU time 62.69 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:49:28 AM PDT 24
Peak memory 209936 kb
Host smart-6d58dfcb-84ce-4024-97fa-cea750e3b786
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796394757 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1796394757
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3498533924
Short name T8
Test name
Test status
Simulation time 111670191691 ps
CPU time 279.97 seconds
Started Jul 01 10:47:43 AM PDT 24
Finished Jul 01 10:52:23 AM PDT 24
Peak memory 201808 kb
Host smart-6786983e-6bb7-4a59-8d97-8ee430934e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498533924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.3498533924
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.4240573183
Short name T259
Test name
Test status
Simulation time 152760028904 ps
CPU time 399.78 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:55:04 AM PDT 24
Peak memory 201776 kb
Host smart-de5aaffc-f88c-48f9-9916-3827c30eb036
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240573183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.4240573183
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3656233387
Short name T251
Test name
Test status
Simulation time 109206983316 ps
CPU time 65.76 seconds
Started Jul 01 10:49:59 AM PDT 24
Finished Jul 01 10:51:06 AM PDT 24
Peak memory 201828 kb
Host smart-b0014348-90ea-4308-9403-a061411210cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656233387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.3656233387
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.143784705
Short name T345
Test name
Test status
Simulation time 99578193828 ps
CPU time 134.05 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:51:57 AM PDT 24
Peak memory 201716 kb
Host smart-a82e888a-b2aa-45e3-b93d-f55123c85802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143784705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_wi
th_pre_cond.143784705
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2338262931
Short name T377
Test name
Test status
Simulation time 52262663801 ps
CPU time 37.97 seconds
Started Jul 01 10:49:25 AM PDT 24
Finished Jul 01 10:50:03 AM PDT 24
Peak memory 201812 kb
Host smart-656f245e-a315-467b-a349-d6bfb40eab9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338262931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.2338262931
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3334243375
Short name T362
Test name
Test status
Simulation time 42732917430 ps
CPU time 33.27 seconds
Started Jul 01 10:49:24 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 201732 kb
Host smart-623b90d9-79fe-4177-b46e-4e019a53b81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334243375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.3334243375
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2098105602
Short name T360
Test name
Test status
Simulation time 305243904362 ps
CPU time 386.09 seconds
Started Jul 01 10:49:25 AM PDT 24
Finished Jul 01 10:55:52 AM PDT 24
Peak memory 201836 kb
Host smart-738b2748-1780-4bd0-a111-f2380d0e877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098105602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.2098105602
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3757055541
Short name T280
Test name
Test status
Simulation time 2154421743 ps
CPU time 7.58 seconds
Started Jul 01 10:33:29 AM PDT 24
Finished Jul 01 10:33:37 AM PDT 24
Peak memory 210340 kb
Host smart-84110e39-f686-4d48-a95d-6e07024067f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757055541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.3757055541
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.4231952539
Short name T172
Test name
Test status
Simulation time 3647678538 ps
CPU time 5.08 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201492 kb
Host smart-83334544-fdfa-490b-935f-5721df45fbf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231952539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.4231952539
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.786404704
Short name T811
Test name
Test status
Simulation time 2604441474 ps
CPU time 3.81 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:29 AM PDT 24
Peak memory 201800 kb
Host smart-7596afbd-a583-430b-836a-7a31f5b5006b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786404704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_aliasing.786404704
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3083044890
Short name T323
Test name
Test status
Simulation time 36133598561 ps
CPU time 86.33 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:34:40 AM PDT 24
Peak memory 202436 kb
Host smart-281dafb9-5fce-433b-828f-b1b9eb1a68e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083044890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.3083044890
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1236603578
Short name T328
Test name
Test status
Simulation time 4011488193 ps
CPU time 10.96 seconds
Started Jul 01 10:33:26 AM PDT 24
Finished Jul 01 10:33:38 AM PDT 24
Peak memory 201984 kb
Host smart-1b65bbe9-7d98-41c8-886d-8965688bd183
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236603578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.1236603578
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.498121398
Short name T876
Test name
Test status
Simulation time 2896744829 ps
CPU time 1.45 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:19 AM PDT 24
Peak memory 210140 kb
Host smart-43fc2755-9ea1-4f49-a4be-e8b911d76499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498121398 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.498121398
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1702890884
Short name T895
Test name
Test status
Simulation time 2030921651 ps
CPU time 5.89 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:17 AM PDT 24
Peak memory 201752 kb
Host smart-c76cb48c-3256-4b8d-9bae-050cb8408c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702890884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1702890884
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2986983257
Short name T884
Test name
Test status
Simulation time 2043168633 ps
CPU time 1.79 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:15 AM PDT 24
Peak memory 201592 kb
Host smart-e1cad170-9e2e-4c77-979e-15da4cc35a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986983257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.2986983257
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.330245028
Short name T816
Test name
Test status
Simulation time 8350203136 ps
CPU time 6.06 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 202144 kb
Host smart-d781ad27-6407-4ebc-9a38-a6a3f967fb62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330245028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.330245028
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.281660468
Short name T283
Test name
Test status
Simulation time 2486851688 ps
CPU time 4.19 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 202116 kb
Host smart-09504c0b-56f0-4b46-a806-c4c21405e1f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281660468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors
.281660468
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3388778666
Short name T908
Test name
Test status
Simulation time 42896617303 ps
CPU time 30.5 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 202140 kb
Host smart-bc74bc21-b2fb-4443-9c37-61abc5f3cd91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388778666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.3388778666
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2320311400
Short name T882
Test name
Test status
Simulation time 2505958681 ps
CPU time 8.32 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 201836 kb
Host smart-e43d58e8-0e92-4b31-a66b-e6339d1866c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320311400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.2320311400
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4202384055
Short name T903
Test name
Test status
Simulation time 20572636459 ps
CPU time 19.47 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 202064 kb
Host smart-ab631ed8-6009-47e0-89fa-02a9b1faa5ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202384055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.4202384055
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.866782258
Short name T821
Test name
Test status
Simulation time 4035952577 ps
CPU time 5.95 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 201840 kb
Host smart-d33768b5-0db5-4b3c-804c-cbf3a8a51d5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866782258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_hw_reset.866782258
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2358897692
Short name T909
Test name
Test status
Simulation time 2117593652 ps
CPU time 5.89 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 217524 kb
Host smart-2f431b38-26d7-4404-8791-91e0831d00f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358897692 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2358897692
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2288397478
Short name T29
Test name
Test status
Simulation time 2062829351 ps
CPU time 6.26 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 201768 kb
Host smart-3a0cbe09-fd7e-4f46-a740-57ff07ba5a5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288397478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2288397478
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2789157287
Short name T831
Test name
Test status
Simulation time 2010471758 ps
CPU time 5.63 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:31 AM PDT 24
Peak memory 201556 kb
Host smart-1fa2742e-d13f-448d-b1e9-06c4458364d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789157287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.2789157287
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1344793895
Short name T292
Test name
Test status
Simulation time 2048176759 ps
CPU time 6.49 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 202108 kb
Host smart-09a14d4e-2e64-40dc-a20c-3f3f38f92b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344793895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.1344793895
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1633928835
Short name T838
Test name
Test status
Simulation time 22487096774 ps
CPU time 15.56 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:33:35 AM PDT 24
Peak memory 202168 kb
Host smart-d0e29cad-573c-4873-aa07-e87f6d2369d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633928835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.1633928835
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2741069655
Short name T815
Test name
Test status
Simulation time 2057441732 ps
CPU time 6.09 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:32 AM PDT 24
Peak memory 201796 kb
Host smart-79cb9819-ec40-4022-900c-ac25d0a414c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741069655 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2741069655
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.356230572
Short name T855
Test name
Test status
Simulation time 2172907050 ps
CPU time 1.21 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 201880 kb
Host smart-50d5b0b1-8109-4bec-a029-3978758a8013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356230572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_r
w.356230572
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3418327130
Short name T800
Test name
Test status
Simulation time 2015444049 ps
CPU time 5.8 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:33:32 AM PDT 24
Peak memory 201504 kb
Host smart-649353f5-1a66-4838-8492-5c24b5093180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418327130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.3418327130
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1946251770
Short name T808
Test name
Test status
Simulation time 4587964833 ps
CPU time 15.6 seconds
Started Jul 01 10:33:32 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 202104 kb
Host smart-ea4d4c28-cd24-46d2-8cdc-929aa51df31f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946251770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.1946251770
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.4272487676
Short name T897
Test name
Test status
Simulation time 42602777691 ps
CPU time 58.64 seconds
Started Jul 01 10:33:30 AM PDT 24
Finished Jul 01 10:34:29 AM PDT 24
Peak memory 202136 kb
Host smart-f095474e-0c8c-4301-a7f0-2c9de73b4aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272487676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.4272487676
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3778275043
Short name T801
Test name
Test status
Simulation time 2071278087 ps
CPU time 5.73 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:31 AM PDT 24
Peak memory 201620 kb
Host smart-b80b0e8e-c3e2-4682-852d-cb79638968cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778275043 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3778275043
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2916260879
Short name T318
Test name
Test status
Simulation time 2047692114 ps
CPU time 6.01 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 201860 kb
Host smart-1b0c6fce-7e40-4059-90b3-2968f69c1498
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916260879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.2916260879
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3593350294
Short name T913
Test name
Test status
Simulation time 2027131235 ps
CPU time 3.16 seconds
Started Jul 01 10:33:35 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 201908 kb
Host smart-2adbffe7-c42c-45c7-986c-6a6828415461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593350294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.3593350294
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2740670887
Short name T20
Test name
Test status
Simulation time 4645625047 ps
CPU time 5.54 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 202160 kb
Host smart-32526c26-24f3-4dc1-971e-d09142a73de2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740670887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.2740670887
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2363480343
Short name T30
Test name
Test status
Simulation time 42522261779 ps
CPU time 53.85 seconds
Started Jul 01 10:33:21 AM PDT 24
Finished Jul 01 10:34:16 AM PDT 24
Peak memory 202092 kb
Host smart-e6b49817-279f-4b84-b498-aa46e4938ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363480343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.2363480343
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3905577817
Short name T847
Test name
Test status
Simulation time 2216111102 ps
CPU time 2.48 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 201996 kb
Host smart-71bc715b-4b30-46cf-a44b-bb4e5962f754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905577817 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3905577817
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.57190290
Short name T874
Test name
Test status
Simulation time 2117233717 ps
CPU time 2.15 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 201864 kb
Host smart-0e22abd6-5623-4d6a-89e2-f99a0306725c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57190290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw
.57190290
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.747191064
Short name T837
Test name
Test status
Simulation time 2012192830 ps
CPU time 5.73 seconds
Started Jul 01 10:33:31 AM PDT 24
Finished Jul 01 10:33:37 AM PDT 24
Peak memory 201596 kb
Host smart-f91d62cd-92c5-4d0f-8b94-10c3ca25929d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747191064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_tes
t.747191064
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.4063295698
Short name T818
Test name
Test status
Simulation time 8634178893 ps
CPU time 12.13 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 202168 kb
Host smart-8fb9d0e9-b637-49ee-ba83-1a4672607552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063295698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.4063295698
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3946411288
Short name T862
Test name
Test status
Simulation time 2041174415 ps
CPU time 7.33 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:32 AM PDT 24
Peak memory 202052 kb
Host smart-4757a180-4091-468f-888d-1e3d9c4a22a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946411288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.3946411288
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2204370211
Short name T290
Test name
Test status
Simulation time 22210034819 ps
CPU time 59.24 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:34:16 AM PDT 24
Peak memory 202156 kb
Host smart-1579102a-8209-4c29-925b-49ba4b060f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204370211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.2204370211
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1336329521
Short name T904
Test name
Test status
Simulation time 2043076108 ps
CPU time 6.19 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:52 AM PDT 24
Peak memory 201852 kb
Host smart-524da843-1988-4cd9-b7ed-3aff047c93a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336329521 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1336329521
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.496248873
Short name T326
Test name
Test status
Simulation time 2253701068 ps
CPU time 1.47 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 201952 kb
Host smart-9cf7dd5b-e467-470e-a3e4-915ef597f2d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496248873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_r
w.496248873
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3598836993
Short name T858
Test name
Test status
Simulation time 2031313334 ps
CPU time 1.91 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 201624 kb
Host smart-c4ec8479-5410-44aa-90d1-1c412b712fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598836993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.3598836993
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3357188805
Short name T331
Test name
Test status
Simulation time 5381867489 ps
CPU time 21.21 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 201976 kb
Host smart-956ebb91-01bb-4b45-b580-c30d01ef1c84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357188805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.3357188805
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.187668306
Short name T281
Test name
Test status
Simulation time 2100602345 ps
CPU time 2.8 seconds
Started Jul 01 10:33:41 AM PDT 24
Finished Jul 01 10:33:45 AM PDT 24
Peak memory 202024 kb
Host smart-6cf3a67a-4d37-42dd-88ec-114ed2b32bd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187668306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.187668306
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1095849194
Short name T877
Test name
Test status
Simulation time 2091753694 ps
CPU time 6.13 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 210224 kb
Host smart-489ecc59-e812-4ac4-a9e5-bed656a5b27d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095849194 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1095849194
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.640578099
Short name T319
Test name
Test status
Simulation time 2175179446 ps
CPU time 1.68 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 201860 kb
Host smart-e8cb4f6f-7cb8-4f76-883f-aaad0a33f854
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640578099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.640578099
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.525204071
Short name T843
Test name
Test status
Simulation time 2036310681 ps
CPU time 1.59 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 201628 kb
Host smart-40c4e99e-67f4-48af-b482-52f6c74bddf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525204071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_tes
t.525204071
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2250656986
Short name T807
Test name
Test status
Simulation time 4489637975 ps
CPU time 8.57 seconds
Started Jul 01 10:33:36 AM PDT 24
Finished Jul 01 10:33:45 AM PDT 24
Peak memory 202136 kb
Host smart-8256cd87-dc5c-41a7-8f16-49e9d157a320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250656986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.2250656986
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.245139581
Short name T880
Test name
Test status
Simulation time 2150467146 ps
CPU time 2.44 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 210376 kb
Host smart-1122e968-d9a1-42c7-ba71-93f7af1f9135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245139581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_error
s.245139581
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.282274360
Short name T829
Test name
Test status
Simulation time 2126894685 ps
CPU time 3.73 seconds
Started Jul 01 10:33:49 AM PDT 24
Finished Jul 01 10:33:55 AM PDT 24
Peak memory 202268 kb
Host smart-1ad4aa75-745b-4a5a-9358-d8676bb17ade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282274360 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.282274360
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.288592743
Short name T324
Test name
Test status
Simulation time 2059502389 ps
CPU time 6.23 seconds
Started Jul 01 10:33:27 AM PDT 24
Finished Jul 01 10:33:34 AM PDT 24
Peak memory 201848 kb
Host smart-a565829d-fd60-487e-83b0-1238f49c6321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288592743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_r
w.288592743
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.469127136
Short name T833
Test name
Test status
Simulation time 2013360260 ps
CPU time 6.1 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:52 AM PDT 24
Peak memory 201596 kb
Host smart-d88b2d21-84c8-4a00-bbc8-56381fe0e103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469127136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_tes
t.469127136
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.847902105
Short name T812
Test name
Test status
Simulation time 7499373916 ps
CPU time 9.95 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 202160 kb
Host smart-5489873c-7056-4cd1-a764-3bd480f96e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847902105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.sysrst_ctrl_same_csr_outstanding.847902105
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2633085303
Short name T282
Test name
Test status
Simulation time 2154756151 ps
CPU time 7.67 seconds
Started Jul 01 10:33:43 AM PDT 24
Finished Jul 01 10:33:52 AM PDT 24
Peak memory 210400 kb
Host smart-0aef8b69-12c8-4b95-ad89-f625fc7398c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633085303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.2633085303
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1498297630
Short name T349
Test name
Test status
Simulation time 42911990652 ps
CPU time 26.43 seconds
Started Jul 01 10:33:26 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 202184 kb
Host smart-1e115204-38ba-4a39-b935-d9922c703121
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498297630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.1498297630
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3698335520
Short name T848
Test name
Test status
Simulation time 2135851142 ps
CPU time 2.01 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 201916 kb
Host smart-ebbe62fa-0349-441b-8ce2-bcd17e96f30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698335520 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3698335520
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2170138638
Short name T321
Test name
Test status
Simulation time 2087497775 ps
CPU time 2.18 seconds
Started Jul 01 10:33:36 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 201752 kb
Host smart-547fbeb1-7fca-4be6-9d27-8374c83e5f31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170138638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.2170138638
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2805657221
Short name T797
Test name
Test status
Simulation time 2040542028 ps
CPU time 1.83 seconds
Started Jul 01 10:33:26 AM PDT 24
Finished Jul 01 10:33:29 AM PDT 24
Peak memory 201540 kb
Host smart-c7b89944-2d51-49a8-9c3b-03660652a898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805657221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.2805657221
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2059610187
Short name T22
Test name
Test status
Simulation time 4603740990 ps
CPU time 3.67 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:29 AM PDT 24
Peak memory 201976 kb
Host smart-5b83267b-2efb-40a7-b953-d85e123361f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059610187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2059610187
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.381572902
Short name T844
Test name
Test status
Simulation time 2031064043 ps
CPU time 6.6 seconds
Started Jul 01 10:33:26 AM PDT 24
Finished Jul 01 10:33:33 AM PDT 24
Peak memory 202044 kb
Host smart-63159059-fd3f-4463-897a-58636e5b466a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381572902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_error
s.381572902
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2394972929
Short name T828
Test name
Test status
Simulation time 42652751625 ps
CPU time 56.9 seconds
Started Jul 01 10:33:36 AM PDT 24
Finished Jul 01 10:34:34 AM PDT 24
Peak memory 202208 kb
Host smart-41f32b1f-a834-4a02-9443-4a82dc5bf31a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394972929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.2394972929
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1667151473
Short name T820
Test name
Test status
Simulation time 2129677894 ps
CPU time 6.47 seconds
Started Jul 01 10:33:22 AM PDT 24
Finished Jul 01 10:33:29 AM PDT 24
Peak memory 201896 kb
Host smart-cda40523-66af-4074-b809-590dd23acbf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667151473 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1667151473
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1318499159
Short name T317
Test name
Test status
Simulation time 2054117764 ps
CPU time 6.15 seconds
Started Jul 01 10:33:28 AM PDT 24
Finished Jul 01 10:33:35 AM PDT 24
Peak memory 201860 kb
Host smart-cd5bbcd6-48dc-4695-94b4-c0e8a2b35358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318499159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.1318499159
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2007783669
Short name T814
Test name
Test status
Simulation time 2015352585 ps
CPU time 5.67 seconds
Started Jul 01 10:33:21 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 201604 kb
Host smart-fcd34cf3-0e9a-4d8c-8b33-ea546436b24b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007783669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.2007783669
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1721912031
Short name T871
Test name
Test status
Simulation time 4938901196 ps
CPU time 13.34 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:34:02 AM PDT 24
Peak memory 202140 kb
Host smart-04e9ca0e-70cc-4b2a-8781-1806858b936a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721912031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.1721912031
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2342563819
Short name T845
Test name
Test status
Simulation time 2049210990 ps
CPU time 6.27 seconds
Started Jul 01 10:33:29 AM PDT 24
Finished Jul 01 10:33:36 AM PDT 24
Peak memory 202000 kb
Host smart-508e353c-6ab8-4cbe-b22e-62692e511302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342563819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.2342563819
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.270707033
Short name T885
Test name
Test status
Simulation time 42513474161 ps
CPU time 33.99 seconds
Started Jul 01 10:33:28 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 202120 kb
Host smart-9ca33edd-c8e8-453e-be26-5c99595d4c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270707033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.270707033
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.668456428
Short name T887
Test name
Test status
Simulation time 2083986313 ps
CPU time 2.33 seconds
Started Jul 01 10:33:49 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 201796 kb
Host smart-0e5d3200-4343-4b64-82af-d3d72e59a0b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668456428 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.668456428
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.742406829
Short name T325
Test name
Test status
Simulation time 2109441929 ps
CPU time 2.25 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 201844 kb
Host smart-cf6965a9-0fbf-4afe-8f44-76bb398521ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742406829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_r
w.742406829
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2929218512
Short name T802
Test name
Test status
Simulation time 2050690024 ps
CPU time 1.22 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 201724 kb
Host smart-dc8ed5af-e7cd-40d6-aadd-50881e65084c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929218512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2929218512
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3839362078
Short name T841
Test name
Test status
Simulation time 9459687715 ps
CPU time 10.46 seconds
Started Jul 01 10:33:30 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 202088 kb
Host smart-b5d392a0-f951-4acc-b74b-241eda873dbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839362078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.3839362078
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2827846031
Short name T284
Test name
Test status
Simulation time 2033315529 ps
CPU time 6.74 seconds
Started Jul 01 10:33:28 AM PDT 24
Finished Jul 01 10:33:35 AM PDT 24
Peak memory 202020 kb
Host smart-d2421aa0-f9cf-4b04-a767-c7032f901240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827846031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.2827846031
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3986550116
Short name T859
Test name
Test status
Simulation time 42388208916 ps
CPU time 58.71 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:34:24 AM PDT 24
Peak memory 202152 kb
Host smart-c4eeb293-82f4-432d-b919-73d2e450c593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986550116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.3986550116
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.865134510
Short name T826
Test name
Test status
Simulation time 2265483753 ps
CPU time 2.33 seconds
Started Jul 01 10:33:29 AM PDT 24
Finished Jul 01 10:33:31 AM PDT 24
Peak memory 201912 kb
Host smart-930de775-c2f9-459c-a0fb-1298a6072665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865134510 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.865134510
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3761809521
Short name T856
Test name
Test status
Simulation time 2038450277 ps
CPU time 6.16 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 201688 kb
Host smart-ebd123f7-e66b-4f1e-a909-86b3b30e9058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761809521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.3761809521
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.709405082
Short name T799
Test name
Test status
Simulation time 2044106335 ps
CPU time 1.91 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 201732 kb
Host smart-f1b251ba-f35a-4e68-954a-5adfd9a58335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709405082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_tes
t.709405082
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2049213849
Short name T851
Test name
Test status
Simulation time 5138411344 ps
CPU time 7 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 202156 kb
Host smart-986e390f-f4bc-4279-a78a-175afb29c62c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049213849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.2049213849
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3178380719
Short name T852
Test name
Test status
Simulation time 2110438592 ps
CPU time 7.44 seconds
Started Jul 01 10:33:33 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 202344 kb
Host smart-08c9085f-46ff-4d17-a710-133af00e65f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178380719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3178380719
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1462835902
Short name T867
Test name
Test status
Simulation time 42945915033 ps
CPU time 30.05 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 202116 kb
Host smart-f87f7033-dc14-4fca-97bf-9f8f0d953c68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462835902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.1462835902
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4011524450
Short name T830
Test name
Test status
Simulation time 2697626850 ps
CPU time 4.3 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 202416 kb
Host smart-8844e824-02a8-4297-a59b-41c255096f2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011524450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.4011524450
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.4275406728
Short name T900
Test name
Test status
Simulation time 74779957484 ps
CPU time 433.9 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:40:30 AM PDT 24
Peak memory 202064 kb
Host smart-79fb801a-7c4d-4b93-bc03-fe40f7cbc4dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275406728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.4275406728
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4020555645
Short name T905
Test name
Test status
Simulation time 4015329384 ps
CPU time 7.31 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 201844 kb
Host smart-d8f6851e-a0da-4bd1-863c-87e055c34452
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020555645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.4020555645
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3222266922
Short name T806
Test name
Test status
Simulation time 2064754690 ps
CPU time 4.63 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 201824 kb
Host smart-a2bcd365-a1f4-48b1-b785-80ab07db86c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222266922 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3222266922
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3016377536
Short name T316
Test name
Test status
Simulation time 2088324279 ps
CPU time 3.42 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 201780 kb
Host smart-42e6d440-c99a-40b3-bd53-41335149b0d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016377536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3016377536
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3548788505
Short name T822
Test name
Test status
Simulation time 2042531335 ps
CPU time 1.64 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:33:19 AM PDT 24
Peak memory 201612 kb
Host smart-9224ff56-ed9b-4033-9dfe-412d3e796a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548788505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.3548788505
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2508738662
Short name T901
Test name
Test status
Simulation time 5329709063 ps
CPU time 7.08 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 202116 kb
Host smart-5068b564-60cd-4897-af8d-39c7eb976d97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508738662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.2508738662
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1081478543
Short name T287
Test name
Test status
Simulation time 2135975850 ps
CPU time 3.3 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 201952 kb
Host smart-893ed192-3eb0-4b87-ab22-dcab0f2224f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081478543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.1081478543
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1803800392
Short name T289
Test name
Test status
Simulation time 23412133500 ps
CPU time 5.75 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 202212 kb
Host smart-aac54e66-20da-4f9d-a9ad-7a2bd19334c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803800392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1803800392
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2848321683
Short name T864
Test name
Test status
Simulation time 2013758133 ps
CPU time 5.96 seconds
Started Jul 01 10:33:31 AM PDT 24
Finished Jul 01 10:33:37 AM PDT 24
Peak memory 201676 kb
Host smart-fc1b3292-c305-4393-bf8f-c1bd753db1cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848321683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2848321683
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2234192089
Short name T825
Test name
Test status
Simulation time 2201244360 ps
CPU time 0.9 seconds
Started Jul 01 10:33:31 AM PDT 24
Finished Jul 01 10:33:33 AM PDT 24
Peak memory 201664 kb
Host smart-44321562-f619-477d-8eb8-f9d52bbf73e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234192089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.2234192089
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2683155036
Short name T798
Test name
Test status
Simulation time 2042741978 ps
CPU time 2.03 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 201632 kb
Host smart-ca9b099f-48d8-40f7-a503-f5aadb0380d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683155036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2683155036
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1251196960
Short name T875
Test name
Test status
Simulation time 2012956780 ps
CPU time 5.49 seconds
Started Jul 01 10:33:34 AM PDT 24
Finished Jul 01 10:33:40 AM PDT 24
Peak memory 201752 kb
Host smart-4240b18d-78e5-4c5c-8794-076e7dc26532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251196960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.1251196960
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1082319248
Short name T824
Test name
Test status
Simulation time 2022434597 ps
CPU time 3.17 seconds
Started Jul 01 10:33:48 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 201480 kb
Host smart-4166837e-ad15-4c8c-9d6c-9a1996cd0c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082319248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1082319248
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.37118171
Short name T899
Test name
Test status
Simulation time 2014155703 ps
CPU time 5.84 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:55 AM PDT 24
Peak memory 201616 kb
Host smart-9c216801-60d9-4d9b-8356-be73e5639869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37118171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test
.37118171
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3479689254
Short name T861
Test name
Test status
Simulation time 2014194122 ps
CPU time 5.85 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 201628 kb
Host smart-010fbfb6-8a51-491d-9190-9f3166361a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479689254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3479689254
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2463453381
Short name T854
Test name
Test status
Simulation time 2011945786 ps
CPU time 5.74 seconds
Started Jul 01 10:33:42 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 201600 kb
Host smart-ae548315-4efa-4339-91ec-5cbd35185f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463453381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.2463453381
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.671653838
Short name T886
Test name
Test status
Simulation time 2011861648 ps
CPU time 5.32 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 201548 kb
Host smart-6bbc3497-e441-4266-83d8-125b8d9af949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671653838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_tes
t.671653838
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4099919
Short name T817
Test name
Test status
Simulation time 2075653549 ps
CPU time 1.14 seconds
Started Jul 01 10:33:31 AM PDT 24
Finished Jul 01 10:33:33 AM PDT 24
Peak memory 201620 kb
Host smart-5cee166f-1396-4b52-bdf4-c4faff91f740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.4099919
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.380838137
Short name T889
Test name
Test status
Simulation time 2889462845 ps
CPU time 10.15 seconds
Started Jul 01 10:33:11 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 202136 kb
Host smart-cb9264c8-1c81-420f-91ae-18f0a30043a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380838137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.380838137
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2669660094
Short name T881
Test name
Test status
Simulation time 2135556754 ps
CPU time 6.46 seconds
Started Jul 01 10:33:25 AM PDT 24
Finished Jul 01 10:33:33 AM PDT 24
Peak memory 201888 kb
Host smart-6a9104dc-ebdd-4e2e-86e2-73c0f1227c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669660094 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2669660094
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.680068037
Short name T846
Test name
Test status
Simulation time 2147964117 ps
CPU time 2.33 seconds
Started Jul 01 10:33:09 AM PDT 24
Finished Jul 01 10:33:12 AM PDT 24
Peak memory 201888 kb
Host smart-f15cd279-36d1-4fa8-9c36-8897ce2cb5e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680068037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw
.680068037
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.4153454383
Short name T891
Test name
Test status
Simulation time 2018290475 ps
CPU time 3.78 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 201640 kb
Host smart-817cf305-fde1-41e8-a4bc-90c3ad24ce5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153454383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.4153454383
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.4017965055
Short name T870
Test name
Test status
Simulation time 8468829463 ps
CPU time 4.06 seconds
Started Jul 01 10:33:23 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 202164 kb
Host smart-ce9017d6-0e16-481e-b132-b60618c951fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017965055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.4017965055
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1728568194
Short name T834
Test name
Test status
Simulation time 2109291509 ps
CPU time 7.45 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 201956 kb
Host smart-0c4e499f-4227-4418-8aa6-16370c26ce2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728568194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.1728568194
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2098587117
Short name T869
Test name
Test status
Simulation time 22186341978 ps
CPU time 54.02 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 202064 kb
Host smart-fdb69461-59df-4e1c-b604-d174a013c3f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098587117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.2098587117
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3567738200
Short name T850
Test name
Test status
Simulation time 2036651303 ps
CPU time 1.91 seconds
Started Jul 01 10:33:33 AM PDT 24
Finished Jul 01 10:33:36 AM PDT 24
Peak memory 201592 kb
Host smart-3d63600d-a043-4b50-bc81-9dee75f12eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567738200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3567738200
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.4090752276
Short name T809
Test name
Test status
Simulation time 2033998617 ps
CPU time 1.84 seconds
Started Jul 01 10:33:26 AM PDT 24
Finished Jul 01 10:33:29 AM PDT 24
Peak memory 201680 kb
Host smart-0c159c10-2a54-496f-8fe4-62ced881479c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090752276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.4090752276
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3632920447
Short name T819
Test name
Test status
Simulation time 2015279871 ps
CPU time 5.43 seconds
Started Jul 01 10:33:43 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 201552 kb
Host smart-d5934e00-49d3-41a6-8a6b-e85560579d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632920447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.3632920447
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1747835357
Short name T835
Test name
Test status
Simulation time 2017154998 ps
CPU time 3.24 seconds
Started Jul 01 10:33:32 AM PDT 24
Finished Jul 01 10:33:36 AM PDT 24
Peak memory 201564 kb
Host smart-13f2b912-1f14-4965-8dcd-9bf6227056b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747835357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.1747835357
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2680930817
Short name T849
Test name
Test status
Simulation time 2013747387 ps
CPU time 6.19 seconds
Started Jul 01 10:33:32 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 201580 kb
Host smart-01e3c9f5-7577-40d0-9150-f924d483eb6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680930817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.2680930817
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.4011441390
Short name T910
Test name
Test status
Simulation time 2010333877 ps
CPU time 5.87 seconds
Started Jul 01 10:33:42 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 201564 kb
Host smart-092cc9bd-2928-4c12-9428-22e836e71186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011441390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.4011441390
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1564079221
Short name T810
Test name
Test status
Simulation time 2018702413 ps
CPU time 3.65 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 201724 kb
Host smart-be8abdfb-7b5d-411b-a3e2-7f743a3ae127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564079221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.1564079221
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1402180024
Short name T868
Test name
Test status
Simulation time 2079909937 ps
CPU time 1.25 seconds
Started Jul 01 10:33:34 AM PDT 24
Finished Jul 01 10:33:36 AM PDT 24
Peak memory 201624 kb
Host smart-eff3a0f0-c6bf-4184-80ee-41531711af6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402180024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.1402180024
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.401687185
Short name T796
Test name
Test status
Simulation time 2085927322 ps
CPU time 1.17 seconds
Started Jul 01 10:33:37 AM PDT 24
Finished Jul 01 10:33:38 AM PDT 24
Peak memory 201560 kb
Host smart-875866ed-ee06-441f-adc6-4cda90e9bfb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401687185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_tes
t.401687185
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.356857030
Short name T912
Test name
Test status
Simulation time 2030311684 ps
CPU time 1.86 seconds
Started Jul 01 10:33:30 AM PDT 24
Finished Jul 01 10:33:32 AM PDT 24
Peak memory 201668 kb
Host smart-fd8c4c7b-1fd8-45f6-a162-76a954b1f11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356857030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_tes
t.356857030
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1875324243
Short name T853
Test name
Test status
Simulation time 3201935645 ps
CPU time 5.7 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 202076 kb
Host smart-525c275e-5d3a-41c3-8828-a78a1034ec1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875324243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.1875324243
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2642391951
Short name T329
Test name
Test status
Simulation time 45378307211 ps
CPU time 27.4 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 202132 kb
Host smart-fc1c1d2a-698d-40f6-8a7a-cbaaa298af4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642391951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2642391951
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.227429457
Short name T320
Test name
Test status
Simulation time 6045896522 ps
CPU time 4.46 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 201832 kb
Host smart-d588bd02-6d9e-4ef1-8d79-8041b3c907a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227429457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.227429457
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3646452932
Short name T314
Test name
Test status
Simulation time 2118122515 ps
CPU time 2.09 seconds
Started Jul 01 10:33:23 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 202080 kb
Host smart-cb317cc5-4e1f-4459-b90e-8ed3dc6bbce6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646452932 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3646452932
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1543816750
Short name T892
Test name
Test status
Simulation time 2032807664 ps
CPU time 6.11 seconds
Started Jul 01 10:33:32 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 201948 kb
Host smart-6027515c-8b43-4b5a-b271-e42b2811132f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543816750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.1543816750
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1114311567
Short name T879
Test name
Test status
Simulation time 2040892349 ps
CPU time 1.54 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 201360 kb
Host smart-7c5c26a2-34e1-4e84-8d8d-ef2ad6871c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114311567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.1114311567
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3180463308
Short name T857
Test name
Test status
Simulation time 4170770554 ps
CPU time 10.9 seconds
Started Jul 01 10:33:12 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 202104 kb
Host smart-ccbd9cbf-e84c-46e2-a96e-182ed8b47755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180463308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.3180463308
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.837197268
Short name T839
Test name
Test status
Simulation time 2108330211 ps
CPU time 7.13 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 202116 kb
Host smart-978740f3-9040-4cac-b0f1-bfc157ec3251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837197268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors
.837197268
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.4023953918
Short name T285
Test name
Test status
Simulation time 42449097627 ps
CPU time 110.3 seconds
Started Jul 01 10:33:10 AM PDT 24
Finished Jul 01 10:35:01 AM PDT 24
Peak memory 202124 kb
Host smart-12645609-ccaa-42a7-9bf8-ef9ef71e784a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023953918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.4023953918
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1583042255
Short name T894
Test name
Test status
Simulation time 2018485547 ps
CPU time 2.94 seconds
Started Jul 01 10:33:22 AM PDT 24
Finished Jul 01 10:33:31 AM PDT 24
Peak memory 201752 kb
Host smart-139dd0ad-81bc-4442-aa25-7a03a9c41c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583042255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1583042255
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.575720637
Short name T898
Test name
Test status
Simulation time 2019285481 ps
CPU time 5.44 seconds
Started Jul 01 10:33:31 AM PDT 24
Finished Jul 01 10:33:37 AM PDT 24
Peak memory 201676 kb
Host smart-cf59f27a-8aca-4e1e-95ea-eb1a87c797d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575720637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_tes
t.575720637
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1937425900
Short name T813
Test name
Test status
Simulation time 2039000888 ps
CPU time 1.88 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:43 AM PDT 24
Peak memory 201680 kb
Host smart-4ab7c684-7620-4cff-a90a-79d87ce0b433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937425900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1937425900
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4191773150
Short name T911
Test name
Test status
Simulation time 2016451060 ps
CPU time 4.46 seconds
Started Jul 01 10:33:43 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 201600 kb
Host smart-9e794cc0-38b8-4829-8c0e-4c255ff65595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191773150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.4191773150
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2297358435
Short name T907
Test name
Test status
Simulation time 2037315489 ps
CPU time 1.87 seconds
Started Jul 01 10:33:41 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 201572 kb
Host smart-6c680310-de25-43de-9d34-100e55a7fa65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297358435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2297358435
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1581485331
Short name T866
Test name
Test status
Simulation time 2010669279 ps
CPU time 5.99 seconds
Started Jul 01 10:33:39 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 201584 kb
Host smart-d553d680-7f3b-40c5-a0b7-c4b6c06efc12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581485331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1581485331
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2276210958
Short name T872
Test name
Test status
Simulation time 2019859779 ps
CPU time 2.93 seconds
Started Jul 01 10:33:42 AM PDT 24
Finished Jul 01 10:33:45 AM PDT 24
Peak memory 201552 kb
Host smart-34c62400-d66c-4673-af4f-133b8ff03ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276210958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.2276210958
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3347542813
Short name T890
Test name
Test status
Simulation time 2016076887 ps
CPU time 5.34 seconds
Started Jul 01 10:33:43 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 201636 kb
Host smart-6cfb6c89-15eb-4cd6-ab89-4ca86f034c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347542813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3347542813
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3507606814
Short name T832
Test name
Test status
Simulation time 2038031555 ps
CPU time 1.86 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 201556 kb
Host smart-d8fde2e9-2c8c-4d63-8263-f4e8ae9649a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507606814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.3507606814
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1147660565
Short name T804
Test name
Test status
Simulation time 2039616601 ps
CPU time 2.17 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 201724 kb
Host smart-da307259-d5d3-48bc-9c3d-d8332aa15fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147660565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1147660565
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2449385266
Short name T902
Test name
Test status
Simulation time 2134029165 ps
CPU time 2.4 seconds
Started Jul 01 10:33:30 AM PDT 24
Finished Jul 01 10:33:32 AM PDT 24
Peak memory 201828 kb
Host smart-31a3e1b9-ae58-448a-8c49-9d2258faebc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449385266 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2449385266
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.4065124081
Short name T860
Test name
Test status
Simulation time 2032030126 ps
CPU time 5.98 seconds
Started Jul 01 10:33:27 AM PDT 24
Finished Jul 01 10:33:33 AM PDT 24
Peak memory 201864 kb
Host smart-77fcbe85-f0a0-40e4-969f-95bc3eb0374c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065124081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.4065124081
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.846697845
Short name T842
Test name
Test status
Simulation time 2041767923 ps
CPU time 1.56 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 201532 kb
Host smart-528cfcce-3a90-4a39-9afe-2057e8d018f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846697845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.846697845
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3720774132
Short name T277
Test name
Test status
Simulation time 7840869816 ps
CPU time 3.63 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 202208 kb
Host smart-23495b8e-cd47-4ca2-8e00-45a4a42a4873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720774132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.3720774132
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3994494636
Short name T896
Test name
Test status
Simulation time 2220171728 ps
CPU time 2.07 seconds
Started Jul 01 10:33:21 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 202052 kb
Host smart-03577dca-4eab-49d9-aa75-b1acf6ceb617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994494636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.3994494636
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.706783823
Short name T272
Test name
Test status
Simulation time 22336134869 ps
CPU time 26.79 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 202168 kb
Host smart-6c685557-85ea-418d-b9de-3dc277205620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706783823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_tl_intg_err.706783823
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4010381236
Short name T803
Test name
Test status
Simulation time 2134180049 ps
CPU time 6.25 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:27 AM PDT 24
Peak memory 201968 kb
Host smart-35164624-812e-4c5c-8ef8-b27f8a0fbbd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010381236 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4010381236
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.635923961
Short name T327
Test name
Test status
Simulation time 2035369718 ps
CPU time 5.9 seconds
Started Jul 01 10:33:15 AM PDT 24
Finished Jul 01 10:33:23 AM PDT 24
Peak memory 201844 kb
Host smart-2bd7bb53-b038-4742-b5fd-c47d78d917ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635923961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw
.635923961
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2767670764
Short name T865
Test name
Test status
Simulation time 2077574244 ps
CPU time 1.07 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 201752 kb
Host smart-fa9a9063-864a-4402-8daa-49c89280e044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767670764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.2767670764
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.300237451
Short name T21
Test name
Test status
Simulation time 7120571141 ps
CPU time 17.78 seconds
Started Jul 01 10:33:28 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 202124 kb
Host smart-372db226-1cdd-4cb9-8699-b07fa7787a98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300237451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_same_csr_outstanding.300237451
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3148790313
Short name T914
Test name
Test status
Simulation time 2229252002 ps
CPU time 4.86 seconds
Started Jul 01 10:33:13 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 202056 kb
Host smart-22fa0a37-57a2-48be-9d81-9451b5844830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148790313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.3148790313
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3563184663
Short name T873
Test name
Test status
Simulation time 22180894657 ps
CPU time 56.18 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:34:17 AM PDT 24
Peak memory 202088 kb
Host smart-52e2b282-039a-4f3f-ac53-a42a924a1b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563184663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3563184663
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4249944850
Short name T836
Test name
Test status
Simulation time 2074623402 ps
CPU time 5.9 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:31 AM PDT 24
Peak memory 201828 kb
Host smart-3758e57b-a029-4e3e-9b23-ca8b1de55d62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249944850 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4249944850
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3710043385
Short name T322
Test name
Test status
Simulation time 2048542972 ps
CPU time 6.09 seconds
Started Jul 01 10:33:23 AM PDT 24
Finished Jul 01 10:33:30 AM PDT 24
Peak memory 201860 kb
Host smart-c57e8296-7553-4916-9965-7b8cffff5902
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710043385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.3710043385
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1567288810
Short name T840
Test name
Test status
Simulation time 2012765093 ps
CPU time 5.69 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:21 AM PDT 24
Peak memory 201532 kb
Host smart-e3904864-0297-48cc-ad27-973f90e9c0a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567288810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.1567288810
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3643806611
Short name T823
Test name
Test status
Simulation time 4814533297 ps
CPU time 6.45 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:33:24 AM PDT 24
Peak memory 202092 kb
Host smart-4876ae04-a68e-427f-89e7-941e97599971
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643806611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.3643806611
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1768133542
Short name T288
Test name
Test status
Simulation time 2217503337 ps
CPU time 2.69 seconds
Started Jul 01 10:33:24 AM PDT 24
Finished Jul 01 10:33:28 AM PDT 24
Peak memory 202100 kb
Host smart-0d30e9bb-4591-4569-82e2-b66e6f84a086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768133542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1768133542
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2248175474
Short name T805
Test name
Test status
Simulation time 2351590500 ps
CPU time 1.87 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 202148 kb
Host smart-33e00fce-dffc-4418-a9f1-76183aa8feb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248175474 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2248175474
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1911973650
Short name T883
Test name
Test status
Simulation time 2064233347 ps
CPU time 5.84 seconds
Started Jul 01 10:33:18 AM PDT 24
Finished Jul 01 10:33:25 AM PDT 24
Peak memory 201828 kb
Host smart-915fadcd-f806-44b5-a2d8-ee1db091b3b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911973650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.1911973650
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.506668089
Short name T827
Test name
Test status
Simulation time 2057636656 ps
CPU time 1.45 seconds
Started Jul 01 10:33:17 AM PDT 24
Finished Jul 01 10:33:19 AM PDT 24
Peak memory 201696 kb
Host smart-13a9f126-b02f-4d20-bd2b-d136be8f8d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506668089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test
.506668089
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1827849718
Short name T330
Test name
Test status
Simulation time 4650227080 ps
CPU time 6.2 seconds
Started Jul 01 10:33:14 AM PDT 24
Finished Jul 01 10:33:22 AM PDT 24
Peak memory 202084 kb
Host smart-5fc44243-e1f8-4705-9d8d-29860401befc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827849718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.1827849718
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.144754616
Short name T278
Test name
Test status
Simulation time 2133800191 ps
CPU time 3.27 seconds
Started Jul 01 10:33:22 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 202008 kb
Host smart-ff2b5a9e-e3b0-4f97-8ee5-373fa388287d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144754616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors
.144754616
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1083501728
Short name T286
Test name
Test status
Simulation time 22271966596 ps
CPU time 40.18 seconds
Started Jul 01 10:33:20 AM PDT 24
Finished Jul 01 10:34:02 AM PDT 24
Peak memory 202220 kb
Host smart-18d6aba3-3ff2-4e04-bea0-1ceb1fb24b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083501728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1083501728
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.81651646
Short name T888
Test name
Test status
Simulation time 2121866133 ps
CPU time 5.99 seconds
Started Jul 01 10:33:49 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 202080 kb
Host smart-0a6e1d4c-81cd-4150-9468-9ee55f029a44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81651646 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.81651646
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.975287181
Short name T893
Test name
Test status
Simulation time 2038001169 ps
CPU time 5.43 seconds
Started Jul 01 10:33:29 AM PDT 24
Finished Jul 01 10:33:35 AM PDT 24
Peak memory 201756 kb
Host smart-74f44a76-5d0c-4e2b-90e4-db0f87fda7d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975287181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw
.975287181
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.139493531
Short name T906
Test name
Test status
Simulation time 2022566528 ps
CPU time 3.19 seconds
Started Jul 01 10:33:22 AM PDT 24
Finished Jul 01 10:33:26 AM PDT 24
Peak memory 201752 kb
Host smart-77dc69ef-6b84-4f1f-993a-13aa401943d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139493531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test
.139493531
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3771287303
Short name T878
Test name
Test status
Simulation time 4987826429 ps
CPU time 11.91 seconds
Started Jul 01 10:33:19 AM PDT 24
Finished Jul 01 10:33:33 AM PDT 24
Peak memory 202164 kb
Host smart-5e2a4c78-e71f-4e53-8abe-57843bfa894b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771287303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.3771287303
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2999862949
Short name T279
Test name
Test status
Simulation time 2079413314 ps
CPU time 2.4 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:33:20 AM PDT 24
Peak memory 201996 kb
Host smart-78069da9-f1fa-4c90-8693-0e4d4475440d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999862949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.2999862949
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2668886164
Short name T291
Test name
Test status
Simulation time 42393900407 ps
CPU time 54.44 seconds
Started Jul 01 10:33:16 AM PDT 24
Finished Jul 01 10:34:12 AM PDT 24
Peak memory 202112 kb
Host smart-c0f98633-5f62-4578-9cc4-42d7218967ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668886164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2668886164
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.1360335366
Short name T510
Test name
Test status
Simulation time 2014719923 ps
CPU time 5.33 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:45 AM PDT 24
Peak memory 201480 kb
Host smart-8fe3129b-8f35-4cae-aee2-138655ed1cc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360335366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.1360335366
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.288153504
Short name T45
Test name
Test status
Simulation time 3215605500 ps
CPU time 7.97 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 201584 kb
Host smart-87e7656c-726f-4c68-be81-5eda4d99e937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288153504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.288153504
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.1904331269
Short name T372
Test name
Test status
Simulation time 110116059234 ps
CPU time 26.7 seconds
Started Jul 01 10:47:52 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201724 kb
Host smart-66f5619a-e841-480c-a4f5-7ee2fc298897
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904331269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.1904331269
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2946565475
Short name T90
Test name
Test status
Simulation time 2427317037 ps
CPU time 2.24 seconds
Started Jul 01 10:47:42 AM PDT 24
Finished Jul 01 10:47:45 AM PDT 24
Peak memory 201520 kb
Host smart-f0052743-ca4a-4b34-824e-b83fdde0a017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946565475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2946565475
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1637115901
Short name T723
Test name
Test status
Simulation time 2365547941 ps
CPU time 2.15 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:10 AM PDT 24
Peak memory 201500 kb
Host smart-03c18498-33fd-491e-a9f2-cfc20ba442fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637115901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1637115901
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.280413725
Short name T778
Test name
Test status
Simulation time 114874332831 ps
CPU time 278.2 seconds
Started Jul 01 10:47:43 AM PDT 24
Finished Jul 01 10:52:21 AM PDT 24
Peak memory 201872 kb
Host smart-cc20631b-4674-4729-a3d1-4479e52a5cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280413725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wit
h_pre_cond.280413725
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.3261159939
Short name T737
Test name
Test status
Simulation time 3302664577 ps
CPU time 2.85 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:47:58 AM PDT 24
Peak memory 201484 kb
Host smart-2dcc355d-3d64-4460-9da2-b5c8bdfe3407
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261159939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.3261159939
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1648556265
Short name T500
Test name
Test status
Simulation time 317483123536 ps
CPU time 276.31 seconds
Started Jul 01 10:47:50 AM PDT 24
Finished Jul 01 10:52:26 AM PDT 24
Peak memory 201592 kb
Host smart-1d1a13c3-ba0d-4cbd-8993-014de6886339
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648556265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.1648556265
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3878548339
Short name T513
Test name
Test status
Simulation time 2617814347 ps
CPU time 5.06 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:44 AM PDT 24
Peak memory 201528 kb
Host smart-f3419c1c-f118-4dce-ac0a-496288e9ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878548339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3878548339
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.910346955
Short name T609
Test name
Test status
Simulation time 2468308898 ps
CPU time 8.2 seconds
Started Jul 01 10:47:35 AM PDT 24
Finished Jul 01 10:47:44 AM PDT 24
Peak memory 201460 kb
Host smart-0c0bd657-6aa5-4b24-9a34-92fb0ee9bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910346955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.910346955
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.2817488160
Short name T575
Test name
Test status
Simulation time 2026536512 ps
CPU time 2.97 seconds
Started Jul 01 10:47:47 AM PDT 24
Finished Jul 01 10:47:51 AM PDT 24
Peak memory 201468 kb
Host smart-b0cb57c3-6a53-4f4c-86c6-8e69666949bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817488160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.2817488160
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.415232395
Short name T425
Test name
Test status
Simulation time 2512550284 ps
CPU time 7.27 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:10 AM PDT 24
Peak memory 201428 kb
Host smart-f59b89b8-1ca7-48f1-887c-4ef81b14cf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415232395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.415232395
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2902892747
Short name T715
Test name
Test status
Simulation time 2111323754 ps
CPU time 6.3 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:48:00 AM PDT 24
Peak memory 201400 kb
Host smart-362dcb7d-1e08-479e-a818-489311c41db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902892747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2902892747
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.1169542745
Short name T674
Test name
Test status
Simulation time 15084567139 ps
CPU time 19.04 seconds
Started Jul 01 10:47:42 AM PDT 24
Finished Jul 01 10:48:01 AM PDT 24
Peak memory 201648 kb
Host smart-e3c39e7a-4703-484a-951c-a2a16bc980f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169542745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.1169542745
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3095066085
Short name T302
Test name
Test status
Simulation time 563009144612 ps
CPU time 248.79 seconds
Started Jul 01 10:48:08 AM PDT 24
Finished Jul 01 10:52:17 AM PDT 24
Peak memory 210332 kb
Host smart-6b1bc95a-c37e-4f2e-91f4-e1f608e51e85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095066085 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.3095066085
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3216259804
Short name T135
Test name
Test status
Simulation time 2663874170 ps
CPU time 1.77 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201384 kb
Host smart-2d4d4a9f-8812-45ee-96a7-cc7c6d1b71e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216259804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.3216259804
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.1789910660
Short name T395
Test name
Test status
Simulation time 2012604166 ps
CPU time 5.28 seconds
Started Jul 01 10:47:47 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 201452 kb
Host smart-5003aa3f-dfd8-4b6d-8521-00c6da2ad99c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789910660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.1789910660
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1918348705
Short name T752
Test name
Test status
Simulation time 3423028837 ps
CPU time 2.18 seconds
Started Jul 01 10:47:55 AM PDT 24
Finished Jul 01 10:47:58 AM PDT 24
Peak memory 201492 kb
Host smart-bb68c135-f1f2-497c-853b-1b00dd30101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918348705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1918348705
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3178158440
Short name T369
Test name
Test status
Simulation time 66564256184 ps
CPU time 81.56 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:49:28 AM PDT 24
Peak memory 201816 kb
Host smart-9ce207fe-314b-4dd1-aea6-b86d0faaf735
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178158440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.3178158440
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3306160205
Short name T481
Test name
Test status
Simulation time 2213192648 ps
CPU time 5.83 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:07 AM PDT 24
Peak memory 201348 kb
Host smart-49a97436-eec7-4d5a-90a8-fabac7aaa150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306160205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.3306160205
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4093922480
Short name T521
Test name
Test status
Simulation time 2518007242 ps
CPU time 7.1 seconds
Started Jul 01 10:47:45 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 201468 kb
Host smart-d376da6b-7b9a-4c5d-b135-1f1f8c32c01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093922480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.4093922480
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3868698986
Short name T790
Test name
Test status
Simulation time 38316395757 ps
CPU time 28.69 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:48:35 AM PDT 24
Peak memory 201844 kb
Host smart-5de47d39-608c-4158-a606-0f27fb06e855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868698986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.3868698986
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3104986778
Short name T771
Test name
Test status
Simulation time 5506513257 ps
CPU time 4.24 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:47:58 AM PDT 24
Peak memory 201504 kb
Host smart-3aa97d06-0ebe-4c6b-8f28-8f6265ac9198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104986778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3104986778
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.2241986064
Short name T34
Test name
Test status
Simulation time 2491928561 ps
CPU time 7.23 seconds
Started Jul 01 10:47:43 AM PDT 24
Finished Jul 01 10:47:51 AM PDT 24
Peak memory 201396 kb
Host smart-89e42ac5-dcdb-4dff-a723-7d868ef396a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241986064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.2241986064
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1822286638
Short name T242
Test name
Test status
Simulation time 2635986317 ps
CPU time 2.11 seconds
Started Jul 01 10:47:40 AM PDT 24
Finished Jul 01 10:47:43 AM PDT 24
Peak memory 201508 kb
Host smart-65188548-803f-40fc-ac65-d0aeb6fc59a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822286638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.1822286638
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2543981903
Short name T116
Test name
Test status
Simulation time 2486034442 ps
CPU time 4.01 seconds
Started Jul 01 10:47:33 AM PDT 24
Finished Jul 01 10:47:39 AM PDT 24
Peak memory 201500 kb
Host smart-f33b3935-8b68-4b28-be2a-68ab81c1a818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543981903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2543981903
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3638162583
Short name T49
Test name
Test status
Simulation time 2151844662 ps
CPU time 6.31 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 201432 kb
Host smart-de458290-170b-49c9-92ce-2a2ebd70c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638162583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.3638162583
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.26249782
Short name T433
Test name
Test status
Simulation time 2511832520 ps
CPU time 7.43 seconds
Started Jul 01 10:47:51 AM PDT 24
Finished Jul 01 10:47:59 AM PDT 24
Peak memory 201496 kb
Host smart-af12d7f4-ae51-488b-9f9b-c5ada858f427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26249782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.26249782
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.4197607603
Short name T295
Test name
Test status
Simulation time 42010434367 ps
CPU time 112.3 seconds
Started Jul 01 10:48:08 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 221084 kb
Host smart-d385c208-5556-4974-ba27-703aa8da48d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197607603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.4197607603
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.3402160501
Short name T471
Test name
Test status
Simulation time 2115353433 ps
CPU time 6.13 seconds
Started Jul 01 10:47:28 AM PDT 24
Finished Jul 01 10:47:37 AM PDT 24
Peak memory 201396 kb
Host smart-db44fa75-f2ef-4a91-830d-a1a27d840967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402160501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.3402160501
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1604756903
Short name T645
Test name
Test status
Simulation time 286852875086 ps
CPU time 673.92 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:59:17 AM PDT 24
Peak memory 201612 kb
Host smart-2f335a0e-83e5-4edc-8e6d-6ca124ae2c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604756903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1604756903
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.975545343
Short name T88
Test name
Test status
Simulation time 28374357972 ps
CPU time 19.2 seconds
Started Jul 01 10:47:44 AM PDT 24
Finished Jul 01 10:48:03 AM PDT 24
Peak memory 217720 kb
Host smart-16010f41-dfa0-43fc-a034-4c8735d675e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975545343 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.975545343
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3689637682
Short name T555
Test name
Test status
Simulation time 5967542927 ps
CPU time 7.08 seconds
Started Jul 01 10:47:47 AM PDT 24
Finished Jul 01 10:47:55 AM PDT 24
Peak memory 201512 kb
Host smart-44c54e9e-c9fd-470c-9101-798b53a85230
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689637682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.3689637682
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.859728790
Short name T678
Test name
Test status
Simulation time 2009656655 ps
CPU time 5.98 seconds
Started Jul 01 10:48:04 AM PDT 24
Finished Jul 01 10:48:11 AM PDT 24
Peak memory 201468 kb
Host smart-6a2056f9-fc47-4f24-8e16-8931aa446607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859728790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_tes
t.859728790
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2829370816
Short name T393
Test name
Test status
Simulation time 3632223895 ps
CPU time 4.79 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 201584 kb
Host smart-6da8bf55-5f8f-4206-993f-0ee1386434e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829370816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2
829370816
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.1533824853
Short name T374
Test name
Test status
Simulation time 69652580506 ps
CPU time 169.63 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:50:47 AM PDT 24
Peak memory 201672 kb
Host smart-c62ed4ca-22e6-4d3e-a303-4261d2912879
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533824853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.1533824853
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3062696785
Short name T223
Test name
Test status
Simulation time 4113473071 ps
CPU time 5.24 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 201552 kb
Host smart-834e7586-0b5f-485e-b3ea-8ee665136912
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062696785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.3062696785
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.2904373353
Short name T195
Test name
Test status
Simulation time 1108438460286 ps
CPU time 1402.88 seconds
Started Jul 01 10:48:12 AM PDT 24
Finished Jul 01 11:11:36 AM PDT 24
Peak memory 201544 kb
Host smart-1e56df29-a0d3-477d-ad7e-2c5c14b19c20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904373353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.2904373353
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.438952671
Short name T535
Test name
Test status
Simulation time 2621651604 ps
CPU time 2.64 seconds
Started Jul 01 10:47:55 AM PDT 24
Finished Jul 01 10:47:59 AM PDT 24
Peak memory 201492 kb
Host smart-1a4219b1-390d-49f5-a2cb-a3e47781bc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438952671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.438952671
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1555018231
Short name T309
Test name
Test status
Simulation time 2488571041 ps
CPU time 2.49 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201472 kb
Host smart-83a54980-91d6-42ab-b185-8f4591e027a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555018231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1555018231
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.504586971
Short name T758
Test name
Test status
Simulation time 2207399332 ps
CPU time 1.91 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 201472 kb
Host smart-820055cb-9432-459b-bcb5-6455c0314ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504586971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.504586971
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.482248292
Short name T228
Test name
Test status
Simulation time 2597254729 ps
CPU time 1.28 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:47:56 AM PDT 24
Peak memory 201524 kb
Host smart-9d894009-1bd0-4634-b8ce-3eb120db63e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482248292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.482248292
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.894368705
Short name T667
Test name
Test status
Simulation time 2128612103 ps
CPU time 2.04 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201404 kb
Host smart-c174ad6e-7f0d-4981-b115-e7a4de489b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894368705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.894368705
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.4004150589
Short name T376
Test name
Test status
Simulation time 110491149157 ps
CPU time 173.28 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:51:11 AM PDT 24
Peak memory 201780 kb
Host smart-870c5f3e-b150-4165-a1c4-e1f9206fa635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004150589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.4004150589
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1917636987
Short name T753
Test name
Test status
Simulation time 5099473303 ps
CPU time 3.86 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201552 kb
Host smart-72e6dc68-b52d-4fe5-b62e-90a6e9a4a3d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917636987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.1917636987
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1378336435
Short name T591
Test name
Test status
Simulation time 2033097849 ps
CPU time 1.98 seconds
Started Jul 01 10:47:59 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 201456 kb
Host smart-e1eca075-1cd4-462d-bb5d-7af38e958fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378336435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1378336435
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.366464828
Short name T776
Test name
Test status
Simulation time 4046189870 ps
CPU time 11.79 seconds
Started Jul 01 10:48:04 AM PDT 24
Finished Jul 01 10:48:17 AM PDT 24
Peak memory 201552 kb
Host smart-149dbf45-9c99-4bc8-bf75-32a43f81e74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366464828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.366464828
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1470514732
Short name T264
Test name
Test status
Simulation time 102699725095 ps
CPU time 60.79 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 201672 kb
Host smart-8e83aec0-f928-4deb-a663-62c428d6c314
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470514732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.1470514732
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2139774036
Short name T96
Test name
Test status
Simulation time 27336580329 ps
CPU time 33.73 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:58 AM PDT 24
Peak memory 202040 kb
Host smart-08d529cd-7c77-4d3b-8d9c-60c601c7631e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139774036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.2139774036
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1682915084
Short name T167
Test name
Test status
Simulation time 3051136372 ps
CPU time 4.28 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201360 kb
Host smart-e9e26480-1b9b-46bb-8d6d-25bd0a8be4cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682915084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.1682915084
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1686102774
Short name T577
Test name
Test status
Simulation time 2613195244 ps
CPU time 7.68 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:48:07 AM PDT 24
Peak memory 201480 kb
Host smart-83b49db8-a0f6-4a4e-aff9-76b995908a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686102774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1686102774
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1895562035
Short name T26
Test name
Test status
Simulation time 2465886519 ps
CPU time 5.13 seconds
Started Jul 01 10:48:19 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201436 kb
Host smart-d1fa24bc-ae10-4011-b587-e63812dd17b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895562035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1895562035
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1323899127
Short name T571
Test name
Test status
Simulation time 2107489365 ps
CPU time 5.81 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201448 kb
Host smart-8180eeb0-afef-4ce2-8a2c-a00629bf66be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323899127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1323899127
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4018858770
Short name T748
Test name
Test status
Simulation time 2517299378 ps
CPU time 4.08 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 201520 kb
Host smart-0e3269de-0670-470d-acf1-8f8704579792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018858770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.4018858770
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.1353617430
Short name T769
Test name
Test status
Simulation time 2120383757 ps
CPU time 3.31 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:26 AM PDT 24
Peak memory 201356 kb
Host smart-baec27a2-b8f3-4373-b171-6b6047ce41b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353617430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.1353617430
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.1450902415
Short name T583
Test name
Test status
Simulation time 556545495956 ps
CPU time 18.31 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:33 AM PDT 24
Peak memory 201464 kb
Host smart-a89dce59-4acb-4808-b903-c4ea79da5f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450902415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.1450902415
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.778915536
Short name T138
Test name
Test status
Simulation time 48022533114 ps
CPU time 105.32 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:50:04 AM PDT 24
Peak memory 210140 kb
Host smart-9b2a68e5-c83d-4600-bffe-71ba963ace98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778915536 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.778915536
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.33392052
Short name T648
Test name
Test status
Simulation time 587237408586 ps
CPU time 33.66 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:36 AM PDT 24
Peak memory 201520 kb
Host smart-c3effd87-2e43-41b7-b8e9-f36103a456c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33392052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_ultra_low_pwr.33392052
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.613441196
Short name T416
Test name
Test status
Simulation time 3337174534 ps
CPU time 4.73 seconds
Started Jul 01 10:48:08 AM PDT 24
Finished Jul 01 10:48:14 AM PDT 24
Peak memory 201520 kb
Host smart-b4a375de-01eb-4c3e-b12e-a2a48de6b0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613441196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.613441196
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.3854917234
Short name T560
Test name
Test status
Simulation time 96370094876 ps
CPU time 261.54 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:52:47 AM PDT 24
Peak memory 201748 kb
Host smart-f9eaa5e8-8104-4dc0-a0d6-badff59f91b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854917234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.3854917234
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2428595612
Short name T662
Test name
Test status
Simulation time 23841304310 ps
CPU time 27.16 seconds
Started Jul 01 10:48:04 AM PDT 24
Finished Jul 01 10:48:32 AM PDT 24
Peak memory 201816 kb
Host smart-b26d1c62-3ac2-4f40-b5d4-d5b75ac30e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428595612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.2428595612
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3149527449
Short name T599
Test name
Test status
Simulation time 4925261303 ps
CPU time 3.53 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:03 AM PDT 24
Peak memory 201500 kb
Host smart-78280ffb-28af-4f20-b14d-f77a330df4a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149527449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.3149527449
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2560847434
Short name T740
Test name
Test status
Simulation time 2614727634 ps
CPU time 3.94 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:05 AM PDT 24
Peak memory 201488 kb
Host smart-96459754-11a3-40dd-a3cf-72f0dc5479e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560847434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.2560847434
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2480471949
Short name T469
Test name
Test status
Simulation time 2491504419 ps
CPU time 2.15 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 201388 kb
Host smart-57430c35-881d-4bc3-9fca-483c1529b773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480471949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2480471949
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.68780972
Short name T202
Test name
Test status
Simulation time 2073659614 ps
CPU time 1.87 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:24 AM PDT 24
Peak memory 201448 kb
Host smart-df326128-246e-4fd8-836f-9ca272e81f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68780972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.68780972
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3773161879
Short name T671
Test name
Test status
Simulation time 2522592788 ps
CPU time 2.43 seconds
Started Jul 01 10:48:03 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 201484 kb
Host smart-66a6fe56-09f5-4031-b1fa-a5524ef5db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773161879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3773161879
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.3996184200
Short name T508
Test name
Test status
Simulation time 2109997577 ps
CPU time 6.04 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201348 kb
Host smart-22dc661c-fee2-4f68-8b5e-df4a4cdb5b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996184200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.3996184200
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.2756197950
Short name T408
Test name
Test status
Simulation time 11816623972 ps
CPU time 31.16 seconds
Started Jul 01 10:48:11 AM PDT 24
Finished Jul 01 10:48:43 AM PDT 24
Peak memory 201820 kb
Host smart-a636095b-6a47-49da-9a0b-f5a0f9d96d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756197950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.2756197950
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2687116086
Short name T212
Test name
Test status
Simulation time 17763307311 ps
CPU time 47.19 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 210132 kb
Host smart-237ebf8b-a258-4374-8868-e24884f00ccf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687116086 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.2687116086
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1547785332
Short name T89
Test name
Test status
Simulation time 4293913863 ps
CPU time 6.28 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 201400 kb
Host smart-9cd532a9-4267-42bb-bdc4-4d900aa757f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547785332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.1547785332
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.3220684692
Short name T219
Test name
Test status
Simulation time 2025567453 ps
CPU time 2.08 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:17 AM PDT 24
Peak memory 201500 kb
Host smart-4f85d353-4fcb-48c0-a809-ad86525f5e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220684692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.3220684692
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1713948844
Short name T338
Test name
Test status
Simulation time 188300905391 ps
CPU time 461.09 seconds
Started Jul 01 10:48:57 AM PDT 24
Finished Jul 01 10:56:38 AM PDT 24
Peak memory 201824 kb
Host smart-2d2b9222-53bd-4a8c-b15c-33cb5a906510
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713948844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1713948844
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2679980773
Short name T355
Test name
Test status
Simulation time 148025764326 ps
CPU time 43.04 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:49:05 AM PDT 24
Peak memory 201872 kb
Host smart-6982e78b-baf4-4089-9480-e62d45d53cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679980773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.2679980773
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1450246298
Short name T642
Test name
Test status
Simulation time 3263445644 ps
CPU time 4.74 seconds
Started Jul 01 10:48:08 AM PDT 24
Finished Jul 01 10:48:13 AM PDT 24
Peak memory 201476 kb
Host smart-8dfd57f9-ce43-4a8f-9469-29db91412e12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450246298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1450246298
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1544210739
Short name T708
Test name
Test status
Simulation time 4072065788 ps
CPU time 11.29 seconds
Started Jul 01 10:48:08 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201488 kb
Host smart-f42601ba-3942-4d72-bdcf-41d1d34491d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544210739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.1544210739
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1163956718
Short name T189
Test name
Test status
Simulation time 2617376094 ps
CPU time 4.12 seconds
Started Jul 01 10:47:59 AM PDT 24
Finished Jul 01 10:48:05 AM PDT 24
Peak memory 201460 kb
Host smart-2806b86a-2c3f-4836-b96e-2007e4bf7fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163956718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1163956718
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.186515213
Short name T432
Test name
Test status
Simulation time 2475396587 ps
CPU time 2.06 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201520 kb
Host smart-697ac4b1-8884-457f-a5b4-0b6efb73c4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186515213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.186515213
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.862163499
Short name T520
Test name
Test status
Simulation time 2243423379 ps
CPU time 3.4 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 201712 kb
Host smart-4e2dfaeb-b876-4142-be8f-cb42d3b2adac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862163499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.862163499
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.821380477
Short name T544
Test name
Test status
Simulation time 2511878268 ps
CPU time 6.92 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:48:24 AM PDT 24
Peak memory 201500 kb
Host smart-59032f80-4d7b-400f-9955-98477ee75d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821380477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.821380477
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.2819034472
Short name T580
Test name
Test status
Simulation time 2128896846 ps
CPU time 2.23 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:05 AM PDT 24
Peak memory 201420 kb
Host smart-400a4ace-0e96-4090-b010-61fce9548edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819034472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2819034472
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.2678974160
Short name T10
Test name
Test status
Simulation time 19176015103 ps
CPU time 5.23 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201700 kb
Host smart-0035a969-c296-4ea1-bc45-d404c18634da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678974160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.2678974160
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.728706109
Short name T258
Test name
Test status
Simulation time 88766629373 ps
CPU time 53.59 seconds
Started Jul 01 10:48:12 AM PDT 24
Finished Jul 01 10:49:06 AM PDT 24
Peak memory 201956 kb
Host smart-71736cb5-64c5-4ad3-a70b-3cb0b163cb88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728706109 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.728706109
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2781424056
Short name T783
Test name
Test status
Simulation time 4307572314 ps
CPU time 3.66 seconds
Started Jul 01 10:48:10 AM PDT 24
Finished Jul 01 10:48:14 AM PDT 24
Peak memory 201512 kb
Host smart-f93a31ed-6164-4652-8b57-5b1853f801a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781424056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.2781424056
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.3376858020
Short name T764
Test name
Test status
Simulation time 2028565726 ps
CPU time 2.01 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201340 kb
Host smart-f5f5c1a3-40bc-4cb3-beb5-373ca5e0e225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376858020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.3376858020
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1245951733
Short name T756
Test name
Test status
Simulation time 3312543549 ps
CPU time 2.65 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:48:19 AM PDT 24
Peak memory 201544 kb
Host smart-3123adc8-706a-4ba0-8e5b-f4e6be41af42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245951733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
245951733
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1526649601
Short name T620
Test name
Test status
Simulation time 87687069521 ps
CPU time 113.89 seconds
Started Jul 01 10:48:24 AM PDT 24
Finished Jul 01 10:50:20 AM PDT 24
Peak memory 201648 kb
Host smart-0197d45f-f80f-4777-a4a4-fdc0779f3993
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526649601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1526649601
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.190333682
Short name T543
Test name
Test status
Simulation time 27846324620 ps
CPU time 20.4 seconds
Started Jul 01 10:48:04 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201852 kb
Host smart-0186e364-16c8-454c-b825-8b84841de613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190333682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_wi
th_pre_cond.190333682
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1912157656
Short name T204
Test name
Test status
Simulation time 4188296419 ps
CPU time 2.09 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:26 AM PDT 24
Peak memory 201424 kb
Host smart-28b7f7d0-f0bb-41fe-970b-17b1f757776d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912157656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.1912157656
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2868857340
Short name T173
Test name
Test status
Simulation time 4165546040 ps
CPU time 2.97 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:22 AM PDT 24
Peak memory 201472 kb
Host smart-1704b582-6641-4220-bca8-27d8245f0f4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868857340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2868857340
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3798421769
Short name T499
Test name
Test status
Simulation time 2612283759 ps
CPU time 7.19 seconds
Started Jul 01 10:48:11 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 201496 kb
Host smart-e2db58e9-e9fd-48c9-9769-69f1f2a27337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798421769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.3798421769
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1503740392
Short name T390
Test name
Test status
Simulation time 2482588799 ps
CPU time 2.27 seconds
Started Jul 01 10:48:28 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201524 kb
Host smart-55b2f68b-b742-433b-8bdd-5d7165882ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503740392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1503740392
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3786385917
Short name T632
Test name
Test status
Simulation time 2197516388 ps
CPU time 2.07 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:24 AM PDT 24
Peak memory 201452 kb
Host smart-14ed707d-968d-43eb-961d-685b7459e4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786385917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3786385917
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.3960295953
Short name T461
Test name
Test status
Simulation time 2512578703 ps
CPU time 6.69 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201512 kb
Host smart-470c3cdb-cb8c-4797-9060-11997260d201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960295953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.3960295953
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.1107278830
Short name T225
Test name
Test status
Simulation time 2128425957 ps
CPU time 1.95 seconds
Started Jul 01 10:48:12 AM PDT 24
Finished Jul 01 10:48:15 AM PDT 24
Peak memory 201500 kb
Host smart-a466ec4f-6f01-4cf0-a087-2b87da3a82b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107278830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.1107278830
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2828629722
Short name T423
Test name
Test status
Simulation time 7888472154 ps
CPU time 11.87 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:34 AM PDT 24
Peak memory 201452 kb
Host smart-99e1a109-84ea-4ef8-82ac-e65dd68794fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828629722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2828629722
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.354900201
Short name T154
Test name
Test status
Simulation time 41344789649 ps
CPU time 80.03 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:49:23 AM PDT 24
Peak memory 210208 kb
Host smart-712b66c6-3843-4753-ae4a-d295b6cdf813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354900201 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.354900201
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1724609582
Short name T133
Test name
Test status
Simulation time 12307520201 ps
CPU time 8.43 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201552 kb
Host smart-54ef91d2-da0f-4425-b465-3a9f80fa1a23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724609582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.1724609582
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.348952463
Short name T454
Test name
Test status
Simulation time 2011214780 ps
CPU time 5.88 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201460 kb
Host smart-d93d8a4b-ceb3-4cab-96b4-b14880c44914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348952463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.348952463
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1397048996
Short name T439
Test name
Test status
Simulation time 117485160144 ps
CPU time 77.65 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:49:41 AM PDT 24
Peak memory 201604 kb
Host smart-b4739516-bc55-42e4-8435-1fdb24a3272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397048996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.1
397048996
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2218827668
Short name T766
Test name
Test status
Simulation time 32968468965 ps
CPU time 21.95 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:47 AM PDT 24
Peak memory 201772 kb
Host smart-c9e12a8e-8ad2-4e31-b628-23f6dd0f8daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218827668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.2218827668
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2408290885
Short name T506
Test name
Test status
Simulation time 2462626269 ps
CPU time 6.94 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:48:24 AM PDT 24
Peak memory 201480 kb
Host smart-2bc2a166-fedf-4bff-b653-69e15a26013d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408290885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.2408290885
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3581542657
Short name T148
Test name
Test status
Simulation time 3910176889 ps
CPU time 10.22 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:48:26 AM PDT 24
Peak memory 201524 kb
Host smart-7452f3e5-968f-4bed-924e-868d60171d09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581542657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.3581542657
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3180634696
Short name T485
Test name
Test status
Simulation time 2629196408 ps
CPU time 2.41 seconds
Started Jul 01 10:48:10 AM PDT 24
Finished Jul 01 10:48:13 AM PDT 24
Peak memory 201476 kb
Host smart-ce73cece-d1aa-49e3-9fa8-d928733b3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180634696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.3180634696
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1166168048
Short name T483
Test name
Test status
Simulation time 2459271696 ps
CPU time 3.84 seconds
Started Jul 01 10:48:34 AM PDT 24
Finished Jul 01 10:48:38 AM PDT 24
Peak memory 201424 kb
Host smart-97595501-e40d-40ea-a81a-4cd92fc44790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166168048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1166168048
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1145587551
Short name T765
Test name
Test status
Simulation time 2150302289 ps
CPU time 1.77 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201516 kb
Host smart-ccaddc80-e448-4fcb-8aeb-fbcbaaa2946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145587551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1145587551
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.4264778314
Short name T268
Test name
Test status
Simulation time 2510156720 ps
CPU time 7.11 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:48:33 AM PDT 24
Peak memory 201500 kb
Host smart-be68075b-0bcb-4680-ba27-679344a42779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264778314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.4264778314
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3330822441
Short name T623
Test name
Test status
Simulation time 2110672420 ps
CPU time 6.08 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201436 kb
Host smart-335a2a34-1908-486e-a0fb-dd91c5c2dfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330822441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3330822441
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.1791933915
Short name T108
Test name
Test status
Simulation time 41511738297 ps
CPU time 28.59 seconds
Started Jul 01 10:48:11 AM PDT 24
Finished Jul 01 10:48:40 AM PDT 24
Peak memory 201804 kb
Host smart-9ad31a67-a9f9-4f85-b8f0-7da0252502ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791933915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.1791933915
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.607195132
Short name T313
Test name
Test status
Simulation time 139656707702 ps
CPU time 141.51 seconds
Started Jul 01 10:48:03 AM PDT 24
Finished Jul 01 10:50:26 AM PDT 24
Peak memory 218288 kb
Host smart-b8dbed78-c910-4acd-82be-11610998ca40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607195132 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.607195132
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3666699876
Short name T124
Test name
Test status
Simulation time 5613029130 ps
CPU time 6.72 seconds
Started Jul 01 10:48:19 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201472 kb
Host smart-e990de6c-a8dc-450a-ba36-af68a5ba5ba1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666699876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.3666699876
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.3267241945
Short name T795
Test name
Test status
Simulation time 2012163364 ps
CPU time 5.81 seconds
Started Jul 01 10:48:46 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201404 kb
Host smart-ff900557-05f9-4682-96cd-018c06f55b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267241945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.3267241945
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2399627155
Short name T246
Test name
Test status
Simulation time 32324526055 ps
CPU time 82.16 seconds
Started Jul 01 10:48:41 AM PDT 24
Finished Jul 01 10:50:04 AM PDT 24
Peak memory 201720 kb
Host smart-d47b67bd-a12b-4f83-8ffa-49b9e7307d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399627155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2399627155
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2134403910
Short name T388
Test name
Test status
Simulation time 2761944601 ps
CPU time 4.09 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:48:22 AM PDT 24
Peak memory 201484 kb
Host smart-0fc06a3d-d270-45fb-b5a4-fde7b1da12d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134403910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.2134403910
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.637269146
Short name T2
Test name
Test status
Simulation time 536896749639 ps
CPU time 1453.63 seconds
Started Jul 01 10:48:25 AM PDT 24
Finished Jul 01 11:12:44 AM PDT 24
Peak memory 201536 kb
Host smart-aea816c3-3538-431e-9f03-abefe5bebdaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637269146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctr
l_edge_detect.637269146
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.107722070
Short name T665
Test name
Test status
Simulation time 2610462423 ps
CPU time 7.42 seconds
Started Jul 01 10:48:10 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 201476 kb
Host smart-d2f523e3-a2ab-4a89-a4a8-0b61e67b5f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107722070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.107722070
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.999333314
Short name T400
Test name
Test status
Simulation time 2472906428 ps
CPU time 2.15 seconds
Started Jul 01 10:48:25 AM PDT 24
Finished Jul 01 10:48:29 AM PDT 24
Peak memory 201448 kb
Host smart-99b35398-a0d2-47e8-ae0a-fb8abf6cf04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999333314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.999333314
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.199248921
Short name T556
Test name
Test status
Simulation time 2083372792 ps
CPU time 1.83 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:16 AM PDT 24
Peak memory 201448 kb
Host smart-a1c5f32a-c55c-432f-a023-7d330409e702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199248921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.199248921
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.918119235
Short name T703
Test name
Test status
Simulation time 2512580156 ps
CPU time 7.14 seconds
Started Jul 01 10:48:12 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201496 kb
Host smart-5d559ab9-8d93-493c-9b31-4652995fabd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918119235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.918119235
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.3519418607
Short name T527
Test name
Test status
Simulation time 2130054275 ps
CPU time 1.91 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:09 AM PDT 24
Peak memory 201444 kb
Host smart-fa82354c-e65b-4bb4-9300-57476cad7d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519418607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.3519418607
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.4108897553
Short name T155
Test name
Test status
Simulation time 9944481715 ps
CPU time 4.95 seconds
Started Jul 01 10:48:08 AM PDT 24
Finished Jul 01 10:48:14 AM PDT 24
Peak memory 201348 kb
Host smart-32e8e88a-9da6-4a1c-8ec4-9bfe688c3f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108897553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.4108897553
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2340994171
Short name T622
Test name
Test status
Simulation time 8572852610 ps
CPU time 2.93 seconds
Started Jul 01 10:48:44 AM PDT 24
Finished Jul 01 10:48:47 AM PDT 24
Peak memory 201496 kb
Host smart-599367e8-a221-4519-b41a-64eb5c303daf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340994171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.2340994171
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.4270184930
Short name T452
Test name
Test status
Simulation time 2037696347 ps
CPU time 1.93 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:26 AM PDT 24
Peak memory 201500 kb
Host smart-d0397974-bb20-453d-9dca-6d1ac9416f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270184930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.4270184930
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1698860572
Short name T757
Test name
Test status
Simulation time 3352113723 ps
CPU time 7.09 seconds
Started Jul 01 10:48:13 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201476 kb
Host smart-cd4f1fdd-2cae-428b-bcb6-d9dcf9d3f764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698860572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
698860572
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.4290430204
Short name T595
Test name
Test status
Simulation time 123358166171 ps
CPU time 86.67 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:49:52 AM PDT 24
Peak memory 201736 kb
Host smart-111064c4-dea7-475e-a0e3-d207b186bf2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290430204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.4290430204
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3430250080
Short name T348
Test name
Test status
Simulation time 115221848401 ps
CPU time 156.66 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:50:54 AM PDT 24
Peak memory 201800 kb
Host smart-33580005-2552-43e6-9a2f-435837f38128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430250080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.3430250080
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3138890371
Short name T404
Test name
Test status
Simulation time 3366091200 ps
CPU time 9.86 seconds
Started Jul 01 10:48:25 AM PDT 24
Finished Jul 01 10:48:36 AM PDT 24
Peak memory 201484 kb
Host smart-84e5e2e3-abdd-48c5-b954-e2e71f8d73f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138890371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.3138890371
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.2199206662
Short name T180
Test name
Test status
Simulation time 3028865121 ps
CPU time 3.53 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201396 kb
Host smart-afd03c8b-ee7f-48a0-ad2b-b01d6f8b9f95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199206662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.2199206662
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2506964178
Short name T736
Test name
Test status
Simulation time 2611754487 ps
CPU time 7.4 seconds
Started Jul 01 10:48:09 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 201564 kb
Host smart-ba5e59fe-48e4-477c-839f-fe294863474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506964178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.2506964178
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3743386962
Short name T449
Test name
Test status
Simulation time 2466151199 ps
CPU time 2.32 seconds
Started Jul 01 10:48:13 AM PDT 24
Finished Jul 01 10:48:17 AM PDT 24
Peak memory 201504 kb
Host smart-74e93aef-7ba2-4315-99fd-f5bbf1c71ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743386962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3743386962
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2778780709
Short name T572
Test name
Test status
Simulation time 2244196036 ps
CPU time 6.7 seconds
Started Jul 01 10:48:19 AM PDT 24
Finished Jul 01 10:48:26 AM PDT 24
Peak memory 201532 kb
Host smart-8c50e572-a631-4e68-917b-0404e87b14fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778780709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.2778780709
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1631108978
Short name T299
Test name
Test status
Simulation time 2533929102 ps
CPU time 2.23 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 201356 kb
Host smart-b1694d81-3935-43cb-ab6d-2a5eb3d838f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631108978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.1631108978
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.2279535070
Short name T523
Test name
Test status
Simulation time 2111116601 ps
CPU time 5.78 seconds
Started Jul 01 10:48:08 AM PDT 24
Finished Jul 01 10:48:14 AM PDT 24
Peak memory 201440 kb
Host smart-0e002e1f-6868-4051-9cdc-39f865fee50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279535070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.2279535070
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2647645088
Short name T701
Test name
Test status
Simulation time 524557001675 ps
CPU time 140.06 seconds
Started Jul 01 10:48:41 AM PDT 24
Finished Jul 01 10:51:01 AM PDT 24
Peak memory 210016 kb
Host smart-19587ab9-3ad9-4733-b8be-134f0a268cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647645088 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.2647645088
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3699690437
Short name T787
Test name
Test status
Simulation time 7601585867 ps
CPU time 2.58 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 201552 kb
Host smart-8de4dc97-28b5-438d-9409-d9986cf0303c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699690437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.3699690437
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.2036464170
Short name T52
Test name
Test status
Simulation time 2008644152 ps
CPU time 5.55 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:48:23 AM PDT 24
Peak memory 201464 kb
Host smart-a4a62e93-3bb5-42ce-aaeb-44a55dc2c97e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036464170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.2036464170
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1338412866
Short name T119
Test name
Test status
Simulation time 483751389039 ps
CPU time 1203.82 seconds
Started Jul 01 10:48:10 AM PDT 24
Finished Jul 01 11:08:15 AM PDT 24
Peak memory 201652 kb
Host smart-d589a0ef-adc7-41ef-8f03-98f8be2dc230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338412866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
338412866
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3609102988
Short name T74
Test name
Test status
Simulation time 113004795003 ps
CPU time 23.18 seconds
Started Jul 01 10:48:25 AM PDT 24
Finished Jul 01 10:48:50 AM PDT 24
Peak memory 201768 kb
Host smart-c977b84a-2f71-4859-86b1-aa76e2b0b778
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609102988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3609102988
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.810485846
Short name T773
Test name
Test status
Simulation time 96890231213 ps
CPU time 62.35 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201744 kb
Host smart-0f29c2da-5da7-4eb7-8801-44d54f46202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810485846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.810485846
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1262041758
Short name T582
Test name
Test status
Simulation time 4171225023 ps
CPU time 11.51 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:34 AM PDT 24
Peak memory 201396 kb
Host smart-5dcfaee3-0ab0-47ed-b444-e0f643d81034
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262041758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.1262041758
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.1255860768
Short name T208
Test name
Test status
Simulation time 3343097804 ps
CPU time 4.15 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201480 kb
Host smart-7771c0eb-673d-4206-bca0-5ecf07eb79d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255860768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.1255860768
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.635985856
Short name T549
Test name
Test status
Simulation time 2661242290 ps
CPU time 1.64 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201528 kb
Host smart-88b44011-dda1-42d3-80f5-7647a6b5e7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635985856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.635985856
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3253504339
Short name T64
Test name
Test status
Simulation time 2470476404 ps
CPU time 3.86 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201420 kb
Host smart-492a192d-acbb-44ae-942e-038ee2679f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253504339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3253504339
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2145725150
Short name T655
Test name
Test status
Simulation time 2181066217 ps
CPU time 6.29 seconds
Started Jul 01 10:48:29 AM PDT 24
Finished Jul 01 10:48:36 AM PDT 24
Peak memory 201520 kb
Host smart-2bc48346-80cf-4e5b-bb7f-91139d7ad553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145725150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.2145725150
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3265300363
Short name T385
Test name
Test status
Simulation time 2515031253 ps
CPU time 7.62 seconds
Started Jul 01 10:48:30 AM PDT 24
Finished Jul 01 10:48:38 AM PDT 24
Peak memory 201504 kb
Host smart-acc65827-22fb-4440-ada0-b2ad21b7b5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265300363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3265300363
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.2412219455
Short name T643
Test name
Test status
Simulation time 2127965152 ps
CPU time 1.86 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201444 kb
Host smart-a98b4040-42be-414d-a85a-20fba99be688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412219455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2412219455
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.3704303870
Short name T679
Test name
Test status
Simulation time 8918090992 ps
CPU time 22.09 seconds
Started Jul 01 10:48:28 AM PDT 24
Finished Jul 01 10:48:51 AM PDT 24
Peak memory 201444 kb
Host smart-8f35e364-2812-4ee0-9403-2dcebe0f9987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704303870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.3704303870
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.4158710301
Short name T87
Test name
Test status
Simulation time 607874196765 ps
CPU time 183.79 seconds
Started Jul 01 10:48:13 AM PDT 24
Finished Jul 01 10:51:17 AM PDT 24
Peak memory 210204 kb
Host smart-9417a6bd-18f7-44a4-bf31-3d3d2e7eb070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158710301 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.4158710301
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.347806872
Short name T749
Test name
Test status
Simulation time 2074514121 ps
CPU time 1.15 seconds
Started Jul 01 10:48:25 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201356 kb
Host smart-a965de20-213e-45b4-8d4d-6a31f7be42fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347806872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_tes
t.347806872
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1455213733
Short name T704
Test name
Test status
Simulation time 3497779974 ps
CPU time 2.95 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201536 kb
Host smart-b7756cc7-4349-4eed-bb2d-0e324be4cdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455213733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
455213733
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3705158138
Short name T336
Test name
Test status
Simulation time 116923731513 ps
CPU time 319.27 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:53:42 AM PDT 24
Peak memory 201828 kb
Host smart-0b88649b-8356-40d7-9c94-8d77bb5bae34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705158138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3705158138
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2038084723
Short name T163
Test name
Test status
Simulation time 24087134562 ps
CPU time 30.52 seconds
Started Jul 01 10:48:30 AM PDT 24
Finished Jul 01 10:49:01 AM PDT 24
Peak memory 201744 kb
Host smart-437d0ba5-5fce-4615-a9aa-533c1f44cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038084723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.2038084723
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1902091626
Short name T56
Test name
Test status
Simulation time 2837968023 ps
CPU time 7.61 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:48:33 AM PDT 24
Peak memory 201472 kb
Host smart-6bc5d598-f674-44a3-b003-0b2651ec1cc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902091626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.1902091626
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.3726557165
Short name T1
Test name
Test status
Simulation time 3517168360 ps
CPU time 6.29 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:48:22 AM PDT 24
Peak memory 201484 kb
Host smart-2478c5e5-fae9-402c-9220-1823df846312
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726557165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.3726557165
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1672112937
Short name T431
Test name
Test status
Simulation time 2614394737 ps
CPU time 4.66 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201500 kb
Host smart-43603d13-743f-4cf7-b05b-b3e7d2cd5650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672112937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1672112937
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.4168449593
Short name T396
Test name
Test status
Simulation time 2451373297 ps
CPU time 4.21 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:29 AM PDT 24
Peak memory 201420 kb
Host smart-3dacf96f-e9fe-4a9c-8674-6e58e2df15c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168449593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.4168449593
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.756014053
Short name T394
Test name
Test status
Simulation time 2037742924 ps
CPU time 5.26 seconds
Started Jul 01 10:48:24 AM PDT 24
Finished Jul 01 10:48:32 AM PDT 24
Peak memory 201352 kb
Host smart-5f6b1fb6-02f9-4e13-ae8c-1ab3ff3da0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756014053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.756014053
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3081844407
Short name T129
Test name
Test status
Simulation time 2549241240 ps
CPU time 1.69 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:48:19 AM PDT 24
Peak memory 201536 kb
Host smart-60f99865-a87f-4650-ab7a-53e893199fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081844407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3081844407
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.2578325343
Short name T112
Test name
Test status
Simulation time 2113768602 ps
CPU time 5.98 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:30 AM PDT 24
Peak memory 201440 kb
Host smart-a14b1549-af8b-4524-90ed-c7bdbc534cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578325343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2578325343
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1125706224
Short name T563
Test name
Test status
Simulation time 201913878211 ps
CPU time 301.1 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:53:58 AM PDT 24
Peak memory 201508 kb
Host smart-ce3c3401-566e-4ea8-809e-f415d0d14099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125706224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1125706224
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.795854846
Short name T131
Test name
Test status
Simulation time 88995732251 ps
CPU time 122.92 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:50:29 AM PDT 24
Peak memory 210152 kb
Host smart-4e2d5268-d85a-47f4-b4de-8bc94d4ab7c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795854846 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.795854846
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3251893140
Short name T682
Test name
Test status
Simulation time 6064883452 ps
CPU time 0.95 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201548 kb
Host smart-1cecf1fc-5d59-4669-a81e-8c0a2ac84c0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251893140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.3251893140
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.2652088975
Short name T222
Test name
Test status
Simulation time 2026610942 ps
CPU time 2.02 seconds
Started Jul 01 10:47:44 AM PDT 24
Finished Jul 01 10:47:47 AM PDT 24
Peak memory 201488 kb
Host smart-e549b0f5-79f0-409b-9a0f-ffab53d6e535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652088975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.2652088975
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1094369712
Short name T522
Test name
Test status
Simulation time 4014136369 ps
CPU time 2.96 seconds
Started Jul 01 10:47:51 AM PDT 24
Finished Jul 01 10:47:54 AM PDT 24
Peak memory 201572 kb
Host smart-6bead272-a2f4-4a22-b8a7-b84e4f8e8c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094369712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1094369712
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2304288653
Short name T111
Test name
Test status
Simulation time 2276130804 ps
CPU time 2.05 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:26 AM PDT 24
Peak memory 201504 kb
Host smart-039baefc-da47-4c37-989d-8fa4f8b3dc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304288653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.2304288653
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3877033682
Short name T144
Test name
Test status
Simulation time 2300782808 ps
CPU time 6.36 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201468 kb
Host smart-be3807d4-b662-4592-a782-1d6ee9b44ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877033682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3877033682
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1212450993
Short name T399
Test name
Test status
Simulation time 4033727100 ps
CPU time 12.13 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:19 AM PDT 24
Peak memory 201500 kb
Host smart-cf102d09-fb08-46d1-9bb8-b17745d4bdb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212450993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.1212450993
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.942427883
Short name T498
Test name
Test status
Simulation time 4267931891 ps
CPU time 10.95 seconds
Started Jul 01 10:47:44 AM PDT 24
Finished Jul 01 10:47:56 AM PDT 24
Peak memory 201392 kb
Host smart-438b4b9c-ba71-4105-af56-eecc50cecb69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942427883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_edge_detect.942427883
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3821586435
Short name T717
Test name
Test status
Simulation time 2620199395 ps
CPU time 3.95 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201500 kb
Host smart-3a83d424-1e18-4fa8-93cf-8e3016248115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821586435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3821586435
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1890852363
Short name T518
Test name
Test status
Simulation time 2511933804 ps
CPU time 1.31 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 201436 kb
Host smart-c6fc0926-b97a-4d09-b584-f8b18c86b567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890852363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.1890852363
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.127015596
Short name T428
Test name
Test status
Simulation time 2050992234 ps
CPU time 1.66 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201440 kb
Host smart-b8701b26-2b52-450b-9ac9-af839ea55bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127015596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.127015596
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1102706888
Short name T501
Test name
Test status
Simulation time 2549544160 ps
CPU time 1.51 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201536 kb
Host smart-1fd28d18-6895-4de1-b056-7887e3fcd344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102706888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1102706888
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1846123821
Short name T294
Test name
Test status
Simulation time 42345108470 ps
CPU time 11.54 seconds
Started Jul 01 10:47:45 AM PDT 24
Finished Jul 01 10:47:57 AM PDT 24
Peak memory 221436 kb
Host smart-e48fabff-a87a-48ed-b59d-95e6f80c6d1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846123821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1846123821
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1918134206
Short name T489
Test name
Test status
Simulation time 2135713703 ps
CPU time 1.38 seconds
Started Jul 01 10:47:44 AM PDT 24
Finished Jul 01 10:47:45 AM PDT 24
Peak memory 201412 kb
Host smart-72531321-217f-4600-9fa2-053d3b24f985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918134206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1918134206
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.3292076599
Short name T13
Test name
Test status
Simulation time 10233162857 ps
CPU time 7.35 seconds
Started Jul 01 10:47:59 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 201524 kb
Host smart-7084c2d0-4ba8-4616-a801-abd06b1122d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292076599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.3292076599
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3791800449
Short name T132
Test name
Test status
Simulation time 6739429920 ps
CPU time 4.99 seconds
Started Jul 01 10:47:41 AM PDT 24
Finished Jul 01 10:47:47 AM PDT 24
Peak memory 201540 kb
Host smart-fba87e42-ae7d-4ef0-8214-e1a36a01f30e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791800449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.3791800449
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.4152845163
Short name T260
Test name
Test status
Simulation time 2133921149 ps
CPU time 1.02 seconds
Started Jul 01 10:48:13 AM PDT 24
Finished Jul 01 10:48:15 AM PDT 24
Peak memory 201468 kb
Host smart-3f041c3f-4329-4f49-a53b-2595eed8d935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152845163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.4152845163
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.319395451
Short name T424
Test name
Test status
Simulation time 3642182909 ps
CPU time 10.21 seconds
Started Jul 01 10:48:25 AM PDT 24
Finished Jul 01 10:48:37 AM PDT 24
Peak memory 201708 kb
Host smart-2638142d-e798-46c8-bea4-49de0567b1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319395451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.319395451
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2270050095
Short name T255
Test name
Test status
Simulation time 117256762662 ps
CPU time 72.58 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:50:28 AM PDT 24
Peak memory 201748 kb
Host smart-e38db8ba-812c-4a6e-a484-a38fd151cd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270050095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.2270050095
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3910828379
Short name T581
Test name
Test status
Simulation time 4712486755 ps
CPU time 3.15 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201528 kb
Host smart-5929a01e-f769-4100-8c61-27e3800c61a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910828379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3910828379
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3471333499
Short name T634
Test name
Test status
Simulation time 2404773148 ps
CPU time 6.45 seconds
Started Jul 01 10:48:43 AM PDT 24
Finished Jul 01 10:48:50 AM PDT 24
Peak memory 201392 kb
Host smart-34e2fc99-734c-4a0c-b923-a3d91c34755c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471333499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.3471333499
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3030469774
Short name T403
Test name
Test status
Simulation time 2625650139 ps
CPU time 3.23 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:48:29 AM PDT 24
Peak memory 201408 kb
Host smart-0e83b2bd-6904-43c5-8a73-785a4f26dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030469774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.3030469774
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3885798945
Short name T436
Test name
Test status
Simulation time 2462539312 ps
CPU time 7.59 seconds
Started Jul 01 10:48:44 AM PDT 24
Finished Jul 01 10:48:52 AM PDT 24
Peak memory 201516 kb
Host smart-da38c043-ec6a-402d-beb5-516498281018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885798945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3885798945
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.4078256262
Short name T734
Test name
Test status
Simulation time 2101575765 ps
CPU time 2.27 seconds
Started Jul 01 10:48:11 AM PDT 24
Finished Jul 01 10:48:14 AM PDT 24
Peak memory 201408 kb
Host smart-df9dbd41-468e-4a0b-b245-ff80b6a0487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078256262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.4078256262
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.296013832
Short name T458
Test name
Test status
Simulation time 2518591790 ps
CPU time 3.94 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:23 AM PDT 24
Peak memory 201472 kb
Host smart-d9706bf2-c485-4b64-9678-035bd92b2c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296013832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.296013832
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.713954625
Short name T716
Test name
Test status
Simulation time 2175654261 ps
CPU time 1.18 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201500 kb
Host smart-abec6180-e484-415f-95aa-a921e8264710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713954625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.713954625
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.360988637
Short name T220
Test name
Test status
Simulation time 5856606495 ps
CPU time 2.5 seconds
Started Jul 01 10:48:38 AM PDT 24
Finished Jul 01 10:48:41 AM PDT 24
Peak memory 201548 kb
Host smart-a5aaaa1e-5ca3-42c7-b843-a52b5e726286
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360988637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ultra_low_pwr.360988637
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.1674815292
Short name T619
Test name
Test status
Simulation time 2035588234 ps
CPU time 1.9 seconds
Started Jul 01 10:48:50 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201500 kb
Host smart-78a6a545-b62b-4046-adae-1b3652efce35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674815292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.1674815292
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.725092760
Short name T234
Test name
Test status
Simulation time 3351340350 ps
CPU time 8 seconds
Started Jul 01 10:48:28 AM PDT 24
Finished Jul 01 10:48:37 AM PDT 24
Peak memory 201476 kb
Host smart-695bd529-4522-4dac-b98c-aa0853e009e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725092760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.725092760
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3603113663
Short name T525
Test name
Test status
Simulation time 77246498675 ps
CPU time 187.19 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:51:23 AM PDT 24
Peak memory 201796 kb
Host smart-c694ccde-de6c-44ed-9d0d-54db65f6f927
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603113663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3603113663
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3675839939
Short name T368
Test name
Test status
Simulation time 148284641602 ps
CPU time 100.8 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 201792 kb
Host smart-81ef7ffb-1b0b-4083-9bd8-97cdb6fe9b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675839939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.3675839939
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1873275796
Short name T735
Test name
Test status
Simulation time 2658765655 ps
CPU time 2.32 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:17 AM PDT 24
Peak memory 201448 kb
Host smart-c31858c8-3c70-447f-9b73-1c687dd77e39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873275796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.1873275796
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3510543265
Short name T789
Test name
Test status
Simulation time 3234277401 ps
CPU time 2.77 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201472 kb
Host smart-dd446f9f-6aa2-4afd-9519-fa878315093f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510543265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.3510543265
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3525340467
Short name T296
Test name
Test status
Simulation time 2609364880 ps
CPU time 7.26 seconds
Started Jul 01 10:48:19 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201316 kb
Host smart-16454736-b2f8-4226-bcfe-84a90e299619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525340467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3525340467
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3948627330
Short name T550
Test name
Test status
Simulation time 2454493814 ps
CPU time 7.54 seconds
Started Jul 01 10:48:39 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 201508 kb
Host smart-f0702f7a-878b-4251-8147-18565a66301a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948627330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.3948627330
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.1074365264
Short name T675
Test name
Test status
Simulation time 2026024282 ps
CPU time 5.71 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201412 kb
Host smart-65e6dcac-e116-4575-8dc5-00ed8cd86c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074365264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1074365264
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2730978037
Short name T121
Test name
Test status
Simulation time 2521750353 ps
CPU time 2.18 seconds
Started Jul 01 10:48:48 AM PDT 24
Finished Jul 01 10:48:51 AM PDT 24
Peak memory 201416 kb
Host smart-7f7cb96e-c500-41e2-9260-c805936a9c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730978037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2730978037
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1068198605
Short name T464
Test name
Test status
Simulation time 2112026241 ps
CPU time 6.41 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:48:22 AM PDT 24
Peak memory 201380 kb
Host smart-b82efd2f-297e-41de-b772-c93478a176c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068198605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1068198605
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.787567900
Short name T516
Test name
Test status
Simulation time 14372530424 ps
CPU time 20.9 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:36 AM PDT 24
Peak memory 201624 kb
Host smart-a1c6da00-347c-4486-9473-fa5a6e636207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787567900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_st
ress_all.787567900
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3015014470
Short name T534
Test name
Test status
Simulation time 34891417945 ps
CPU time 49.61 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:49:05 AM PDT 24
Peak memory 210096 kb
Host smart-141a180a-330c-4b61-8dd0-a47475874a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015014470 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3015014470
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2356974624
Short name T738
Test name
Test status
Simulation time 4276205984 ps
CPU time 6.63 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:48:22 AM PDT 24
Peak memory 201460 kb
Host smart-d7a17057-de5c-4c45-8b0d-5ba1911ef6bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356974624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.2356974624
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.3948680959
Short name T576
Test name
Test status
Simulation time 2010959544 ps
CPU time 5.55 seconds
Started Jul 01 10:48:39 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 201432 kb
Host smart-e864b244-001c-4eb0-be83-9d17c318855c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948680959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.3948680959
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.502005631
Short name T770
Test name
Test status
Simulation time 2891339123 ps
CPU time 2.19 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201536 kb
Host smart-0b8eadec-d5a1-4a22-95af-241ac22964e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502005631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.502005631
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2347933989
Short name T381
Test name
Test status
Simulation time 204568707517 ps
CPU time 33.35 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 201772 kb
Host smart-8bf652db-1c08-4b7e-9a90-38d2fcdc5e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347933989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.2347933989
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1322528025
Short name T443
Test name
Test status
Simulation time 3972810088 ps
CPU time 5.21 seconds
Started Jul 01 10:48:24 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201464 kb
Host smart-9a6b8602-713a-4a93-8d88-3d1c84906954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322528025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.1322528025
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.3886546993
Short name T772
Test name
Test status
Simulation time 1198450683138 ps
CPU time 865.74 seconds
Started Jul 01 10:48:51 AM PDT 24
Finished Jul 01 11:03:17 AM PDT 24
Peak memory 201536 kb
Host smart-8efa5b67-dc86-4826-82a3-a70d12d83d72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886546993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.3886546993
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.607041080
Short name T646
Test name
Test status
Simulation time 2626886219 ps
CPU time 2.48 seconds
Started Jul 01 10:48:41 AM PDT 24
Finished Jul 01 10:48:44 AM PDT 24
Peak memory 201452 kb
Host smart-ed42a224-7ec0-4540-8a13-6e673988ba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607041080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.607041080
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.1567228367
Short name T435
Test name
Test status
Simulation time 2486507246 ps
CPU time 1.98 seconds
Started Jul 01 10:48:24 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201444 kb
Host smart-46308a7e-2bd2-4b65-a04a-6d0708021973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567228367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.1567228367
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3582830015
Short name T168
Test name
Test status
Simulation time 2116652244 ps
CPU time 3.2 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:24 AM PDT 24
Peak memory 201256 kb
Host smart-1398909a-7fb1-4903-83dd-cff2232e516c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582830015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3582830015
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.3655726351
Short name T603
Test name
Test status
Simulation time 2534633456 ps
CPU time 1.7 seconds
Started Jul 01 10:48:24 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201444 kb
Host smart-307a1f41-3ae9-4415-94ab-f921a6dbcfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655726351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.3655726351
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.573730382
Short name T681
Test name
Test status
Simulation time 2114320836 ps
CPU time 5.43 seconds
Started Jul 01 10:49:04 AM PDT 24
Finished Jul 01 10:49:10 AM PDT 24
Peak memory 201348 kb
Host smart-d25a9780-acc7-46b6-af18-4c94679055d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573730382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.573730382
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.161289183
Short name T496
Test name
Test status
Simulation time 9951910662 ps
CPU time 25.81 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:47 AM PDT 24
Peak memory 201424 kb
Host smart-22c8c1bf-c789-425f-9eb2-573867fe30f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161289183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.161289183
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2579200863
Short name T274
Test name
Test status
Simulation time 45470278759 ps
CPU time 56.98 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:49:15 AM PDT 24
Peak memory 210192 kb
Host smart-decf7182-72b1-411a-a99a-bdd595676386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579200863 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2579200863
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3933060741
Short name T569
Test name
Test status
Simulation time 5636611273 ps
CPU time 2.37 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 201352 kb
Host smart-96725caa-8c5a-4359-9cb5-9c2724a9b3c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933060741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3933060741
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.3489190118
Short name T777
Test name
Test status
Simulation time 2034419896 ps
CPU time 1.96 seconds
Started Jul 01 10:48:40 AM PDT 24
Finished Jul 01 10:48:42 AM PDT 24
Peak memory 201512 kb
Host smart-2d4bbdd2-03cc-4ea3-bff1-c6072a2c9500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489190118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.3489190118
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3775976698
Short name T784
Test name
Test status
Simulation time 3250715324 ps
CPU time 1.02 seconds
Started Jul 01 10:49:00 AM PDT 24
Finished Jul 01 10:49:01 AM PDT 24
Peak memory 201604 kb
Host smart-f1aebfc9-33b9-421c-89d3-f4355af6f82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775976698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3
775976698
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.1039872835
Short name T339
Test name
Test status
Simulation time 196260838065 ps
CPU time 261.05 seconds
Started Jul 01 10:48:36 AM PDT 24
Finished Jul 01 10:52:58 AM PDT 24
Peak memory 201816 kb
Host smart-a2397b06-fcbd-4e96-9950-dc3be9401e13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039872835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.1039872835
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1735776675
Short name T732
Test name
Test status
Simulation time 4281250963 ps
CPU time 6.33 seconds
Started Jul 01 10:48:27 AM PDT 24
Finished Jul 01 10:48:33 AM PDT 24
Peak memory 201444 kb
Host smart-36b5a8bc-8643-48a2-9b60-f9e49b9e1ca5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735776675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.1735776675
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.1694591019
Short name T66
Test name
Test status
Simulation time 3768445626 ps
CPU time 10.45 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:35 AM PDT 24
Peak memory 201536 kb
Host smart-5b4e16d2-553b-4878-a239-6539aa615b75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694591019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.1694591019
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1475961617
Short name T205
Test name
Test status
Simulation time 2630754133 ps
CPU time 2.17 seconds
Started Jul 01 10:48:24 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201480 kb
Host smart-3c905af4-a025-4e5e-b91d-8d25d5a57d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475961617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1475961617
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2975176007
Short name T760
Test name
Test status
Simulation time 2612856653 ps
CPU time 1.02 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:26 AM PDT 24
Peak memory 201484 kb
Host smart-08253d42-5e51-471d-8524-65121a35e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975176007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2975176007
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3862224628
Short name T446
Test name
Test status
Simulation time 2223458115 ps
CPU time 6.07 seconds
Started Jul 01 10:48:57 AM PDT 24
Finished Jul 01 10:49:04 AM PDT 24
Peak memory 201496 kb
Host smart-4d75b247-8fbe-4cdd-b588-0714ef1bf9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862224628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.3862224628
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.878969282
Short name T597
Test name
Test status
Simulation time 2513564165 ps
CPU time 7.26 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:29 AM PDT 24
Peak memory 201500 kb
Host smart-f8167ad6-e8ba-4dec-976e-c4fdc3dc9994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878969282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.878969282
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.3184683629
Short name T113
Test name
Test status
Simulation time 2113354556 ps
CPU time 6.48 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201412 kb
Host smart-178b2bae-f5a4-4d54-bedf-a589352ccc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184683629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3184683629
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.4209691872
Short name T442
Test name
Test status
Simulation time 15880327890 ps
CPU time 11.58 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:30 AM PDT 24
Peak memory 201488 kb
Host smart-11ec529b-5fc9-40f8-b367-f938a47ecc80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209691872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.4209691872
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2671542520
Short name T73
Test name
Test status
Simulation time 7950874188 ps
CPU time 7.83 seconds
Started Jul 01 10:48:46 AM PDT 24
Finished Jul 01 10:48:55 AM PDT 24
Peak memory 201412 kb
Host smart-2a950f3e-79f0-4640-b880-e195ef16a6e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671542520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.2671542520
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.345850067
Short name T389
Test name
Test status
Simulation time 2011472252 ps
CPU time 5.6 seconds
Started Jul 01 10:48:51 AM PDT 24
Finished Jul 01 10:48:58 AM PDT 24
Peak memory 201388 kb
Host smart-9247ce23-7bb5-4ce6-96f8-86cd3cd97e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345850067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_tes
t.345850067
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.442643828
Short name T596
Test name
Test status
Simulation time 3000891646 ps
CPU time 2.47 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201572 kb
Host smart-4d73eafb-b24b-4684-8efe-300b1303f092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442643828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.442643828
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2446312734
Short name T375
Test name
Test status
Simulation time 157412461853 ps
CPU time 194.04 seconds
Started Jul 01 10:48:38 AM PDT 24
Finished Jul 01 10:51:53 AM PDT 24
Peak memory 201728 kb
Host smart-53f07054-1c33-403d-bf0d-4e884742b00e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446312734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2446312734
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.2807523213
Short name T779
Test name
Test status
Simulation time 3295832750 ps
CPU time 2.84 seconds
Started Jul 01 10:48:27 AM PDT 24
Finished Jul 01 10:48:30 AM PDT 24
Peak memory 201476 kb
Host smart-a78121d4-c57e-4889-bd20-0857acaf4292
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807523213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.2807523213
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.99109240
Short name T174
Test name
Test status
Simulation time 4481864164 ps
CPU time 3.37 seconds
Started Jul 01 10:49:03 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 201532 kb
Host smart-f199f624-6be1-4663-ba77-482456d145b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99109240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl
_edge_detect.99109240
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3744231558
Short name T729
Test name
Test status
Simulation time 2615782497 ps
CPU time 3.97 seconds
Started Jul 01 10:48:24 AM PDT 24
Finished Jul 01 10:48:30 AM PDT 24
Peak memory 201480 kb
Host smart-b2b2d640-9bb0-47bc-94db-cf2935924ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744231558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3744231558
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.225869248
Short name T600
Test name
Test status
Simulation time 2470948723 ps
CPU time 2.81 seconds
Started Jul 01 10:48:59 AM PDT 24
Finished Jul 01 10:49:03 AM PDT 24
Peak memory 201520 kb
Host smart-49349b04-18c8-4c14-a1ee-2d193ac517af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225869248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.225869248
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1248957266
Short name T637
Test name
Test status
Simulation time 2203731487 ps
CPU time 2.23 seconds
Started Jul 01 10:48:21 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201524 kb
Host smart-c922454e-3deb-446d-bcd6-2eda8a58d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248957266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1248957266
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2468244852
Short name T480
Test name
Test status
Simulation time 2511164031 ps
CPU time 7.45 seconds
Started Jul 01 10:48:27 AM PDT 24
Finished Jul 01 10:48:35 AM PDT 24
Peak memory 201504 kb
Host smart-fe88f6b6-8d2c-4756-9249-b36009ee3ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468244852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2468244852
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.155445091
Short name T547
Test name
Test status
Simulation time 2135833418 ps
CPU time 1.81 seconds
Started Jul 01 10:48:54 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 201440 kb
Host smart-eb6f69ca-6986-40fd-9535-a1d314cb2383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155445091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.155445091
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.3974219229
Short name T684
Test name
Test status
Simulation time 6679276017 ps
CPU time 4.01 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:28 AM PDT 24
Peak memory 201512 kb
Host smart-5404af46-beec-4dad-b25e-b2e258768c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974219229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.3974219229
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.311152702
Short name T122
Test name
Test status
Simulation time 24766656664 ps
CPU time 54.05 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:49:51 AM PDT 24
Peak memory 218144 kb
Host smart-d06c253e-7647-479e-b2a8-837a2beb88ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311152702 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.311152702
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1085537061
Short name T140
Test name
Test status
Simulation time 5843015752 ps
CPU time 7.08 seconds
Started Jul 01 10:48:45 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201580 kb
Host smart-b0726e85-78d6-4e5f-bbe7-50c775d72821
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085537061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1085537061
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.3576243478
Short name T626
Test name
Test status
Simulation time 2039871359 ps
CPU time 2.04 seconds
Started Jul 01 10:49:09 AM PDT 24
Finished Jul 01 10:49:12 AM PDT 24
Peak memory 201520 kb
Host smart-6d1d91e9-2117-48c6-9fe1-e8e22af5f99a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576243478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.3576243478
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2946897019
Short name T745
Test name
Test status
Simulation time 3075921315 ps
CPU time 8.71 seconds
Started Jul 01 10:48:40 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201440 kb
Host smart-0cfa9905-bd8a-459e-bc18-84793ba583c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946897019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.2
946897019
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1442583204
Short name T103
Test name
Test status
Simulation time 88475519095 ps
CPU time 219.08 seconds
Started Jul 01 10:48:27 AM PDT 24
Finished Jul 01 10:52:07 AM PDT 24
Peak memory 201720 kb
Host smart-c930c437-f088-4d19-833b-3888457318ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442583204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1442583204
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1414081620
Short name T750
Test name
Test status
Simulation time 2835749311 ps
CPU time 8.15 seconds
Started Jul 01 10:48:52 AM PDT 24
Finished Jul 01 10:49:01 AM PDT 24
Peak memory 201408 kb
Host smart-89674080-999d-4b38-b032-770ec093e38b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414081620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.1414081620
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2869470186
Short name T149
Test name
Test status
Simulation time 4942601449 ps
CPU time 6.76 seconds
Started Jul 01 10:48:31 AM PDT 24
Finished Jul 01 10:48:38 AM PDT 24
Peak memory 201456 kb
Host smart-a39aa8db-950d-4019-8753-0eb665907851
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869470186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.2869470186
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3291998445
Short name T584
Test name
Test status
Simulation time 2609785542 ps
CPU time 7.42 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:29 AM PDT 24
Peak memory 201388 kb
Host smart-7795a7c4-ec6d-46d7-9f0b-847f19209c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291998445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3291998445
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2817949291
Short name T590
Test name
Test status
Simulation time 2477939553 ps
CPU time 2.35 seconds
Started Jul 01 10:48:31 AM PDT 24
Finished Jul 01 10:48:33 AM PDT 24
Peak memory 201428 kb
Host smart-937f5fbe-7462-4a58-9bb3-0853c3cd0228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817949291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.2817949291
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2771236046
Short name T617
Test name
Test status
Simulation time 2112807751 ps
CPU time 1.3 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:48:27 AM PDT 24
Peak memory 201420 kb
Host smart-57fd959e-5de5-42ac-ad04-9e27d8a8c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771236046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2771236046
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3762351907
Short name T200
Test name
Test status
Simulation time 2528925331 ps
CPU time 1.88 seconds
Started Jul 01 10:48:35 AM PDT 24
Finished Jul 01 10:48:37 AM PDT 24
Peak memory 201520 kb
Host smart-6a58a8b1-4267-410f-a2bf-aa8cf69b4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762351907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3762351907
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.176568929
Short name T505
Test name
Test status
Simulation time 2136910982 ps
CPU time 1.73 seconds
Started Jul 01 10:48:47 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201364 kb
Host smart-8b1d7a09-f22b-4243-a4ff-88b2b39f1fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176568929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.176568929
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.2855798296
Short name T240
Test name
Test status
Simulation time 86576585403 ps
CPU time 214.31 seconds
Started Jul 01 10:48:28 AM PDT 24
Finished Jul 01 10:52:03 AM PDT 24
Peak memory 201784 kb
Host smart-f848724a-3bf0-4bcf-a16a-ce92e707c000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855798296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.2855798296
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2207752379
Short name T71
Test name
Test status
Simulation time 2019498787896 ps
CPU time 55.75 seconds
Started Jul 01 10:49:10 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 201556 kb
Host smart-87840fc9-36fd-4f8c-a2c7-97eb84d2f7a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207752379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.2207752379
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.341428169
Short name T421
Test name
Test status
Simulation time 2052741502 ps
CPU time 1.12 seconds
Started Jul 01 10:48:55 AM PDT 24
Finished Jul 01 10:48:57 AM PDT 24
Peak memory 201408 kb
Host smart-8af2c050-593a-4299-b656-da2549625475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341428169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_tes
t.341428169
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.960818955
Short name T300
Test name
Test status
Simulation time 3217845831 ps
CPU time 2.82 seconds
Started Jul 01 10:49:01 AM PDT 24
Finished Jul 01 10:49:04 AM PDT 24
Peak memory 201440 kb
Host smart-faf1e40c-4d01-4781-a308-ba8b1a78ddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960818955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.960818955
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.904744200
Short name T249
Test name
Test status
Simulation time 37150563035 ps
CPU time 48.47 seconds
Started Jul 01 10:48:48 AM PDT 24
Finished Jul 01 10:49:37 AM PDT 24
Peak memory 201800 kb
Host smart-3f230487-e344-4f2f-9d3d-76d49bd91774
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904744200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_combo_detect.904744200
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.241489570
Short name T261
Test name
Test status
Simulation time 4126035126 ps
CPU time 11.31 seconds
Started Jul 01 10:48:51 AM PDT 24
Finished Jul 01 10:49:03 AM PDT 24
Peak memory 201384 kb
Host smart-eb4cac6d-b5f1-4345-b9b6-67aa51c550e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241489570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ec_pwr_on_rst.241489570
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2503955298
Short name T488
Test name
Test status
Simulation time 2589311124 ps
CPU time 3.36 seconds
Started Jul 01 10:48:27 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201488 kb
Host smart-c4f7dbcf-2c39-4e36-95ae-79bddb74cd4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503955298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2503955298
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1785817024
Short name T614
Test name
Test status
Simulation time 2615501553 ps
CPU time 3.72 seconds
Started Jul 01 10:48:44 AM PDT 24
Finished Jul 01 10:48:48 AM PDT 24
Peak memory 201432 kb
Host smart-5e8ffebb-28a8-4d7f-b247-a21dff422b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785817024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1785817024
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1061825550
Short name T524
Test name
Test status
Simulation time 2460889023 ps
CPU time 7.84 seconds
Started Jul 01 10:48:27 AM PDT 24
Finished Jul 01 10:48:36 AM PDT 24
Peak memory 201484 kb
Host smart-40f12c18-77bb-4776-ac58-e3e4f8aed0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061825550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1061825550
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2556419672
Short name T298
Test name
Test status
Simulation time 2174474422 ps
CPU time 6.54 seconds
Started Jul 01 10:48:28 AM PDT 24
Finished Jul 01 10:48:35 AM PDT 24
Peak memory 201456 kb
Host smart-cea1ddb4-6e8f-4ed0-b47a-689a535501a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556419672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2556419672
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3019871757
Short name T441
Test name
Test status
Simulation time 2514515217 ps
CPU time 4.22 seconds
Started Jul 01 10:48:28 AM PDT 24
Finished Jul 01 10:48:34 AM PDT 24
Peak memory 201488 kb
Host smart-f9345875-01ce-4629-a6e6-46f8ba177176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019871757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3019871757
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.2223816653
Short name T411
Test name
Test status
Simulation time 2121030616 ps
CPU time 2.16 seconds
Started Jul 01 10:48:28 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201424 kb
Host smart-8c244d03-49d7-45ea-8413-2c64a4593f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223816653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.2223816653
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.3446479992
Short name T473
Test name
Test status
Simulation time 6918078381 ps
CPU time 17.31 seconds
Started Jul 01 10:48:27 AM PDT 24
Finished Jul 01 10:48:45 AM PDT 24
Peak memory 201516 kb
Host smart-76cceca1-a3b8-40af-8107-f1f2f61ceda6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446479992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.3446479992
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2332416268
Short name T207
Test name
Test status
Simulation time 158571111694 ps
CPU time 97.77 seconds
Started Jul 01 10:48:58 AM PDT 24
Finished Jul 01 10:50:36 AM PDT 24
Peak memory 210128 kb
Host smart-f28bfd67-2ee1-4db1-a641-9a81508acbdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332416268 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2332416268
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1566829053
Short name T383
Test name
Test status
Simulation time 1416851284952 ps
CPU time 27.35 seconds
Started Jul 01 10:48:50 AM PDT 24
Finished Jul 01 10:49:17 AM PDT 24
Peak memory 201808 kb
Host smart-cb22d262-e829-43fa-aff8-479dac6a9a97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566829053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.1566829053
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.1220227680
Short name T16
Test name
Test status
Simulation time 2067793145 ps
CPU time 1.24 seconds
Started Jul 01 10:48:38 AM PDT 24
Finished Jul 01 10:48:39 AM PDT 24
Peak memory 201476 kb
Host smart-2a5a05e0-c758-4070-8a01-a3f115376f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220227680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.1220227680
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1079021518
Short name T465
Test name
Test status
Simulation time 3437372159 ps
CPU time 1.28 seconds
Started Jul 01 10:48:55 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 201604 kb
Host smart-d9f9d918-3171-4873-851a-64c12ea13843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079021518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.1
079021518
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.725687051
Short name T106
Test name
Test status
Simulation time 188007202005 ps
CPU time 77.94 seconds
Started Jul 01 10:48:32 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 201832 kb
Host smart-1cf8b4c6-8faa-47d5-a88e-6015102e2214
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725687051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_combo_detect.725687051
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3052494152
Short name T77
Test name
Test status
Simulation time 88845072916 ps
CPU time 60.38 seconds
Started Jul 01 10:48:44 AM PDT 24
Finished Jul 01 10:49:44 AM PDT 24
Peak memory 201724 kb
Host smart-c0028440-7071-4ec9-8f5c-c580d83be6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052494152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.3052494152
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2751798444
Short name T406
Test name
Test status
Simulation time 3648874646 ps
CPU time 2.76 seconds
Started Jul 01 10:48:50 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201476 kb
Host smart-2704f508-1142-493c-8a74-bece3f760529
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751798444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.2751798444
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.3393229719
Short name T178
Test name
Test status
Simulation time 2499696052 ps
CPU time 2.19 seconds
Started Jul 01 10:48:46 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201520 kb
Host smart-78c42698-5ad5-4dff-8172-0dbc4e492d23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393229719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.3393229719
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2460980090
Short name T215
Test name
Test status
Simulation time 2622089197 ps
CPU time 4.07 seconds
Started Jul 01 10:48:34 AM PDT 24
Finished Jul 01 10:48:38 AM PDT 24
Peak memory 201528 kb
Host smart-8194d31a-2646-4503-aa42-54234533400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460980090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.2460980090
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3657100209
Short name T417
Test name
Test status
Simulation time 2472895675 ps
CPU time 3.01 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:49:00 AM PDT 24
Peak memory 201376 kb
Host smart-1384d199-2ab7-4853-99c9-abf21bf6826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657100209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3657100209
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.803152967
Short name T562
Test name
Test status
Simulation time 2271649096 ps
CPU time 2.17 seconds
Started Jul 01 10:48:35 AM PDT 24
Finished Jul 01 10:48:38 AM PDT 24
Peak memory 201484 kb
Host smart-946f0418-95ea-456a-b500-e6bd86299864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803152967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.803152967
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.2953262419
Short name T669
Test name
Test status
Simulation time 2518595176 ps
CPU time 3.83 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:48:57 AM PDT 24
Peak memory 201488 kb
Host smart-0b546872-3475-43be-830a-59266c4a8d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953262419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.2953262419
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.1439748200
Short name T546
Test name
Test status
Simulation time 2129209656 ps
CPU time 1.75 seconds
Started Jul 01 10:48:51 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201412 kb
Host smart-348a68c0-49d8-4581-9d44-b167153cfcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439748200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.1439748200
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1420552940
Short name T33
Test name
Test status
Simulation time 11568660548 ps
CPU time 2.63 seconds
Started Jul 01 10:49:07 AM PDT 24
Finished Jul 01 10:49:10 AM PDT 24
Peak memory 201532 kb
Host smart-07b8de4d-a74a-4f16-bd58-5361c7023920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420552940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1420552940
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.212139984
Short name T586
Test name
Test status
Simulation time 7981995243 ps
CPU time 7.73 seconds
Started Jul 01 10:48:40 AM PDT 24
Finished Jul 01 10:48:48 AM PDT 24
Peak memory 201564 kb
Host smart-3113caca-971a-443a-9e32-e9dc60f144cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212139984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ultra_low_pwr.212139984
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.775874362
Short name T594
Test name
Test status
Simulation time 2051447449 ps
CPU time 1.79 seconds
Started Jul 01 10:48:51 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201492 kb
Host smart-6922a9a8-5163-4c5c-bd13-e29917962188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775874362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_tes
t.775874362
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2586958350
Short name T696
Test name
Test status
Simulation time 3225705679 ps
CPU time 4.65 seconds
Started Jul 01 10:48:33 AM PDT 24
Finished Jul 01 10:48:38 AM PDT 24
Peak memory 201448 kb
Host smart-a7ae59c6-6d1d-4427-b971-113dacbba333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586958350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2
586958350
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.592092012
Short name T342
Test name
Test status
Simulation time 108591236740 ps
CPU time 41.43 seconds
Started Jul 01 10:48:54 AM PDT 24
Finished Jul 01 10:49:36 AM PDT 24
Peak memory 201724 kb
Host smart-7d5829aa-574e-42d7-aa4c-5bddbb0d1bbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592092012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_combo_detect.592092012
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1713144631
Short name T430
Test name
Test status
Simulation time 2932864487 ps
CPU time 8.41 seconds
Started Jul 01 10:48:32 AM PDT 24
Finished Jul 01 10:48:41 AM PDT 24
Peak memory 201368 kb
Host smart-88ce9354-0b27-4a59-9f6c-142d7ee98b90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713144631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.1713144631
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.116194527
Short name T694
Test name
Test status
Simulation time 3970409351 ps
CPU time 6.02 seconds
Started Jul 01 10:48:55 AM PDT 24
Finished Jul 01 10:49:02 AM PDT 24
Peak memory 201492 kb
Host smart-5e637890-c9b3-48be-8e3f-6dddd3c55889
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116194527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctr
l_edge_detect.116194527
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.930632130
Short name T15
Test name
Test status
Simulation time 2612472185 ps
CPU time 7.86 seconds
Started Jul 01 10:48:35 AM PDT 24
Finished Jul 01 10:48:43 AM PDT 24
Peak memory 201448 kb
Host smart-5b21833a-0f86-4b42-86f6-502f987c5796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930632130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.930632130
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.2827818945
Short name T448
Test name
Test status
Simulation time 2451595513 ps
CPU time 2.96 seconds
Started Jul 01 10:48:51 AM PDT 24
Finished Jul 01 10:48:55 AM PDT 24
Peak memory 201508 kb
Host smart-7e66c6f4-6d25-45c8-a2a2-a2bf06217fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827818945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2827818945
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1673001995
Short name T606
Test name
Test status
Simulation time 2148112414 ps
CPU time 2.02 seconds
Started Jul 01 10:48:37 AM PDT 24
Finished Jul 01 10:48:40 AM PDT 24
Peak memory 201520 kb
Host smart-38045e5e-12f7-4f1c-8de6-a6aaa4b8472c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673001995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.1673001995
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.3376133306
Short name T593
Test name
Test status
Simulation time 2542177931 ps
CPU time 1.62 seconds
Started Jul 01 10:48:52 AM PDT 24
Finished Jul 01 10:48:54 AM PDT 24
Peak memory 201448 kb
Host smart-4dba4e16-a699-4fe2-a920-dc8f276056f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376133306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.3376133306
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.2175835005
Short name T616
Test name
Test status
Simulation time 2144695932 ps
CPU time 1.58 seconds
Started Jul 01 10:48:35 AM PDT 24
Finished Jul 01 10:48:37 AM PDT 24
Peak memory 201392 kb
Host smart-a014b252-7aa1-4d04-b923-7858172b6513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175835005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.2175835005
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3800954414
Short name T6
Test name
Test status
Simulation time 14138705997 ps
CPU time 35.48 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 201668 kb
Host smart-6198a66d-6c95-430e-92ad-fa9cc26c73b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800954414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3800954414
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3352491454
Short name T211
Test name
Test status
Simulation time 544994353925 ps
CPU time 63.26 seconds
Started Jul 01 10:48:52 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 210188 kb
Host smart-97a49e91-91a3-494a-a1e0-cd979472b5f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352491454 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.3352491454
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.4130057936
Short name T81
Test name
Test status
Simulation time 672989276275 ps
CPU time 26.97 seconds
Started Jul 01 10:48:34 AM PDT 24
Finished Jul 01 10:49:02 AM PDT 24
Peak memory 201568 kb
Host smart-41145622-f316-41d0-b266-4c900dd8e356
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130057936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.4130057936
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.1515404858
Short name T512
Test name
Test status
Simulation time 2052066250 ps
CPU time 1.64 seconds
Started Jul 01 10:48:35 AM PDT 24
Finished Jul 01 10:48:37 AM PDT 24
Peak memory 201464 kb
Host smart-89d23ef0-7c97-4a7f-a61b-94e3e6b66410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515404858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.1515404858
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.908651977
Short name T397
Test name
Test status
Simulation time 3461472678 ps
CPU time 4.96 seconds
Started Jul 01 10:49:05 AM PDT 24
Finished Jul 01 10:49:10 AM PDT 24
Peak memory 201604 kb
Host smart-58bf0063-7b1e-4e83-897e-deec8e06fe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908651977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.908651977
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1846285028
Short name T185
Test name
Test status
Simulation time 162398431114 ps
CPU time 95.05 seconds
Started Jul 01 10:49:09 AM PDT 24
Finished Jul 01 10:50:45 AM PDT 24
Peak memory 201688 kb
Host smart-a832c4d2-4fdb-478a-a645-4f3cffea5eb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846285028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.1846285028
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1643761360
Short name T625
Test name
Test status
Simulation time 3868658404 ps
CPU time 11.15 seconds
Started Jul 01 10:48:38 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201460 kb
Host smart-5017d232-2973-4ebc-8a8e-4742a92e36e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643761360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.1643761360
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.769312116
Short name T176
Test name
Test status
Simulation time 3112327348 ps
CPU time 7.48 seconds
Started Jul 01 10:48:54 AM PDT 24
Finished Jul 01 10:49:02 AM PDT 24
Peak memory 201436 kb
Host smart-890f5381-5028-4ca5-85ec-b240afc71cd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769312116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctr
l_edge_detect.769312116
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3556838614
Short name T181
Test name
Test status
Simulation time 2611373839 ps
CPU time 7.64 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:48:50 AM PDT 24
Peak memory 201312 kb
Host smart-a8a1d74c-5d9c-409f-8b0f-cc2987ced068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556838614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3556838614
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1035711566
Short name T713
Test name
Test status
Simulation time 2443589148 ps
CPU time 7.44 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:26 AM PDT 24
Peak memory 201524 kb
Host smart-71dcf5b9-46e0-4b29-bb65-71f1dd98cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035711566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.1035711566
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.4145250862
Short name T463
Test name
Test status
Simulation time 2249504492 ps
CPU time 6.39 seconds
Started Jul 01 10:48:38 AM PDT 24
Finished Jul 01 10:48:45 AM PDT 24
Peak memory 201492 kb
Host smart-2954da6a-2025-40fb-8c64-bc6b398700f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145250862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.4145250862
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1119033614
Short name T482
Test name
Test status
Simulation time 2560068284 ps
CPU time 1.73 seconds
Started Jul 01 10:48:40 AM PDT 24
Finished Jul 01 10:48:42 AM PDT 24
Peak memory 201504 kb
Host smart-9e2ef254-06c9-4e2c-a4af-0027792cf16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119033614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.1119033614
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.109715208
Short name T568
Test name
Test status
Simulation time 2113062133 ps
CPU time 6.17 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201248 kb
Host smart-734c679d-c1a5-4371-885b-2931e2e46594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109715208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.109715208
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1486126373
Short name T315
Test name
Test status
Simulation time 33414118998 ps
CPU time 80.06 seconds
Started Jul 01 10:49:07 AM PDT 24
Finished Jul 01 10:50:28 AM PDT 24
Peak memory 210260 kb
Host smart-fe29d57e-25a9-41dd-a7d9-52f1b84ac63a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486126373 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1486126373
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1112332501
Short name T697
Test name
Test status
Simulation time 6882883251 ps
CPU time 8.05 seconds
Started Jul 01 10:48:37 AM PDT 24
Finished Jul 01 10:48:45 AM PDT 24
Peak memory 201540 kb
Host smart-91e89564-7bee-42fb-a5b7-23ae7e02b714
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112332501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.1112332501
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1387112836
Short name T110
Test name
Test status
Simulation time 2103244875 ps
CPU time 1.01 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:47:59 AM PDT 24
Peak memory 201420 kb
Host smart-8358d0c3-d96e-4fc1-97e4-61c4e61b9704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387112836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1387112836
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2202083146
Short name T102
Test name
Test status
Simulation time 319181991847 ps
CPU time 217.39 seconds
Started Jul 01 10:48:04 AM PDT 24
Finished Jul 01 10:51:43 AM PDT 24
Peak memory 201548 kb
Host smart-4f2bec83-726e-496e-ba4e-b587ce7923d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202083146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.2202083146
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1538939600
Short name T337
Test name
Test status
Simulation time 127841552083 ps
CPU time 274.39 seconds
Started Jul 01 10:48:09 AM PDT 24
Finished Jul 01 10:52:44 AM PDT 24
Peak memory 201656 kb
Host smart-c9313bc9-08cf-4109-8eee-b6b80bf21ab3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538939600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.1538939600
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3688234994
Short name T647
Test name
Test status
Simulation time 2184546980 ps
CPU time 6.52 seconds
Started Jul 01 10:47:40 AM PDT 24
Finished Jul 01 10:47:47 AM PDT 24
Peak memory 201468 kb
Host smart-7052c9e4-1f45-42e8-8998-15d5b4ee4c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688234994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3688234994
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.812823883
Short name T759
Test name
Test status
Simulation time 2375567660 ps
CPU time 2.14 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:48:09 AM PDT 24
Peak memory 201508 kb
Host smart-683edcb1-66da-4491-8c59-cc3b32137a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812823883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.812823883
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.582499797
Short name T359
Test name
Test status
Simulation time 31320264640 ps
CPU time 84.37 seconds
Started Jul 01 10:48:09 AM PDT 24
Finished Jul 01 10:49:35 AM PDT 24
Peak memory 201756 kb
Host smart-7ff0a08f-ebb3-4beb-b3a6-1b1d1ffd5940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582499797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wit
h_pre_cond.582499797
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2537937509
Short name T470
Test name
Test status
Simulation time 4580998115 ps
CPU time 12.96 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:52 AM PDT 24
Peak memory 201508 kb
Host smart-8f1e488a-3780-486a-b56d-62340d5f973a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537937509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.2537937509
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.602747997
Short name T170
Test name
Test status
Simulation time 2613747119 ps
CPU time 7.64 seconds
Started Jul 01 10:47:38 AM PDT 24
Finished Jul 01 10:47:46 AM PDT 24
Peak memory 201476 kb
Host smart-6aa2d72c-685e-4c39-a33f-99e7a32dc168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602747997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.602747997
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.623961137
Short name T221
Test name
Test status
Simulation time 2469746883 ps
CPU time 3.73 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:11 AM PDT 24
Peak memory 201348 kb
Host smart-8ddb4dc9-1037-45c3-bfde-45bdc4ed0dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623961137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.623961137
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.2952253993
Short name T171
Test name
Test status
Simulation time 2131680718 ps
CPU time 1.11 seconds
Started Jul 01 10:47:52 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 201452 kb
Host smart-ec72267f-130f-493e-b7f0-66bc965058a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952253993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2952253993
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2217090926
Short name T165
Test name
Test status
Simulation time 2562373199 ps
CPU time 1.32 seconds
Started Jul 01 10:48:12 AM PDT 24
Finished Jul 01 10:48:14 AM PDT 24
Peak memory 201504 kb
Host smart-bd85b133-6c5b-49b4-a85e-30ff2f903335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217090926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2217090926
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3109336199
Short name T271
Test name
Test status
Simulation time 42029471791 ps
CPU time 64.62 seconds
Started Jul 01 10:47:41 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 221388 kb
Host smart-e85ebf6a-d970-4ae8-96f3-9c95a852a38b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109336199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3109336199
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2732254724
Short name T570
Test name
Test status
Simulation time 2113285195 ps
CPU time 6.08 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:48:05 AM PDT 24
Peak memory 201352 kb
Host smart-2c2bf91c-12c1-42a7-9638-060098769e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732254724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2732254724
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.1645840458
Short name T692
Test name
Test status
Simulation time 10401092463 ps
CPU time 26.07 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:48:23 AM PDT 24
Peak memory 201448 kb
Host smart-dfed8ad9-0e60-4f1b-9055-f009fae31c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645840458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.1645840458
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.684195678
Short name T63
Test name
Test status
Simulation time 22531746559 ps
CPU time 58.26 seconds
Started Jul 01 10:48:05 AM PDT 24
Finished Jul 01 10:49:05 AM PDT 24
Peak memory 218164 kb
Host smart-d2ff0191-97d1-4db2-9899-f3c65ffde463
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684195678 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.684195678
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.631743167
Short name T59
Test name
Test status
Simulation time 4707263181 ps
CPU time 3.96 seconds
Started Jul 01 10:48:02 AM PDT 24
Finished Jul 01 10:48:07 AM PDT 24
Peak memory 201484 kb
Host smart-cb0f56b8-756a-431f-82cd-42e1b490095a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631743167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_ultra_low_pwr.631743167
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.3546575927
Short name T136
Test name
Test status
Simulation time 2011134033 ps
CPU time 5.58 seconds
Started Jul 01 10:48:35 AM PDT 24
Finished Jul 01 10:48:41 AM PDT 24
Peak memory 201524 kb
Host smart-edafcaea-8b02-4412-9c41-811176c32af7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546575927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.3546575927
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2318137577
Short name T203
Test name
Test status
Simulation time 3412975322 ps
CPU time 1.57 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:48:44 AM PDT 24
Peak memory 201520 kb
Host smart-0c91798d-25d0-4209-a493-8a8e72806b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318137577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
318137577
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.202088468
Short name T164
Test name
Test status
Simulation time 168421452646 ps
CPU time 81.87 seconds
Started Jul 01 10:48:59 AM PDT 24
Finished Jul 01 10:50:21 AM PDT 24
Peak memory 201732 kb
Host smart-c92ea147-3d61-4474-8a5f-760f93dd752f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202088468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_combo_detect.202088468
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3151313830
Short name T365
Test name
Test status
Simulation time 123726066376 ps
CPU time 164.91 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:51:39 AM PDT 24
Peak memory 201804 kb
Host smart-a6df6c91-c434-4458-9368-29b9a42f4bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151313830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.3151313830
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3357283260
Short name T666
Test name
Test status
Simulation time 3249039447 ps
CPU time 2.91 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:48:59 AM PDT 24
Peak memory 201492 kb
Host smart-d6116dc7-e5c8-45c9-9a30-f114932a10c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357283260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.3357283260
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2868323541
Short name T175
Test name
Test status
Simulation time 4553832234 ps
CPU time 3.7 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 201508 kb
Host smart-7f2e545b-5b0f-40d4-92b3-f9feb8e1e397
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868323541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.2868323541
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1556376407
Short name T387
Test name
Test status
Simulation time 2622502049 ps
CPU time 4.1 seconds
Started Jul 01 10:49:03 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 201500 kb
Host smart-9dcac147-b659-4011-9c52-48e6992e91b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556376407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1556376407
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1265168400
Short name T539
Test name
Test status
Simulation time 2471979286 ps
CPU time 3.99 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:48:47 AM PDT 24
Peak memory 201468 kb
Host smart-a638f6d8-1457-46c5-b095-54c7adaf81d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265168400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1265168400
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.856643004
Short name T405
Test name
Test status
Simulation time 2253171623 ps
CPU time 3.61 seconds
Started Jul 01 10:48:39 AM PDT 24
Finished Jul 01 10:48:43 AM PDT 24
Peak memory 201476 kb
Host smart-af43734a-6bbc-4ae1-a808-8d8d66986716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856643004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.856643004
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3602130674
Short name T689
Test name
Test status
Simulation time 2520790929 ps
CPU time 2.43 seconds
Started Jul 01 10:49:10 AM PDT 24
Finished Jul 01 10:49:13 AM PDT 24
Peak memory 201524 kb
Host smart-46b595ba-89ad-428f-90ca-63cb74bcf413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602130674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3602130674
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.3404389905
Short name T537
Test name
Test status
Simulation time 2117017071 ps
CPU time 3.34 seconds
Started Jul 01 10:48:39 AM PDT 24
Finished Jul 01 10:48:43 AM PDT 24
Peak memory 201412 kb
Host smart-76ff5083-a034-4a83-ad3b-d653e44cebe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404389905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.3404389905
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2578365140
Short name T82
Test name
Test status
Simulation time 1485305662746 ps
CPU time 110.81 seconds
Started Jul 01 10:48:38 AM PDT 24
Finished Jul 01 10:50:29 AM PDT 24
Peak memory 201520 kb
Host smart-14f16870-69af-4c99-b6f1-b90699c97830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578365140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2578365140
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1781852291
Short name T139
Test name
Test status
Simulation time 29840891160 ps
CPU time 17.21 seconds
Started Jul 01 10:48:38 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 210160 kb
Host smart-3878d3ce-d115-49ef-b93e-f34e510cbb62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781852291 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1781852291
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.395648899
Short name T190
Test name
Test status
Simulation time 5489385720 ps
CPU time 2.73 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:49:00 AM PDT 24
Peak memory 201488 kb
Host smart-f88cac6e-a23b-4b09-b617-f4a844a7aa96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395648899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ultra_low_pwr.395648899
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.1159987514
Short name T548
Test name
Test status
Simulation time 2016599334 ps
CPU time 3.2 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 201444 kb
Host smart-0afda704-eeb9-406d-9b66-08e84d259356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159987514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.1159987514
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3579105957
Short name T457
Test name
Test status
Simulation time 3421976661 ps
CPU time 3.07 seconds
Started Jul 01 10:48:40 AM PDT 24
Finished Jul 01 10:48:43 AM PDT 24
Peak memory 201564 kb
Host smart-59b04080-53e8-4f8c-9310-1ba96d85911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579105957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
579105957
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3288268144
Short name T257
Test name
Test status
Simulation time 186734216185 ps
CPU time 40.28 seconds
Started Jul 01 10:49:03 AM PDT 24
Finished Jul 01 10:49:44 AM PDT 24
Peak memory 201676 kb
Host smart-b68149ef-baf3-4b21-b6bf-53422e5531c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288268144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.3288268144
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3393273706
Short name T661
Test name
Test status
Simulation time 54219775909 ps
CPU time 49.69 seconds
Started Jul 01 10:49:07 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 201716 kb
Host smart-f6dfeb26-fba2-4800-a6ca-d52a159b1a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393273706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.3393273706
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3266104792
Short name T459
Test name
Test status
Simulation time 4926803969 ps
CPU time 3.51 seconds
Started Jul 01 10:48:38 AM PDT 24
Finished Jul 01 10:48:42 AM PDT 24
Peak memory 201508 kb
Host smart-a82545f2-1267-4ca4-8363-cebfc2de8803
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266104792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.3266104792
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.272899677
Short name T160
Test name
Test status
Simulation time 656299065206 ps
CPU time 1758.17 seconds
Started Jul 01 10:48:40 AM PDT 24
Finished Jul 01 11:17:59 AM PDT 24
Peak memory 201524 kb
Host smart-9e5d047b-e04e-4a59-9619-e9bcd0cade19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272899677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctr
l_edge_detect.272899677
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2203600160
Short name T628
Test name
Test status
Simulation time 2614193450 ps
CPU time 4.24 seconds
Started Jul 01 10:49:03 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 201372 kb
Host smart-704a6e80-5246-4e44-aa55-50f7477f6e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203600160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2203600160
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1094144102
Short name T182
Test name
Test status
Simulation time 2549192434 ps
CPU time 1.26 seconds
Started Jul 01 10:48:54 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 201516 kb
Host smart-adccbac1-3242-4d4e-bd10-48a0edaf69b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094144102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1094144102
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.318672946
Short name T767
Test name
Test status
Simulation time 2105984786 ps
CPU time 0.96 seconds
Started Jul 01 10:48:39 AM PDT 24
Finished Jul 01 10:48:41 AM PDT 24
Peak memory 201448 kb
Host smart-bb2f6615-04f7-49a8-b919-9e3c1ceb0326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318672946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.318672946
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.3586039206
Short name T664
Test name
Test status
Simulation time 2511741029 ps
CPU time 7.45 seconds
Started Jul 01 10:48:37 AM PDT 24
Finished Jul 01 10:48:45 AM PDT 24
Peak memory 201544 kb
Host smart-7f4826cd-bd86-4e81-8fd2-5ca112bbddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586039206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.3586039206
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.450172495
Short name T607
Test name
Test status
Simulation time 2111774867 ps
CPU time 6.29 seconds
Started Jul 01 10:49:04 AM PDT 24
Finished Jul 01 10:49:11 AM PDT 24
Peak memory 201440 kb
Host smart-61c073d1-cbfe-43b3-8232-b1a77cc73c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450172495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.450172495
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.3197395418
Short name T105
Test name
Test status
Simulation time 15589111691 ps
CPU time 9.39 seconds
Started Jul 01 10:48:41 AM PDT 24
Finished Jul 01 10:48:51 AM PDT 24
Peak memory 201828 kb
Host smart-deff4f2a-5f06-4122-991a-dc0886dc7bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197395418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.3197395418
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3640859452
Short name T631
Test name
Test status
Simulation time 8146634784 ps
CPU time 3.81 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:20 AM PDT 24
Peak memory 201564 kb
Host smart-b21a1da2-2346-4610-ad46-54c678b66fb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640859452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.3640859452
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.1443645686
Short name T53
Test name
Test status
Simulation time 2037062403 ps
CPU time 2.15 seconds
Started Jul 01 10:49:09 AM PDT 24
Finished Jul 01 10:49:12 AM PDT 24
Peak memory 201340 kb
Host smart-0ba1dd0c-969b-49ab-a143-5e569d4c239c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443645686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.1443645686
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.646334189
Short name T780
Test name
Test status
Simulation time 3378366179 ps
CPU time 8.46 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201436 kb
Host smart-22dd6fd3-10e6-40b0-883c-d2fcefa3f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646334189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.646334189
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3156975073
Short name T574
Test name
Test status
Simulation time 27331246535 ps
CPU time 73.06 seconds
Started Jul 01 10:48:41 AM PDT 24
Finished Jul 01 10:49:55 AM PDT 24
Peak memory 201824 kb
Host smart-5c32c98b-342d-490f-8994-1c705084f2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156975073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.3156975073
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1022262138
Short name T540
Test name
Test status
Simulation time 4127779417 ps
CPU time 1.18 seconds
Started Jul 01 10:49:11 AM PDT 24
Finished Jul 01 10:49:12 AM PDT 24
Peak memory 201484 kb
Host smart-be10fb56-0f53-495b-8062-eee23777c310
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022262138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.1022262138
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.2147505475
Short name T153
Test name
Test status
Simulation time 5302736063 ps
CPU time 5.15 seconds
Started Jul 01 10:49:09 AM PDT 24
Finished Jul 01 10:49:16 AM PDT 24
Peak memory 201568 kb
Host smart-ef18cc58-4c8b-4c47-b550-0cc5cbfcbb95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147505475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.2147505475
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1782209545
Short name T115
Test name
Test status
Simulation time 2637001268 ps
CPU time 1.92 seconds
Started Jul 01 10:48:44 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 201472 kb
Host smart-a7f8e7d5-df25-491b-b78c-c2a6dcab7aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782209545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.1782209545
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.2698018595
Short name T699
Test name
Test status
Simulation time 2473557492 ps
CPU time 6.55 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201456 kb
Host smart-2252fb50-c549-4082-adfd-f41d86a64794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698018595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.2698018595
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.993649130
Short name T719
Test name
Test status
Simulation time 2108673569 ps
CPU time 3.21 seconds
Started Jul 01 10:48:48 AM PDT 24
Finished Jul 01 10:48:51 AM PDT 24
Peak memory 201448 kb
Host smart-5ca0c91e-3a89-4565-9e6e-7fa61c14a945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993649130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.993649130
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1752283945
Short name T598
Test name
Test status
Simulation time 2532208623 ps
CPU time 2.71 seconds
Started Jul 01 10:48:46 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201420 kb
Host smart-1ae67718-2146-4f6c-a9f5-e187df5e2bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752283945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.1752283945
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.1065686787
Short name T495
Test name
Test status
Simulation time 2119057355 ps
CPU time 3.42 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:17 AM PDT 24
Peak memory 201444 kb
Host smart-f86229bd-6d3b-4a5b-8d7e-49266c3759e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065686787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.1065686787
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.2380786355
Short name T130
Test name
Test status
Simulation time 13587225306 ps
CPU time 8.17 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201568 kb
Host smart-e3ca18fd-1133-4484-ade2-dcf98acab926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380786355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.2380786355
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3670925119
Short name T72
Test name
Test status
Simulation time 54758222121 ps
CPU time 36.94 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:52 AM PDT 24
Peak memory 218256 kb
Host smart-a29f2631-d85e-4696-9476-fb01d1afc14c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670925119 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3670925119
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1973742968
Short name T565
Test name
Test status
Simulation time 4048478485 ps
CPU time 1.93 seconds
Started Jul 01 10:48:41 AM PDT 24
Finished Jul 01 10:48:43 AM PDT 24
Peak memory 201452 kb
Host smart-0bd8d3e8-b911-4212-a72d-5154656ed439
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973742968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.1973742968
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.2209949687
Short name T731
Test name
Test status
Simulation time 2044966977 ps
CPU time 1.89 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 201652 kb
Host smart-e79ff1ef-feda-4c10-87b5-61dffb85dba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209949687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.2209949687
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2930647435
Short name T414
Test name
Test status
Simulation time 3200390572 ps
CPU time 9.18 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:26 AM PDT 24
Peak memory 201412 kb
Host smart-39dc3524-c68b-46f3-82c8-39214b135c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930647435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2
930647435
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.2920191351
Short name T573
Test name
Test status
Simulation time 17392463514 ps
CPU time 4.76 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 201660 kb
Host smart-465644a1-1ab0-4c1d-9b6f-e20bb063be25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920191351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.2920191351
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3300720060
Short name T357
Test name
Test status
Simulation time 64046220736 ps
CPU time 92.36 seconds
Started Jul 01 10:48:47 AM PDT 24
Finished Jul 01 10:50:20 AM PDT 24
Peak memory 201784 kb
Host smart-892f41a6-acd2-4965-bbf7-f17ca9957b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300720060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.3300720060
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.4072497805
Short name T497
Test name
Test status
Simulation time 3557447217 ps
CPU time 1.75 seconds
Started Jul 01 10:48:44 AM PDT 24
Finished Jul 01 10:48:46 AM PDT 24
Peak memory 201436 kb
Host smart-f8dd3c21-ad70-4ed9-83c9-037e325c086d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072497805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.4072497805
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2583889803
Short name T775
Test name
Test status
Simulation time 2632605614 ps
CPU time 2.57 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:48:45 AM PDT 24
Peak memory 201472 kb
Host smart-81066dfc-73e2-43f4-81e8-9a586f7c2eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583889803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.2583889803
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1918322903
Short name T308
Test name
Test status
Simulation time 2460378948 ps
CPU time 6.98 seconds
Started Jul 01 10:48:41 AM PDT 24
Finished Jul 01 10:48:48 AM PDT 24
Peak memory 201472 kb
Host smart-3c001edc-3db5-4938-ab6c-1271bbdc8b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918322903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1918322903
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.923789431
Short name T788
Test name
Test status
Simulation time 2108587217 ps
CPU time 6.46 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 201364 kb
Host smart-fd40946b-f4f3-4276-bb8f-9cdea4394229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923789431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.923789431
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1620708210
Short name T179
Test name
Test status
Simulation time 2529555181 ps
CPU time 2.11 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:17 AM PDT 24
Peak memory 201452 kb
Host smart-a3d43375-52b0-4f04-a817-c59166c45e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620708210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1620708210
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.3825996808
Short name T479
Test name
Test status
Simulation time 2111211219 ps
CPU time 5.91 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201348 kb
Host smart-87d8aae5-4c1b-4003-a596-aafa647d4afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825996808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.3825996808
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.3804313991
Short name T206
Test name
Test status
Simulation time 260474772456 ps
CPU time 635.79 seconds
Started Jul 01 10:48:46 AM PDT 24
Finished Jul 01 10:59:23 AM PDT 24
Peak memory 201504 kb
Host smart-e7b8d154-1891-42aa-adb3-8e06d5b6892d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804313991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.3804313991
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.79474478
Short name T538
Test name
Test status
Simulation time 83256572529 ps
CPU time 96.9 seconds
Started Jul 01 10:49:20 AM PDT 24
Finished Jul 01 10:50:58 AM PDT 24
Peak memory 202068 kb
Host smart-735425d8-dba3-4014-aa00-d3ad254c9870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79474478 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.79474478
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1529080556
Short name T653
Test name
Test status
Simulation time 5762450051 ps
CPU time 3.33 seconds
Started Jul 01 10:48:45 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201352 kb
Host smart-6e077b18-51d2-42ef-9b70-57983be8b706
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529080556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.1529080556
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.1598788711
Short name T226
Test name
Test status
Simulation time 2035563143 ps
CPU time 1.89 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:17 AM PDT 24
Peak memory 201512 kb
Host smart-a69bfb48-6634-4a6c-bd8c-da779c58136f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598788711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.1598788711
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1852219827
Short name T407
Test name
Test status
Simulation time 3228849342 ps
CPU time 8.89 seconds
Started Jul 01 10:48:45 AM PDT 24
Finished Jul 01 10:48:54 AM PDT 24
Peak memory 201228 kb
Host smart-96b60bd5-3938-41b4-a84e-004837e217e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852219827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.1
852219827
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.4101822025
Short name T267
Test name
Test status
Simulation time 116539932592 ps
CPU time 188.75 seconds
Started Jul 01 10:48:45 AM PDT 24
Finished Jul 01 10:51:54 AM PDT 24
Peak memory 201476 kb
Host smart-fc2b5527-2231-4301-afc9-e975f3f76b67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101822025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.4101822025
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.3730232971
Short name T413
Test name
Test status
Simulation time 3961745449 ps
CPU time 3.06 seconds
Started Jul 01 10:49:10 AM PDT 24
Finished Jul 01 10:49:14 AM PDT 24
Peak memory 201508 kb
Host smart-2c86f83d-67e9-4b11-b784-7bc00f2b6bf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730232971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.3730232971
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2244261209
Short name T209
Test name
Test status
Simulation time 3419481797 ps
CPU time 1.34 seconds
Started Jul 01 10:48:47 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201368 kb
Host smart-3da71519-3018-40b0-8e02-a42fad706f22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244261209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.2244261209
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2439066085
Short name T303
Test name
Test status
Simulation time 2613300973 ps
CPU time 7.45 seconds
Started Jul 01 10:48:45 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201356 kb
Host smart-d7ddeaaa-d3c8-47a3-955a-6c376a14e03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439066085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.2439066085
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1043495857
Short name T444
Test name
Test status
Simulation time 2525667569 ps
CPU time 1.29 seconds
Started Jul 01 10:48:47 AM PDT 24
Finished Jul 01 10:48:49 AM PDT 24
Peak memory 201472 kb
Host smart-93a1079f-9c57-4f06-be11-447d1587b961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043495857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1043495857
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.3203781442
Short name T677
Test name
Test status
Simulation time 2120981280 ps
CPU time 1.88 seconds
Started Jul 01 10:48:42 AM PDT 24
Finished Jul 01 10:48:45 AM PDT 24
Peak memory 201428 kb
Host smart-19dfb87d-8c8e-4997-bbd3-0b1b8f121f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203781442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.3203781442
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.4239140735
Short name T644
Test name
Test status
Simulation time 2512528421 ps
CPU time 4.12 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:17 AM PDT 24
Peak memory 201512 kb
Host smart-4b0fa815-2380-4c49-9e70-aff203659915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239140735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.4239140735
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.3512252843
Short name T624
Test name
Test status
Simulation time 2113923673 ps
CPU time 6.03 seconds
Started Jul 01 10:49:11 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 201428 kb
Host smart-4711c85c-5b3a-4551-845a-a0541a0c4223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512252843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3512252843
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.3239516320
Short name T152
Test name
Test status
Simulation time 9032395092 ps
CPU time 2.52 seconds
Started Jul 01 10:48:47 AM PDT 24
Finished Jul 01 10:48:50 AM PDT 24
Peak memory 201544 kb
Host smart-e4e07fa7-2120-4ce9-bb8e-48ed98a19f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239516320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.3239516320
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2985624180
Short name T427
Test name
Test status
Simulation time 5711267789 ps
CPU time 3.77 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 201572 kb
Host smart-abaf888f-b58b-4896-bbfd-e66b4d4c37a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985624180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2985624180
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.316969873
Short name T746
Test name
Test status
Simulation time 2114501751 ps
CPU time 0.94 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:20 AM PDT 24
Peak memory 201488 kb
Host smart-81a80a90-9335-4853-a56f-395b8a179abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316969873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_tes
t.316969873
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2610460904
Short name T650
Test name
Test status
Simulation time 128588004448 ps
CPU time 290.23 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:53:43 AM PDT 24
Peak memory 201632 kb
Host smart-b0966d67-99fd-483c-ae70-071d1bae53a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610460904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2
610460904
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.4125817879
Short name T333
Test name
Test status
Simulation time 164403702238 ps
CPU time 438.33 seconds
Started Jul 01 10:48:48 AM PDT 24
Finished Jul 01 10:56:07 AM PDT 24
Peak memory 201828 kb
Host smart-f34e4931-afeb-4cf6-840e-795818483b1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125817879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.4125817879
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1887539206
Short name T492
Test name
Test status
Simulation time 238739073692 ps
CPU time 533.7 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:58:07 AM PDT 24
Peak memory 201820 kb
Host smart-6ab94240-fcc1-4081-b38e-6699a540f128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887539206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.1887539206
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1686327301
Short name T517
Test name
Test status
Simulation time 5577073094 ps
CPU time 7.84 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:23 AM PDT 24
Peak memory 201536 kb
Host smart-cae2fd45-9141-4fcb-ad5f-9cea6028ce0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686327301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.1686327301
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.2204173680
Short name T84
Test name
Test status
Simulation time 3716378820 ps
CPU time 2.47 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:17 AM PDT 24
Peak memory 201456 kb
Host smart-7f356a46-941a-470f-aea5-0363434562e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204173680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.2204173680
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.484944769
Short name T4
Test name
Test status
Simulation time 2645877084 ps
CPU time 1.52 seconds
Started Jul 01 10:48:45 AM PDT 24
Finished Jul 01 10:48:47 AM PDT 24
Peak memory 201484 kb
Host smart-068417b6-682f-453d-af98-6e7ced382d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484944769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.484944769
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1712725638
Short name T476
Test name
Test status
Simulation time 2502979734 ps
CPU time 1.53 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:16 AM PDT 24
Peak memory 201512 kb
Host smart-28ae7f4b-f9bd-4013-a435-dca4924bd95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712725638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1712725638
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.798575315
Short name T519
Test name
Test status
Simulation time 2254320648 ps
CPU time 2.11 seconds
Started Jul 01 10:49:10 AM PDT 24
Finished Jul 01 10:49:13 AM PDT 24
Peak memory 201508 kb
Host smart-45ad04c4-ef68-4ae6-9116-f0565ef69b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798575315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.798575315
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.4266051173
Short name T213
Test name
Test status
Simulation time 2538899915 ps
CPU time 2.27 seconds
Started Jul 01 10:49:04 AM PDT 24
Finished Jul 01 10:49:07 AM PDT 24
Peak memory 201448 kb
Host smart-98bce73c-c2a5-4c2f-854f-1c22d2187db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266051173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.4266051173
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.929595727
Short name T201
Test name
Test status
Simulation time 2117325152 ps
CPU time 3.81 seconds
Started Jul 01 10:48:48 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201424 kb
Host smart-d8dac3a6-ffcd-478a-958b-6cd19278be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929595727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.929595727
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.4218732984
Short name T728
Test name
Test status
Simulation time 16594221737 ps
CPU time 18.46 seconds
Started Jul 01 10:48:48 AM PDT 24
Finished Jul 01 10:49:07 AM PDT 24
Peak memory 201624 kb
Host smart-4e66734e-ab56-4354-8be6-1597bdcaeccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218732984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.4218732984
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3222076543
Short name T306
Test name
Test status
Simulation time 27118771130 ps
CPU time 13.72 seconds
Started Jul 01 10:49:09 AM PDT 24
Finished Jul 01 10:49:24 AM PDT 24
Peak memory 210104 kb
Host smart-5c41d45a-dc6f-400f-a4a7-353cbc9a2563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222076543 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.3222076543
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.1060404255
Short name T726
Test name
Test status
Simulation time 7526882919 ps
CPU time 2.5 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201544 kb
Host smart-bf2ea99f-91a9-4938-a677-d55c551a3703
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060404255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.1060404255
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.3944334491
Short name T707
Test name
Test status
Simulation time 2009127916 ps
CPU time 5.93 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:49:00 AM PDT 24
Peak memory 201716 kb
Host smart-db6b3875-f461-446e-8a76-802f2f918843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944334491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.3944334491
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2984233699
Short name T618
Test name
Test status
Simulation time 3916418139 ps
CPU time 3.23 seconds
Started Jul 01 10:49:23 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 201592 kb
Host smart-a493d5f9-b533-4862-bb49-72bb92341869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984233699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.2
984233699
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.3123280475
Short name T95
Test name
Test status
Simulation time 105237111633 ps
CPU time 259.25 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:53:35 AM PDT 24
Peak memory 201660 kb
Host smart-cbf587d3-164a-4ff5-a0f6-9dd27c58b545
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123280475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.3123280475
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2277470469
Short name T364
Test name
Test status
Simulation time 106123718230 ps
CPU time 274.38 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:53:51 AM PDT 24
Peak memory 201632 kb
Host smart-d98f8bd3-a043-49d6-9911-5bf998879ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277470469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.2277470469
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2505301066
Short name T239
Test name
Test status
Simulation time 3763423370 ps
CPU time 2.59 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 201396 kb
Host smart-d9e52ba3-ef3b-4618-9621-38a896e768b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505301066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.2505301066
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3910110456
Short name T196
Test name
Test status
Simulation time 3711186001 ps
CPU time 8.88 seconds
Started Jul 01 10:48:52 AM PDT 24
Finished Jul 01 10:49:01 AM PDT 24
Peak memory 201472 kb
Host smart-2bfcf0ba-0642-4a9b-a68d-604f268409e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910110456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.3910110456
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.738836588
Short name T218
Test name
Test status
Simulation time 2671127447 ps
CPU time 1.51 seconds
Started Jul 01 10:49:05 AM PDT 24
Finished Jul 01 10:49:07 AM PDT 24
Peak memory 201512 kb
Host smart-c6170092-ce49-4faf-9c9b-e2462943450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738836588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.738836588
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3899822025
Short name T672
Test name
Test status
Simulation time 2462333384 ps
CPU time 7.63 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:26 AM PDT 24
Peak memory 201432 kb
Host smart-3aaa8dc8-4933-43b6-a27b-c8846d055509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899822025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3899822025
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1469701516
Short name T656
Test name
Test status
Simulation time 2257197191 ps
CPU time 6.72 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:25 AM PDT 24
Peak memory 201508 kb
Host smart-2fe10feb-5773-42ba-b8ca-982f52ea2190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469701516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1469701516
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.176013346
Short name T117
Test name
Test status
Simulation time 2512705183 ps
CPU time 3.84 seconds
Started Jul 01 10:48:51 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 201480 kb
Host smart-3f9ab7bc-1e21-48c3-af9d-eabb39b03a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176013346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.176013346
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.2063212556
Short name T792
Test name
Test status
Simulation time 2114919802 ps
CPU time 3.33 seconds
Started Jul 01 10:48:49 AM PDT 24
Finished Jul 01 10:48:53 AM PDT 24
Peak memory 201436 kb
Host smart-5d613590-561e-45c7-a518-09415ff31432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063212556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.2063212556
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.1589673549
Short name T198
Test name
Test status
Simulation time 7306260264 ps
CPU time 18.6 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:36 AM PDT 24
Peak memory 201292 kb
Host smart-a298c7d4-24b4-46a7-9582-7d1d972a6967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589673549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.1589673549
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3084057261
Short name T194
Test name
Test status
Simulation time 49420234914 ps
CPU time 32.87 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 210092 kb
Host smart-9d11de32-5cbb-40c6-bbf3-f16e04d6fc4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084057261 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.3084057261
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3141236556
Short name T61
Test name
Test status
Simulation time 8313192389 ps
CPU time 4.21 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:24 AM PDT 24
Peak memory 201468 kb
Host smart-737b3a16-fa17-4eef-8bc2-8ea84cfd0d0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141236556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.3141236556
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1689693858
Short name T438
Test name
Test status
Simulation time 2014004527 ps
CPU time 5.58 seconds
Started Jul 01 10:48:52 AM PDT 24
Finished Jul 01 10:48:58 AM PDT 24
Peak memory 201500 kb
Host smart-f22f9636-1ff4-4e21-aeb7-ef2b59f2a5fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689693858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1689693858
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2232201352
Short name T114
Test name
Test status
Simulation time 3718889653 ps
CPU time 3.25 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:48:57 AM PDT 24
Peak memory 201632 kb
Host smart-c1ce4e53-92d5-4a1c-814a-7bf98665788b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232201352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
232201352
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.520912433
Short name T197
Test name
Test status
Simulation time 36582945166 ps
CPU time 15.03 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:34 AM PDT 24
Peak memory 201672 kb
Host smart-a366b11a-3907-4dc2-bff8-ac6c3e706c9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520912433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_combo_detect.520912433
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3119573248
Short name T97
Test name
Test status
Simulation time 59361742698 ps
CPU time 75.66 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:50:34 AM PDT 24
Peak memory 201580 kb
Host smart-533eff02-32eb-4632-8280-c0399da20171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119573248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.3119573248
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2068351865
Short name T652
Test name
Test status
Simulation time 48535484057 ps
CPU time 30.55 seconds
Started Jul 01 10:48:57 AM PDT 24
Finished Jul 01 10:49:28 AM PDT 24
Peak memory 201504 kb
Host smart-976fb82a-a2ea-425d-b213-e4570092d526
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068351865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2068351865
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3474729697
Short name T763
Test name
Test status
Simulation time 4027335725 ps
CPU time 3.7 seconds
Started Jul 01 10:49:00 AM PDT 24
Finished Jul 01 10:49:04 AM PDT 24
Peak memory 201440 kb
Host smart-507aae23-3f78-402f-9b9a-8701dc8b7688
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474729697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.3474729697
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2917511598
Short name T627
Test name
Test status
Simulation time 2621568529 ps
CPU time 4.01 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:23 AM PDT 24
Peak memory 201536 kb
Host smart-050d572c-aeac-43d9-9e93-7d8dff1a3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917511598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.2917511598
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.1975310424
Short name T587
Test name
Test status
Simulation time 2502659518 ps
CPU time 2.44 seconds
Started Jul 01 10:48:52 AM PDT 24
Finished Jul 01 10:48:55 AM PDT 24
Peak memory 201512 kb
Host smart-257cd58e-ce87-4e7e-bb9f-280a9e3509cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975310424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1975310424
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2296508423
Short name T451
Test name
Test status
Simulation time 2068162626 ps
CPU time 1.9 seconds
Started Jul 01 10:48:55 AM PDT 24
Finished Jul 01 10:48:57 AM PDT 24
Peak memory 201248 kb
Host smart-bd680984-b39e-46c8-aab9-3d453b56a4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296508423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.2296508423
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.4117123584
Short name T467
Test name
Test status
Simulation time 2521916058 ps
CPU time 2.32 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:20 AM PDT 24
Peak memory 201528 kb
Host smart-1a05fe51-1c4a-4dcf-a968-4945d1139bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117123584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.4117123584
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.639844596
Short name T51
Test name
Test status
Simulation time 2113764101 ps
CPU time 3.11 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:20 AM PDT 24
Peak memory 201280 kb
Host smart-309cba22-7052-4b07-98c6-7fda58b393bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639844596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.639844596
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.863881650
Short name T235
Test name
Test status
Simulation time 854297143966 ps
CPU time 1987.55 seconds
Started Jul 01 10:48:54 AM PDT 24
Finished Jul 01 11:22:02 AM PDT 24
Peak memory 201504 kb
Host smart-09185279-5011-43ff-aad6-8f815bb21af4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863881650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_st
ress_all.863881650
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.944185408
Short name T252
Test name
Test status
Simulation time 173059305980 ps
CPU time 99.46 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:50:54 AM PDT 24
Peak memory 210140 kb
Host smart-11be8a49-a917-42c9-b463-cac34b4b310c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944185408 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.944185408
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.249213459
Short name T687
Test name
Test status
Simulation time 5141251328 ps
CPU time 4.01 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201556 kb
Host smart-eaed6571-7a1a-4d72-bf5c-2977ab2989ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249213459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_ultra_low_pwr.249213459
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.2988659558
Short name T193
Test name
Test status
Simulation time 2009080448 ps
CPU time 5.67 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:49:26 AM PDT 24
Peak memory 201652 kb
Host smart-8373a1c5-ee67-4616-9c4b-86e78ff9320c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988659558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.2988659558
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1132258709
Short name T28
Test name
Test status
Simulation time 3885384663 ps
CPU time 1.12 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:48:55 AM PDT 24
Peak memory 201572 kb
Host smart-b175ab1e-adf7-47c6-bccc-4f84d516f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132258709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.1
132258709
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.3585294771
Short name T343
Test name
Test status
Simulation time 161806119146 ps
CPU time 316.71 seconds
Started Jul 01 10:48:54 AM PDT 24
Finished Jul 01 10:54:11 AM PDT 24
Peak memory 201812 kb
Host smart-86e46c29-f14a-4146-b771-7bbeaaa666a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585294771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.3585294771
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3204220951
Short name T502
Test name
Test status
Simulation time 29086680756 ps
CPU time 36.84 seconds
Started Jul 01 10:48:58 AM PDT 24
Finished Jul 01 10:49:35 AM PDT 24
Peak memory 201776 kb
Host smart-dc471cd2-700b-4ae6-983e-41f0c427c455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204220951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.3204220951
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.764864580
Short name T445
Test name
Test status
Simulation time 4197259884 ps
CPU time 3.36 seconds
Started Jul 01 10:48:57 AM PDT 24
Finished Jul 01 10:49:01 AM PDT 24
Peak memory 201484 kb
Host smart-4b2d93bf-f24e-48c7-932d-5d9a09636203
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764864580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.764864580
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2913373893
Short name T657
Test name
Test status
Simulation time 3345859464 ps
CPU time 1.89 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:48:55 AM PDT 24
Peak memory 201532 kb
Host smart-77ae2249-55c8-42af-b240-b3f00b8955ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913373893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.2913373893
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1847769329
Short name T633
Test name
Test status
Simulation time 2621266370 ps
CPU time 3.89 seconds
Started Jul 01 10:48:51 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 201520 kb
Host smart-b3b65d92-1404-4455-bf07-27081cbead8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847769329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1847769329
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.2514015286
Short name T613
Test name
Test status
Simulation time 2464804798 ps
CPU time 7.05 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201532 kb
Host smart-daab3f5b-d477-4a72-8a99-317bac2570fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514015286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.2514015286
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.4276801192
Short name T530
Test name
Test status
Simulation time 2200760865 ps
CPU time 2.14 seconds
Started Jul 01 10:48:53 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 201476 kb
Host smart-7d96f719-b115-4efc-96ba-6047bae9b8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276801192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.4276801192
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1668967687
Short name T141
Test name
Test status
Simulation time 2520015737 ps
CPU time 3.02 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201536 kb
Host smart-517ecd83-61ac-464e-92e2-b6589c6a3185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668967687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1668967687
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.2022045446
Short name T415
Test name
Test status
Simulation time 2133170397 ps
CPU time 1.92 seconds
Started Jul 01 10:48:55 AM PDT 24
Finished Jul 01 10:48:58 AM PDT 24
Peak memory 201388 kb
Host smart-c689ae5c-8dd2-4058-8219-bcc0b7deb652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022045446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2022045446
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.2161948711
Short name T683
Test name
Test status
Simulation time 12773754400 ps
CPU time 31.89 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 201476 kb
Host smart-269a0083-19ed-40d8-8b02-4d8970bfb51f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161948711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.2161948711
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3230529793
Short name T651
Test name
Test status
Simulation time 33347359230 ps
CPU time 14.85 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:33 AM PDT 24
Peak memory 201992 kb
Host smart-5d7e3959-6d31-48ec-bd29-8c67ae377345
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230529793 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3230529793
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.766762325
Short name T487
Test name
Test status
Simulation time 3925312647 ps
CPU time 2.24 seconds
Started Jul 01 10:48:54 AM PDT 24
Finished Jul 01 10:48:57 AM PDT 24
Peak memory 201452 kb
Host smart-f3af7c44-8e04-4ade-bca3-5de994f0a551
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766762325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ultra_low_pwr.766762325
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.2516076189
Short name T386
Test name
Test status
Simulation time 2021122191 ps
CPU time 3.1 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:49:23 AM PDT 24
Peak memory 201424 kb
Host smart-34d8e077-aa9a-4a10-ac26-17a9f261f710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516076189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.2516076189
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.153052382
Short name T92
Test name
Test status
Simulation time 3317830826 ps
CPU time 2.63 seconds
Started Jul 01 10:49:37 AM PDT 24
Finished Jul 01 10:49:41 AM PDT 24
Peak memory 201492 kb
Host smart-a8dc8287-b9e0-4eb5-8fd6-7b202e5aff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153052382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.153052382
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1988573001
Short name T43
Test name
Test status
Simulation time 156905493807 ps
CPU time 215.07 seconds
Started Jul 01 10:48:55 AM PDT 24
Finished Jul 01 10:52:31 AM PDT 24
Peak memory 201824 kb
Host smart-50996215-b4de-427f-844e-7e4271d275bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988573001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1988573001
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3186445941
Short name T638
Test name
Test status
Simulation time 54019851800 ps
CPU time 69.91 seconds
Started Jul 01 10:48:57 AM PDT 24
Finished Jul 01 10:50:07 AM PDT 24
Peak memory 201756 kb
Host smart-29cfa000-5db2-4a45-8a48-02bc1c17f7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186445941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.3186445941
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1165905372
Short name T611
Test name
Test status
Simulation time 3361412242 ps
CPU time 2.55 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 201484 kb
Host smart-ea047df2-26f4-4571-9c8d-729cebd36e2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165905372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.1165905372
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.672151352
Short name T210
Test name
Test status
Simulation time 2624755912 ps
CPU time 4.09 seconds
Started Jul 01 10:48:59 AM PDT 24
Finished Jul 01 10:49:04 AM PDT 24
Peak memory 201488 kb
Host smart-136c0033-d58d-4902-84e2-9e829c60f877
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672151352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.672151352
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.681795040
Short name T636
Test name
Test status
Simulation time 2628828706 ps
CPU time 2.16 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:17 AM PDT 24
Peak memory 201432 kb
Host smart-bd5eca96-a882-4345-9829-08807392f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681795040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.681795040
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.4237810088
Short name T629
Test name
Test status
Simulation time 2471829865 ps
CPU time 4.08 seconds
Started Jul 01 10:48:58 AM PDT 24
Finished Jul 01 10:49:03 AM PDT 24
Peak memory 201360 kb
Host smart-516c6b34-f491-47a7-aebe-ce23da6ab6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237810088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.4237810088
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2370680451
Short name T391
Test name
Test status
Simulation time 2136385798 ps
CPU time 6.37 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:25 AM PDT 24
Peak memory 201288 kb
Host smart-b08f551c-8755-4153-ac2b-6908cbd7db92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370680451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2370680451
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1390126045
Short name T410
Test name
Test status
Simulation time 2516108021 ps
CPU time 3.95 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:24 AM PDT 24
Peak memory 201392 kb
Host smart-9b24bbbe-3843-437f-9ad0-d16edd6eae28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390126045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1390126045
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.3443524970
Short name T151
Test name
Test status
Simulation time 2109237633 ps
CPU time 5.76 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:49:02 AM PDT 24
Peak memory 201400 kb
Host smart-5ebc6a7b-81fe-41b2-b4a8-3931b90ab46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443524970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3443524970
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.2130736636
Short name T101
Test name
Test status
Simulation time 76254467626 ps
CPU time 95.65 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:50:53 AM PDT 24
Peak memory 201880 kb
Host smart-5f3b527b-96b8-4be1-8def-77e3e5155510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130736636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.2130736636
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2029518053
Short name T5
Test name
Test status
Simulation time 5270012335 ps
CPU time 1.79 seconds
Started Jul 01 10:49:00 AM PDT 24
Finished Jul 01 10:49:02 AM PDT 24
Peak memory 201552 kb
Host smart-826c3707-92a8-475e-be1a-71dba286283a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029518053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.2029518053
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.238397212
Short name T691
Test name
Test status
Simulation time 2017819094 ps
CPU time 3 seconds
Started Jul 01 10:47:40 AM PDT 24
Finished Jul 01 10:47:43 AM PDT 24
Peak memory 201516 kb
Host smart-8eea6539-a257-4b76-ab3f-9984a1a72833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238397212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test
.238397212
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1214232671
Short name T186
Test name
Test status
Simulation time 3425040833 ps
CPU time 2.93 seconds
Started Jul 01 10:47:40 AM PDT 24
Finished Jul 01 10:47:44 AM PDT 24
Peak memory 201612 kb
Host smart-edb7171b-38be-4eb7-a467-827d8fe43f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214232671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.1214232671
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.392445947
Short name T786
Test name
Test status
Simulation time 80751694226 ps
CPU time 48.1 seconds
Started Jul 01 10:47:40 AM PDT 24
Finished Jul 01 10:48:29 AM PDT 24
Peak memory 201732 kb
Host smart-f8e3e80d-3d04-4e9f-bf81-5b9f7cc984e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392445947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_combo_detect.392445947
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1818679572
Short name T166
Test name
Test status
Simulation time 2241370408 ps
CPU time 1.49 seconds
Started Jul 01 10:48:09 AM PDT 24
Finished Jul 01 10:48:12 AM PDT 24
Peak memory 201640 kb
Host smart-d1cfff6f-3b01-465d-91b7-b8240139d6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818679572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.1818679572
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2958190179
Short name T725
Test name
Test status
Simulation time 2350462367 ps
CPU time 1.84 seconds
Started Jul 01 10:47:59 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 201572 kb
Host smart-0759742d-180a-4480-9adc-0f5ec6224f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958190179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2958190179
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3531169859
Short name T99
Test name
Test status
Simulation time 80744127565 ps
CPU time 50.31 seconds
Started Jul 01 10:48:10 AM PDT 24
Finished Jul 01 10:49:01 AM PDT 24
Peak memory 201676 kb
Host smart-2ba3a64f-469b-4cbe-ad66-fdd7328da3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531169859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3531169859
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.2307491686
Short name T685
Test name
Test status
Simulation time 3318728840 ps
CPU time 2.52 seconds
Started Jul 01 10:47:41 AM PDT 24
Finished Jul 01 10:47:44 AM PDT 24
Peak memory 201472 kb
Host smart-9e0a3fc3-5272-4ccb-99c7-741ebf23ece2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307491686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.2307491686
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.3416490235
Short name T229
Test name
Test status
Simulation time 4438459681 ps
CPU time 1.17 seconds
Started Jul 01 10:47:52 AM PDT 24
Finished Jul 01 10:47:53 AM PDT 24
Peak memory 201592 kb
Host smart-4c9f16fd-4990-4728-ab20-33424a4a1905
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416490235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.3416490235
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3564562166
Short name T660
Test name
Test status
Simulation time 2614926449 ps
CPU time 4.13 seconds
Started Jul 01 10:47:51 AM PDT 24
Finished Jul 01 10:47:55 AM PDT 24
Peak memory 201484 kb
Host smart-5c43de07-7f4a-4147-bffb-018736ed9d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564562166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3564562166
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3369604286
Short name T307
Test name
Test status
Simulation time 2508788501 ps
CPU time 1.39 seconds
Started Jul 01 10:47:46 AM PDT 24
Finished Jul 01 10:47:48 AM PDT 24
Peak memory 201484 kb
Host smart-601e0f5e-8a4e-4561-a484-16050d82c689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369604286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.3369604286
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3642889911
Short name T401
Test name
Test status
Simulation time 2032563950 ps
CPU time 2.39 seconds
Started Jul 01 10:48:04 AM PDT 24
Finished Jul 01 10:48:07 AM PDT 24
Peak memory 201476 kb
Host smart-6f9e5fac-9a91-453f-9e1a-18b6a86eada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642889911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3642889911
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3865158569
Short name T529
Test name
Test status
Simulation time 2511668875 ps
CPU time 6.69 seconds
Started Jul 01 10:47:41 AM PDT 24
Finished Jul 01 10:47:48 AM PDT 24
Peak memory 201504 kb
Host smart-0e73b1d1-f217-4b97-9e95-58f08579f3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865158569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3865158569
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1412884083
Short name T270
Test name
Test status
Simulation time 42011932781 ps
CPU time 101.34 seconds
Started Jul 01 10:47:45 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 222400 kb
Host smart-d5da813c-d667-45f7-8c26-ea99f2c68810
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412884083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1412884083
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.3121306298
Short name T199
Test name
Test status
Simulation time 2108829043 ps
CPU time 5.13 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:07 AM PDT 24
Peak memory 201316 kb
Host smart-1229b4ea-5d56-44f1-8b1c-010a31058441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121306298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3121306298
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.590713993
Short name T447
Test name
Test status
Simulation time 21314009822 ps
CPU time 58.19 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:48:56 AM PDT 24
Peak memory 201924 kb
Host smart-ea126720-21d0-4b9a-b708-4222389891e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590713993 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.590713993
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.3694128504
Short name T484
Test name
Test status
Simulation time 2029191694 ps
CPU time 1.93 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201496 kb
Host smart-9e2264a0-8216-4836-9b88-385230f6c69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694128504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.3694128504
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4218477146
Short name T727
Test name
Test status
Simulation time 3538536541 ps
CPU time 2.91 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 201512 kb
Host smart-ef3a356b-c9b4-4ef6-8a94-71374dcf8e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218477146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.4
218477146
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.1806546466
Short name T371
Test name
Test status
Simulation time 158030379718 ps
CPU time 197.95 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:52:37 AM PDT 24
Peak memory 201848 kb
Host smart-7f53b978-b36d-41da-8e87-a7d286d61eda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806546466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.1806546466
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1034658540
Short name T615
Test name
Test status
Simulation time 64864944141 ps
CPU time 41.55 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:50:01 AM PDT 24
Peak memory 201720 kb
Host smart-24e3af59-2fd6-46e5-a6cd-9d0d0d5ad857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034658540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.1034658540
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2862635789
Short name T455
Test name
Test status
Simulation time 3130390916 ps
CPU time 2.55 seconds
Started Jul 01 10:48:57 AM PDT 24
Finished Jul 01 10:49:00 AM PDT 24
Peak memory 201548 kb
Host smart-fa5a300c-3ece-448c-a87d-54b046962c74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862635789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.2862635789
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3158083989
Short name T605
Test name
Test status
Simulation time 2626474698 ps
CPU time 6.91 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:25 AM PDT 24
Peak memory 201532 kb
Host smart-e4cd54eb-4439-49e6-9b62-20d2b2086b45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158083989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.3158083989
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1637197610
Short name T564
Test name
Test status
Simulation time 2608781392 ps
CPU time 7.14 seconds
Started Jul 01 10:49:00 AM PDT 24
Finished Jul 01 10:49:07 AM PDT 24
Peak memory 201516 kb
Host smart-6eff277a-d78b-4eb0-9d06-4ed1d18b1f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637197610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1637197610
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2071197761
Short name T474
Test name
Test status
Simulation time 2463561603 ps
CPU time 2.33 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 201504 kb
Host smart-704ccf53-9936-40d8-a67d-841aea315908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071197761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2071197761
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3419044617
Short name T304
Test name
Test status
Simulation time 2042551535 ps
CPU time 2.29 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201308 kb
Host smart-1b798bd5-6e7d-458a-8cd2-32a87e2be251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419044617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.3419044617
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1241597726
Short name T514
Test name
Test status
Simulation time 2511738662 ps
CPU time 7.38 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:49:04 AM PDT 24
Peak memory 201496 kb
Host smart-e41d1c93-32bb-4591-bdb8-15b1a0dc73a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241597726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.1241597726
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.2562097640
Short name T429
Test name
Test status
Simulation time 2116327130 ps
CPU time 3.27 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201428 kb
Host smart-9425a660-dfbe-43c1-bbd2-d8036918c568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562097640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.2562097640
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.2448497587
Short name T402
Test name
Test status
Simulation time 6667030062 ps
CPU time 5.42 seconds
Started Jul 01 10:49:09 AM PDT 24
Finished Jul 01 10:49:15 AM PDT 24
Peak memory 201468 kb
Host smart-678e1026-65b6-404f-89da-e6c2f4fdd6be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448497587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.2448497587
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.382994113
Short name T217
Test name
Test status
Simulation time 6058655637 ps
CPU time 4.69 seconds
Started Jul 01 10:49:20 AM PDT 24
Finished Jul 01 10:49:25 AM PDT 24
Peak memory 201704 kb
Host smart-bf64e9d4-0b54-45b5-a8c6-cc2a82592ef6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382994113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ultra_low_pwr.382994113
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.52447324
Short name T412
Test name
Test status
Simulation time 2013341235 ps
CPU time 5.77 seconds
Started Jul 01 10:49:02 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 201496 kb
Host smart-c4c6ceef-cad2-4166-bfeb-39f1091306c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52447324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test
.52447324
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2167216418
Short name T635
Test name
Test status
Simulation time 3008754749 ps
CPU time 2.64 seconds
Started Jul 01 10:48:58 AM PDT 24
Finished Jul 01 10:49:01 AM PDT 24
Peak memory 201544 kb
Host smart-70df3fb8-5b20-45f0-a8e1-dbfd388bf0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167216418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.2
167216418
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1769935267
Short name T585
Test name
Test status
Simulation time 167278611429 ps
CPU time 427.32 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:56:24 AM PDT 24
Peak memory 201784 kb
Host smart-4aafb87f-3f02-47e7-9f3a-ce1f1194926e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769935267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.1769935267
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.909472295
Short name T247
Test name
Test status
Simulation time 61581412851 ps
CPU time 42.24 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 201888 kb
Host smart-8a49f3df-f823-43df-9c08-475d490dc2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909472295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_wi
th_pre_cond.909472295
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2747486514
Short name T567
Test name
Test status
Simulation time 2852317838 ps
CPU time 7.68 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:49:28 AM PDT 24
Peak memory 201392 kb
Host smart-139b94c4-50bb-406e-9c44-9ca26319c883
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747486514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.2747486514
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.292096515
Short name T159
Test name
Test status
Simulation time 3425931867 ps
CPU time 6.56 seconds
Started Jul 01 10:49:23 AM PDT 24
Finished Jul 01 10:49:30 AM PDT 24
Peak memory 201344 kb
Host smart-030b8b85-2066-48d3-83f1-3e194afaa6d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292096515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctr
l_edge_detect.292096515
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1742868033
Short name T640
Test name
Test status
Simulation time 2608586952 ps
CPU time 7.91 seconds
Started Jul 01 10:48:57 AM PDT 24
Finished Jul 01 10:49:06 AM PDT 24
Peak memory 201504 kb
Host smart-6addce76-5ce9-4454-a6cd-a6b8152bed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742868033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1742868033
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2918408593
Short name T297
Test name
Test status
Simulation time 2486450585 ps
CPU time 4.5 seconds
Started Jul 01 10:48:59 AM PDT 24
Finished Jul 01 10:49:04 AM PDT 24
Peak memory 201476 kb
Host smart-5d206ad0-2b9e-48b0-805e-0e90de6ff4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918408593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2918408593
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1273284059
Short name T730
Test name
Test status
Simulation time 2202154681 ps
CPU time 1.37 seconds
Started Jul 01 10:48:56 AM PDT 24
Finished Jul 01 10:48:58 AM PDT 24
Peak memory 201532 kb
Host smart-521c5610-95eb-4afd-9d4e-4ccdcdfb3c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273284059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1273284059
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2621462048
Short name T54
Test name
Test status
Simulation time 2522778279 ps
CPU time 3.25 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 201508 kb
Host smart-5587d013-25d3-46db-91c5-06a948cdcbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621462048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2621462048
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.2712952600
Short name T782
Test name
Test status
Simulation time 2117310879 ps
CPU time 3.08 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201440 kb
Host smart-fe890e6e-67c7-4c02-91ca-2ccd0fd05f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712952600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.2712952600
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.247418272
Short name T493
Test name
Test status
Simulation time 7130030419 ps
CPU time 11.77 seconds
Started Jul 01 10:49:23 AM PDT 24
Finished Jul 01 10:49:36 AM PDT 24
Peak memory 201444 kb
Host smart-ffae5003-f19f-4589-8843-f96b89884fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247418272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.247418272
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1478802108
Short name T741
Test name
Test status
Simulation time 3013448412 ps
CPU time 6.85 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:24 AM PDT 24
Peak memory 201488 kb
Host smart-dff92bfc-34fb-4e97-aa59-02a6e4b030d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478802108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1478802108
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.3483175818
Short name T533
Test name
Test status
Simulation time 2037942449 ps
CPU time 1.93 seconds
Started Jul 01 10:49:05 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 201464 kb
Host smart-c2dba1e9-2638-4a65-b02b-773820cbe2c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483175818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.3483175818
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2189231094
Short name T494
Test name
Test status
Simulation time 4012457789 ps
CPU time 11.03 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:29 AM PDT 24
Peak memory 201568 kb
Host smart-ec69a1fd-7b2e-4760-a165-6a1494eb5303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189231094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.2
189231094
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1696079181
Short name T266
Test name
Test status
Simulation time 43322027087 ps
CPU time 29.18 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:47 AM PDT 24
Peak memory 201812 kb
Host smart-e69ecee4-5762-4188-be94-4424faea5826
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696079181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1696079181
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.931952643
Short name T676
Test name
Test status
Simulation time 3415401693 ps
CPU time 2.6 seconds
Started Jul 01 10:49:20 AM PDT 24
Finished Jul 01 10:49:24 AM PDT 24
Peak memory 201380 kb
Host smart-10cb7c45-5a78-4e98-8182-947c291d31c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931952643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.931952643
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3319398463
Short name T65
Test name
Test status
Simulation time 3188037690 ps
CPU time 2.1 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:20 AM PDT 24
Peak memory 201428 kb
Host smart-0afd19bc-e75b-4719-859c-037187f13597
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319398463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.3319398463
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3077711002
Short name T125
Test name
Test status
Simulation time 2635222858 ps
CPU time 2.42 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:11 AM PDT 24
Peak memory 201508 kb
Host smart-970b1707-327a-451c-80f6-75d0b54ecb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077711002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.3077711002
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3108046890
Short name T62
Test name
Test status
Simulation time 2469755703 ps
CPU time 1.69 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:49:49 AM PDT 24
Peak memory 201500 kb
Host smart-3313ab40-657d-4b8e-b22a-3601e8429959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108046890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.3108046890
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3041826868
Short name T253
Test name
Test status
Simulation time 2192075033 ps
CPU time 2.08 seconds
Started Jul 01 10:49:05 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 201472 kb
Host smart-efd93851-c2d2-44c8-ad51-1619f37c7c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041826868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3041826868
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.4260068355
Short name T143
Test name
Test status
Simulation time 2511142225 ps
CPU time 7.28 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:26 AM PDT 24
Peak memory 201452 kb
Host smart-1349b950-df12-470e-a8c4-717855cd243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260068355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.4260068355
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.439882930
Short name T612
Test name
Test status
Simulation time 2110920087 ps
CPU time 6.29 seconds
Started Jul 01 10:49:04 AM PDT 24
Finished Jul 01 10:49:11 AM PDT 24
Peak memory 201408 kb
Host smart-b913958b-37d1-4cc0-96f3-6c4ef5cec4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439882930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.439882930
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1787784204
Short name T781
Test name
Test status
Simulation time 9780034964 ps
CPU time 25.73 seconds
Started Jul 01 10:49:07 AM PDT 24
Finished Jul 01 10:49:34 AM PDT 24
Peak memory 201528 kb
Host smart-ee317a1a-354d-4e86-8c60-8360e5896905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787784204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1787784204
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1436869155
Short name T98
Test name
Test status
Simulation time 100923753151 ps
CPU time 56.11 seconds
Started Jul 01 10:49:03 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 218276 kb
Host smart-c86d8149-2c84-4525-b50b-0007d63950bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436869155 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.1436869155
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.3297685718
Short name T761
Test name
Test status
Simulation time 2135561160 ps
CPU time 0.98 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:14 AM PDT 24
Peak memory 201484 kb
Host smart-f7f4a431-52ff-49f6-9244-ca6727703e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297685718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.3297685718
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2729061468
Short name T301
Test name
Test status
Simulation time 3259897810 ps
CPU time 2.5 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 201556 kb
Host smart-914d6e14-ee58-427c-9375-0c6fe719019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729061468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2
729061468
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.2395035578
Short name T256
Test name
Test status
Simulation time 114790072672 ps
CPU time 289.22 seconds
Started Jul 01 10:49:38 AM PDT 24
Finished Jul 01 10:54:28 AM PDT 24
Peak memory 201772 kb
Host smart-d7f0819f-b730-40a1-ba3c-1bb27fc611cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395035578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.2395035578
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.211084280
Short name T663
Test name
Test status
Simulation time 27109206532 ps
CPU time 17.68 seconds
Started Jul 01 10:49:29 AM PDT 24
Finished Jul 01 10:49:53 AM PDT 24
Peak memory 201872 kb
Host smart-440a0878-20ae-4815-b190-515f74ea1eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211084280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.211084280
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3248232460
Short name T78
Test name
Test status
Simulation time 3904213195 ps
CPU time 2.62 seconds
Started Jul 01 10:49:05 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 201504 kb
Host smart-e8b65a9c-4bb5-4719-a655-d337971e2381
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248232460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.3248232460
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1384395473
Short name T460
Test name
Test status
Simulation time 2612527143 ps
CPU time 7.17 seconds
Started Jul 01 10:49:07 AM PDT 24
Finished Jul 01 10:49:15 AM PDT 24
Peak memory 201508 kb
Host smart-f4cd0738-3f07-46ae-8528-ea3e95886bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384395473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.1384395473
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.935724955
Short name T553
Test name
Test status
Simulation time 2457857019 ps
CPU time 6.37 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:15 AM PDT 24
Peak memory 201480 kb
Host smart-f557ad8a-e38b-44d8-aa10-40f637ed7b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935724955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.935724955
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2644677782
Short name T418
Test name
Test status
Simulation time 2116773488 ps
CPU time 6.06 seconds
Started Jul 01 10:49:07 AM PDT 24
Finished Jul 01 10:49:14 AM PDT 24
Peak memory 201424 kb
Host smart-ef21455a-f04a-48b9-844b-35801694ef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644677782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.2644677782
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3574561245
Short name T658
Test name
Test status
Simulation time 2513621663 ps
CPU time 4.67 seconds
Started Jul 01 10:49:07 AM PDT 24
Finished Jul 01 10:49:12 AM PDT 24
Peak memory 201496 kb
Host smart-4ce21e17-ce63-4d55-865c-cc2c83579911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574561245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3574561245
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.195214943
Short name T50
Test name
Test status
Simulation time 2129467119 ps
CPU time 1.89 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:18 AM PDT 24
Peak memory 201416 kb
Host smart-9c121c22-54ec-49da-84b7-fe18881c1855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195214943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.195214943
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.1136420415
Short name T453
Test name
Test status
Simulation time 11838023357 ps
CPU time 16.82 seconds
Started Jul 01 10:49:04 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201680 kb
Host smart-7e692f85-6b9e-4883-a0b6-a202ee1fc1cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136420415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.1136420415
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2085662504
Short name T232
Test name
Test status
Simulation time 32591049725 ps
CPU time 37.49 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:53 AM PDT 24
Peak memory 218352 kb
Host smart-0b38e6ac-cea3-4c7b-9657-170f2690d5c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085662504 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2085662504
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3972603786
Short name T58
Test name
Test status
Simulation time 8092975091 ps
CPU time 7.94 seconds
Started Jul 01 10:49:06 AM PDT 24
Finished Jul 01 10:49:14 AM PDT 24
Peak memory 201552 kb
Host smart-744803b5-9ef6-480b-8e11-89715c52554d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972603786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.3972603786
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2392503746
Short name T420
Test name
Test status
Simulation time 2038862931 ps
CPU time 1.8 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:11 AM PDT 24
Peak memory 201476 kb
Host smart-637c024e-308d-4cbf-a878-5574507726f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392503746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2392503746
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3005735300
Short name T118
Test name
Test status
Simulation time 3649371979 ps
CPU time 3.6 seconds
Started Jul 01 10:49:30 AM PDT 24
Finished Jul 01 10:49:34 AM PDT 24
Peak memory 201508 kb
Host smart-05ad5688-dc4d-425e-a910-5210e35811c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005735300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3
005735300
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1489913446
Short name T67
Test name
Test status
Simulation time 26587475843 ps
CPU time 49.19 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:58 AM PDT 24
Peak memory 201868 kb
Host smart-9d382105-22e6-47ef-8c8d-17e0e05c71b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489913446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.1489913446
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2183334396
Short name T477
Test name
Test status
Simulation time 3186312206 ps
CPU time 8.39 seconds
Started Jul 01 10:49:50 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 201632 kb
Host smart-54c7944f-e76a-4712-b1de-bf1e35cd56e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183334396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.2183334396
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2468632836
Short name T724
Test name
Test status
Simulation time 2707444736 ps
CPU time 1.97 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201532 kb
Host smart-7d2d8625-a896-400f-9c85-36dca31888c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468632836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.2468632836
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2898588985
Short name T238
Test name
Test status
Simulation time 2618635898 ps
CPU time 3.94 seconds
Started Jul 01 10:49:04 AM PDT 24
Finished Jul 01 10:49:09 AM PDT 24
Peak memory 201520 kb
Host smart-60599172-88ae-40b7-975b-bfd69531ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898588985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2898588985
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1843809566
Short name T426
Test name
Test status
Simulation time 2455628890 ps
CPU time 7.23 seconds
Started Jul 01 10:49:03 AM PDT 24
Finished Jul 01 10:49:11 AM PDT 24
Peak memory 201484 kb
Host smart-c528ba05-14d3-4285-a820-7e42add9df76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843809566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1843809566
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.224407640
Short name T686
Test name
Test status
Simulation time 2156965161 ps
CPU time 6.37 seconds
Started Jul 01 10:49:19 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 201452 kb
Host smart-7ae7188a-a2d3-4a2f-9056-e033799debcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224407640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.224407640
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1406147772
Short name T794
Test name
Test status
Simulation time 2511504537 ps
CPU time 7.55 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 201448 kb
Host smart-e3c4616d-781d-4eb5-8063-4603d830ed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406147772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.1406147772
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.3748511476
Short name T456
Test name
Test status
Simulation time 2117306897 ps
CPU time 3.19 seconds
Started Jul 01 10:49:20 AM PDT 24
Finished Jul 01 10:49:24 AM PDT 24
Peak memory 201448 kb
Host smart-6ba2c611-28be-4821-b56e-5d69b94f1d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748511476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3748511476
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.4262866456
Short name T188
Test name
Test status
Simulation time 13164103162 ps
CPU time 5.22 seconds
Started Jul 01 10:49:04 AM PDT 24
Finished Jul 01 10:49:10 AM PDT 24
Peak memory 201556 kb
Host smart-9f5a84e0-ea36-4c5f-8beb-183706a9a317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262866456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.4262866456
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.912404389
Short name T768
Test name
Test status
Simulation time 35406890226 ps
CPU time 94.18 seconds
Started Jul 01 10:49:03 AM PDT 24
Finished Jul 01 10:50:38 AM PDT 24
Peak memory 218340 kb
Host smart-628a8e34-57b1-4c13-98bb-551d915bf402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912404389 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.912404389
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1289333747
Short name T608
Test name
Test status
Simulation time 11228191442 ps
CPU time 4.95 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:14 AM PDT 24
Peak memory 201548 kb
Host smart-6addd65d-8ac5-41d8-9311-905dbc4bf97a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289333747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.1289333747
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.3207809444
Short name T722
Test name
Test status
Simulation time 2012048450 ps
CPU time 5.75 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:29 AM PDT 24
Peak memory 201500 kb
Host smart-7dee2973-00fa-4948-82f4-262f80518910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207809444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.3207809444
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.94365932
Short name T702
Test name
Test status
Simulation time 3350467753 ps
CPU time 3.99 seconds
Started Jul 01 10:49:06 AM PDT 24
Finished Jul 01 10:49:10 AM PDT 24
Peak memory 201480 kb
Host smart-b004ee98-fa27-49e0-8b9b-ebf9cd90b9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94365932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.94365932
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3984474937
Short name T265
Test name
Test status
Simulation time 90418645091 ps
CPU time 229.42 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:53:07 AM PDT 24
Peak memory 201784 kb
Host smart-46159351-1801-4c94-a61a-7baf327ddba7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984474937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3984474937
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1008680246
Short name T94
Test name
Test status
Simulation time 40128990926 ps
CPU time 49.97 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:59 AM PDT 24
Peak memory 201712 kb
Host smart-298e8964-83a7-4112-a8be-78fbf9850220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008680246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.1008680246
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3500608386
Short name T639
Test name
Test status
Simulation time 4983617915 ps
CPU time 3.9 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:12 AM PDT 24
Peak memory 201536 kb
Host smart-a4f374bf-969f-40d1-a713-da103897d954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500608386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.3500608386
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3377590092
Short name T739
Test name
Test status
Simulation time 5761538266 ps
CPU time 4.23 seconds
Started Jul 01 10:49:29 AM PDT 24
Finished Jul 01 10:49:34 AM PDT 24
Peak memory 201512 kb
Host smart-b30fb0f6-2c1e-4d2b-b79c-e93a20e83a6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377590092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.3377590092
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4192783761
Short name T592
Test name
Test status
Simulation time 2619973504 ps
CPU time 3.92 seconds
Started Jul 01 10:49:11 AM PDT 24
Finished Jul 01 10:49:15 AM PDT 24
Peak memory 201480 kb
Host smart-6be05feb-f1f3-4333-9c9e-7b1894685c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192783761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.4192783761
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.761694541
Short name T559
Test name
Test status
Simulation time 2490918236 ps
CPU time 2.05 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:11 AM PDT 24
Peak memory 201316 kb
Host smart-234bad5b-563c-4de9-806d-0b82e5edb012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761694541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.761694541
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1635576566
Short name T541
Test name
Test status
Simulation time 2272920302 ps
CPU time 2.16 seconds
Started Jul 01 10:49:29 AM PDT 24
Finished Jul 01 10:49:32 AM PDT 24
Peak memory 201420 kb
Host smart-8366de63-b022-4d64-b878-b2e1da17b36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635576566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.1635576566
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2378042858
Short name T601
Test name
Test status
Simulation time 2528139124 ps
CPU time 2.38 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201516 kb
Host smart-410a8e8e-a175-4d0b-9b77-976d2452bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378042858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.2378042858
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.673585242
Short name T659
Test name
Test status
Simulation time 2115222590 ps
CPU time 6.1 seconds
Started Jul 01 10:49:39 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 201364 kb
Host smart-8dab00fb-b5b3-456e-b04a-2c5d9b06df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673585242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.673585242
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3937413516
Short name T146
Test name
Test status
Simulation time 24114110415 ps
CPU time 59.24 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:50:18 AM PDT 24
Peak memory 217372 kb
Host smart-ad7d5008-07c0-452a-b10c-426f38d5771a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937413516 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3937413516
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.298613820
Short name T86
Test name
Test status
Simulation time 4545790454 ps
CPU time 2.46 seconds
Started Jul 01 10:49:08 AM PDT 24
Finished Jul 01 10:49:11 AM PDT 24
Peak memory 201516 kb
Host smart-fb6e3770-a989-4aa8-b486-82dcabbeb829
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298613820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ultra_low_pwr.298613820
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.2239045367
Short name T440
Test name
Test status
Simulation time 2011958621 ps
CPU time 5.81 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201476 kb
Host smart-759792b0-3b23-4da7-873a-cbc01cfc2e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239045367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.2239045367
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2650760881
Short name T91
Test name
Test status
Simulation time 3333940651 ps
CPU time 9.55 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:23 AM PDT 24
Peak memory 201596 kb
Host smart-7cb35a7e-3b31-449d-8222-682a8ea43fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650760881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.2
650760881
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.4174688907
Short name T690
Test name
Test status
Simulation time 50352629231 ps
CPU time 133.93 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:51:34 AM PDT 24
Peak memory 201812 kb
Host smart-674a90ed-2ee0-40ef-b827-7c7818cc823e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174688907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.4174688907
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3136603439
Short name T353
Test name
Test status
Simulation time 54718448102 ps
CPU time 35.85 seconds
Started Jul 01 10:49:11 AM PDT 24
Finished Jul 01 10:49:47 AM PDT 24
Peak memory 201744 kb
Host smart-87558914-0bb9-4867-81d2-d9d4e7badd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136603439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.3136603439
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2318986048
Short name T504
Test name
Test status
Simulation time 3344201916 ps
CPU time 9.17 seconds
Started Jul 01 10:49:09 AM PDT 24
Finished Jul 01 10:49:19 AM PDT 24
Peak memory 201460 kb
Host smart-a6f0d39a-ed5c-42f5-a75a-4ca9ac4abd0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318986048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.2318986048
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.1973020725
Short name T233
Test name
Test status
Simulation time 2599720682 ps
CPU time 6.17 seconds
Started Jul 01 10:49:09 AM PDT 24
Finished Jul 01 10:49:16 AM PDT 24
Peak memory 201500 kb
Host smart-eeef659a-98b9-49ae-a64e-180243e1b876
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973020725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.1973020725
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1510173013
Short name T490
Test name
Test status
Simulation time 2615334897 ps
CPU time 4.14 seconds
Started Jul 01 10:49:23 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 201420 kb
Host smart-d7c8b2f0-aefb-40a9-8ea3-80dbeee87bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510173013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1510173013
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3883285943
Short name T754
Test name
Test status
Simulation time 2567632718 ps
CPU time 1.04 seconds
Started Jul 01 10:49:06 AM PDT 24
Finished Jul 01 10:49:08 AM PDT 24
Peak memory 201468 kb
Host smart-3926f8c2-6106-47a1-a4b4-d33c86f21062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883285943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3883285943
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2871654528
Short name T392
Test name
Test status
Simulation time 2167282195 ps
CPU time 5.78 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201512 kb
Host smart-11c4df1e-29b6-4c3b-9ba6-03dbb71448f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871654528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2871654528
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.4229728742
Short name T709
Test name
Test status
Simulation time 2510472646 ps
CPU time 6.61 seconds
Started Jul 01 10:49:33 AM PDT 24
Finished Jul 01 10:49:40 AM PDT 24
Peak memory 201512 kb
Host smart-0e8fb0ca-e703-4ff3-a2f7-d8018f438b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229728742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.4229728742
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.3567002454
Short name T305
Test name
Test status
Simulation time 2116614131 ps
CPU time 3.23 seconds
Started Jul 01 10:49:44 AM PDT 24
Finished Jul 01 10:49:48 AM PDT 24
Peak memory 201340 kb
Host smart-9fe25c6f-9565-4cc7-8561-11df697cb293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567002454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.3567002454
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.1165431621
Short name T668
Test name
Test status
Simulation time 11164377716 ps
CPU time 30.48 seconds
Started Jul 01 10:49:11 AM PDT 24
Finished Jul 01 10:49:42 AM PDT 24
Peak memory 201500 kb
Host smart-293d812b-0931-4da4-a983-79e44fb684ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165431621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.1165431621
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.198870803
Short name T747
Test name
Test status
Simulation time 4123256562 ps
CPU time 6.1 seconds
Started Jul 01 10:49:15 AM PDT 24
Finished Jul 01 10:49:24 AM PDT 24
Peak memory 201428 kb
Host smart-2b57c185-71e1-4338-a4ce-f9b907f40b19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198870803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ultra_low_pwr.198870803
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.3524136419
Short name T491
Test name
Test status
Simulation time 2011778176 ps
CPU time 5.82 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:26 AM PDT 24
Peak memory 201464 kb
Host smart-8bbe9c26-e5d9-4043-82ca-bbf706a8976f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524136419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.3524136419
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.4050394626
Short name T48
Test name
Test status
Simulation time 3126923293 ps
CPU time 2.53 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201360 kb
Host smart-d8a80a54-ef93-4ae9-9160-5c51cb13ce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050394626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.4
050394626
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.25565546
Short name T126
Test name
Test status
Simulation time 191409239551 ps
CPU time 42 seconds
Started Jul 01 10:49:24 AM PDT 24
Finished Jul 01 10:50:06 AM PDT 24
Peak memory 201824 kb
Host smart-67503f57-bfb4-4512-868c-a84932188abd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25565546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctr
l_combo_detect.25565546
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.804244486
Short name T641
Test name
Test status
Simulation time 24430698894 ps
CPU time 7.21 seconds
Started Jul 01 10:49:16 AM PDT 24
Finished Jul 01 10:49:26 AM PDT 24
Peak memory 201832 kb
Host smart-e07c0803-6855-459c-bd2f-eb99155006af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804244486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_wi
th_pre_cond.804244486
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.689769933
Short name T578
Test name
Test status
Simulation time 5482114374 ps
CPU time 7.72 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:20 AM PDT 24
Peak memory 201556 kb
Host smart-2651eaac-fd56-4477-8994-3a38d39d7526
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689769933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ec_pwr_on_rst.689769933
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1881594605
Short name T35
Test name
Test status
Simulation time 3386501121 ps
CPU time 7.16 seconds
Started Jul 01 10:49:29 AM PDT 24
Finished Jul 01 10:49:37 AM PDT 24
Peak memory 201440 kb
Host smart-7ee05340-c121-4a90-aa09-ca0556864661
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881594605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.1881594605
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4091931835
Short name T751
Test name
Test status
Simulation time 2843987156 ps
CPU time 1.07 seconds
Started Jul 01 10:49:14 AM PDT 24
Finished Jul 01 10:49:17 AM PDT 24
Peak memory 201488 kb
Host smart-d7f01207-229b-42e9-a0bc-6651decd6c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091931835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.4091931835
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.548638786
Short name T25
Test name
Test status
Simulation time 2476135781 ps
CPU time 2.1 seconds
Started Jul 01 10:49:10 AM PDT 24
Finished Jul 01 10:49:13 AM PDT 24
Peak memory 201312 kb
Host smart-d021a48a-90f4-4f97-a65a-33fb082bdf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548638786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.548638786
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4277209804
Short name T695
Test name
Test status
Simulation time 2262005682 ps
CPU time 2.51 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:49:16 AM PDT 24
Peak memory 201516 kb
Host smart-ee2d35d7-962e-4ed8-8c45-73faa7fe45f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277209804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.4277209804
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.915291435
Short name T310
Test name
Test status
Simulation time 2514650092 ps
CPU time 3.9 seconds
Started Jul 01 10:49:11 AM PDT 24
Finished Jul 01 10:49:16 AM PDT 24
Peak memory 201360 kb
Host smart-93528462-b313-4b68-be05-f3c8832be8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915291435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.915291435
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.3339223671
Short name T419
Test name
Test status
Simulation time 2117034983 ps
CPU time 3.16 seconds
Started Jul 01 10:49:07 AM PDT 24
Finished Jul 01 10:49:11 AM PDT 24
Peak memory 201440 kb
Host smart-deacbe6f-7d61-4efe-a40b-edafdee18551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339223671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3339223671
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3974126053
Short name T57
Test name
Test status
Simulation time 10884823806 ps
CPU time 26.84 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:50:14 AM PDT 24
Peak memory 201560 kb
Host smart-9ed332a3-9ea2-4282-b1c4-ccec6176b1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974126053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3974126053
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1924314325
Short name T216
Test name
Test status
Simulation time 1477358060594 ps
CPU time 78.34 seconds
Started Jul 01 10:49:12 AM PDT 24
Finished Jul 01 10:50:31 AM PDT 24
Peak memory 210220 kb
Host smart-77e62f40-c8b0-489d-a557-547dac550830
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924314325 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1924314325
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.536105947
Short name T630
Test name
Test status
Simulation time 207257063345 ps
CPU time 35.38 seconds
Started Jul 01 10:49:13 AM PDT 24
Finished Jul 01 10:49:49 AM PDT 24
Peak memory 201500 kb
Host smart-0e44fde6-742d-42db-841f-fdc551a26cef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536105947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ultra_low_pwr.536105947
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.578395917
Short name T602
Test name
Test status
Simulation time 2038691967 ps
CPU time 1.88 seconds
Started Jul 01 10:49:35 AM PDT 24
Finished Jul 01 10:49:37 AM PDT 24
Peak memory 201360 kb
Host smart-7dd55b7b-4b8f-4343-adc0-83dac7ba807b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578395917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_tes
t.578395917
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3695747822
Short name T107
Test name
Test status
Simulation time 3246691342 ps
CPU time 3.47 seconds
Started Jul 01 10:49:42 AM PDT 24
Finished Jul 01 10:49:46 AM PDT 24
Peak memory 201544 kb
Host smart-cc7429b5-60ca-440a-8b66-dd28835ed493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695747822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.3
695747822
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.2738030735
Short name T793
Test name
Test status
Simulation time 35598069714 ps
CPU time 87.5 seconds
Started Jul 01 10:49:11 AM PDT 24
Finished Jul 01 10:50:39 AM PDT 24
Peak memory 201784 kb
Host smart-e71dfed3-50d8-4105-8c88-2c233c88839b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738030735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.2738030735
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3573610322
Short name T532
Test name
Test status
Simulation time 4974208036 ps
CPU time 14.06 seconds
Started Jul 01 10:49:28 AM PDT 24
Finished Jul 01 10:49:43 AM PDT 24
Peak memory 201516 kb
Host smart-908ebdbb-d834-4dcb-9151-08cbcab127f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573610322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.3573610322
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1853198225
Short name T552
Test name
Test status
Simulation time 2613048628 ps
CPU time 7.8 seconds
Started Jul 01 10:49:25 AM PDT 24
Finished Jul 01 10:49:34 AM PDT 24
Peak memory 201428 kb
Host smart-a18d2cb5-2f80-46cc-89f7-4987bf08edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853198225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1853198225
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.864155483
Short name T472
Test name
Test status
Simulation time 2511003942 ps
CPU time 1.5 seconds
Started Jul 01 10:49:11 AM PDT 24
Finished Jul 01 10:49:13 AM PDT 24
Peak memory 201476 kb
Host smart-f591fa84-f1f0-4b39-b927-9838d9240617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864155483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.864155483
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3727764566
Short name T610
Test name
Test status
Simulation time 2252605273 ps
CPU time 2.06 seconds
Started Jul 01 10:49:23 AM PDT 24
Finished Jul 01 10:49:25 AM PDT 24
Peak memory 201484 kb
Host smart-5dc78e24-f16c-4252-93a5-a0c0fe0b00bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727764566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.3727764566
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3195678777
Short name T184
Test name
Test status
Simulation time 2512063436 ps
CPU time 6.81 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:51 AM PDT 24
Peak memory 201432 kb
Host smart-c6431ee2-30be-471c-a79b-9019123cb567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195678777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3195678777
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.692294073
Short name T17
Test name
Test status
Simulation time 2140006374 ps
CPU time 1.57 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:21 AM PDT 24
Peak memory 201192 kb
Host smart-85927c67-588c-4848-b81d-27923515711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692294073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.692294073
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.1999304807
Short name T312
Test name
Test status
Simulation time 9754356843 ps
CPU time 7.21 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 201560 kb
Host smart-b57fcf6b-ed6b-4119-a34f-76557645d04c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999304807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.1999304807
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.4021901846
Short name T158
Test name
Test status
Simulation time 68994175973 ps
CPU time 180.36 seconds
Started Jul 01 10:49:49 AM PDT 24
Finished Jul 01 10:52:50 AM PDT 24
Peak memory 210056 kb
Host smart-7e85c41c-4289-410e-ac0d-3ea85f4407ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021901846 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.4021901846
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1651903159
Short name T588
Test name
Test status
Simulation time 4282354673 ps
CPU time 6.91 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 201472 kb
Host smart-62f401f5-c678-4eee-b8a1-e432392d1a96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651903159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1651903159
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.2845325028
Short name T557
Test name
Test status
Simulation time 2014431107 ps
CPU time 6.06 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:49:26 AM PDT 24
Peak memory 201452 kb
Host smart-7a44f6e9-0c07-46b6-879a-432eed49f054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845325028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.2845325028
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.474798813
Short name T542
Test name
Test status
Simulation time 125996134955 ps
CPU time 103.4 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:51:31 AM PDT 24
Peak memory 201604 kb
Host smart-9b7234c3-95a9-42f8-a084-8882a0f7cf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474798813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.474798813
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.699381238
Short name T705
Test name
Test status
Simulation time 61636198947 ps
CPU time 37.97 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:50:34 AM PDT 24
Peak memory 201848 kb
Host smart-d1c1d0e6-fea7-49eb-ba9e-d5456395e2a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699381238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_combo_detect.699381238
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3122293810
Short name T244
Test name
Test status
Simulation time 31197214643 ps
CPU time 40.24 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 201836 kb
Host smart-9627ebcf-6118-4d0c-956a-97413a2179f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122293810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.3122293810
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1486696637
Short name T236
Test name
Test status
Simulation time 3114274707 ps
CPU time 5.32 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 201424 kb
Host smart-4a1230cc-bf56-418c-9fb4-5948e3786cde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486696637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1486696637
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.3436852683
Short name T39
Test name
Test status
Simulation time 4743974162 ps
CPU time 10.67 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:49:31 AM PDT 24
Peak memory 201568 kb
Host smart-22939420-4c6d-42e6-a518-c0dcbe773274
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436852683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.3436852683
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2505880535
Short name T109
Test name
Test status
Simulation time 2613522709 ps
CPU time 7.77 seconds
Started Jul 01 10:49:42 AM PDT 24
Finished Jul 01 10:49:50 AM PDT 24
Peak memory 201504 kb
Host smart-3029a98c-3b6e-4172-af24-19cade7b7b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505880535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.2505880535
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2089234972
Short name T621
Test name
Test status
Simulation time 2452259314 ps
CPU time 8.3 seconds
Started Jul 01 10:49:21 AM PDT 24
Finished Jul 01 10:49:30 AM PDT 24
Peak memory 201484 kb
Host smart-45baa6dc-e48c-4d39-afee-320184881a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089234972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.2089234972
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.460541399
Short name T468
Test name
Test status
Simulation time 2224074128 ps
CPU time 6.14 seconds
Started Jul 01 10:49:20 AM PDT 24
Finished Jul 01 10:49:27 AM PDT 24
Peak memory 201484 kb
Host smart-960b643d-b202-4523-a623-a45921aeee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460541399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.460541399
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2968743595
Short name T241
Test name
Test status
Simulation time 2527355959 ps
CPU time 2.24 seconds
Started Jul 01 10:49:17 AM PDT 24
Finished Jul 01 10:49:22 AM PDT 24
Peak memory 201500 kb
Host smart-a3b9be7c-b3a8-4125-8f1e-98bf6f704323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968743595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2968743595
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.1282513423
Short name T224
Test name
Test status
Simulation time 2115928856 ps
CPU time 3.12 seconds
Started Jul 01 10:49:56 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 201340 kb
Host smart-9bf727ac-12ef-49c2-8e0d-b1aa161ec6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282513423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1282513423
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.3633987476
Short name T161
Test name
Test status
Simulation time 16942716836 ps
CPU time 24.42 seconds
Started Jul 01 10:49:18 AM PDT 24
Finished Jul 01 10:49:44 AM PDT 24
Peak memory 201508 kb
Host smart-67b9c3f3-234a-49e4-accc-772d74c34a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633987476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.3633987476
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3170283029
Short name T137
Test name
Test status
Simulation time 1272537845732 ps
CPU time 326.65 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:55:14 AM PDT 24
Peak memory 201504 kb
Host smart-f2048dff-89a5-4afe-a0da-c16d9966f80e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170283029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3170283029
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.2479319657
Short name T437
Test name
Test status
Simulation time 2031044317 ps
CPU time 1.97 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:47:56 AM PDT 24
Peak memory 201460 kb
Host smart-31f560d0-5e41-4228-acea-7ca0a5b3e3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479319657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.2479319657
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2768701437
Short name T785
Test name
Test status
Simulation time 3051296116 ps
CPU time 8.71 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:16 AM PDT 24
Peak memory 201572 kb
Host smart-0f03b5a7-bb90-487b-8c03-70e945d3a24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768701437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2768701437
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.218035669
Short name T774
Test name
Test status
Simulation time 115830369740 ps
CPU time 142.62 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:50:21 AM PDT 24
Peak memory 201852 kb
Host smart-318d1fb2-4220-4360-9445-cc7dc78dcc2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218035669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_combo_detect.218035669
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3823645182
Short name T478
Test name
Test status
Simulation time 88795740188 ps
CPU time 215.5 seconds
Started Jul 01 10:47:52 AM PDT 24
Finished Jul 01 10:51:29 AM PDT 24
Peak memory 201828 kb
Host smart-d7b168be-8d0c-4661-8fdb-6a24248bd058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823645182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.3823645182
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2082863293
Short name T698
Test name
Test status
Simulation time 3375766990 ps
CPU time 2.81 seconds
Started Jul 01 10:47:59 AM PDT 24
Finished Jul 01 10:48:03 AM PDT 24
Peak memory 201336 kb
Host smart-3ecaf1f2-b837-4cfb-9a57-d97afbe72f81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082863293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.2082863293
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3600263919
Short name T762
Test name
Test status
Simulation time 3225487885 ps
CPU time 2.3 seconds
Started Jul 01 10:47:47 AM PDT 24
Finished Jul 01 10:47:50 AM PDT 24
Peak memory 201436 kb
Host smart-9cd94b24-3cdc-4a1c-aaaa-f93e03d6f1cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600263919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3600263919
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3131425587
Short name T509
Test name
Test status
Simulation time 2613954464 ps
CPU time 7.45 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:10 AM PDT 24
Peak memory 201428 kb
Host smart-007f246a-d193-4676-8381-5d376fc04e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131425587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3131425587
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2828048166
Short name T654
Test name
Test status
Simulation time 2452053661 ps
CPU time 4.3 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:48:03 AM PDT 24
Peak memory 201504 kb
Host smart-aa3df65b-87f6-4f97-aa77-40bcff0ea208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828048166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.2828048166
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1863666013
Short name T145
Test name
Test status
Simulation time 2237148811 ps
CPU time 3.48 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:03 AM PDT 24
Peak memory 201536 kb
Host smart-9f4c27ea-8f85-4da0-a35c-d8f144fce36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863666013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.1863666013
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3738721287
Short name T462
Test name
Test status
Simulation time 2524818673 ps
CPU time 2.32 seconds
Started Jul 01 10:47:43 AM PDT 24
Finished Jul 01 10:47:45 AM PDT 24
Peak memory 201384 kb
Host smart-e32afc97-d100-4b25-af8e-e8f35fc51d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738721287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.3738721287
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.670344477
Short name T531
Test name
Test status
Simulation time 2112538561 ps
CPU time 6.13 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:08 AM PDT 24
Peak memory 201440 kb
Host smart-91ddcb18-2c3f-49cc-a3c9-b29f418c68ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670344477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.670344477
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.2908376053
Short name T384
Test name
Test status
Simulation time 6966391366 ps
CPU time 5.27 seconds
Started Jul 01 10:47:54 AM PDT 24
Finished Jul 01 10:48:01 AM PDT 24
Peak memory 201532 kb
Host smart-7ab0da88-04aa-4b6b-a793-b7ee90951309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908376053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.2908376053
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3065314434
Short name T134
Test name
Test status
Simulation time 4706430242 ps
CPU time 4.74 seconds
Started Jul 01 10:48:12 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 201524 kb
Host smart-1a78e176-f507-4ac2-8727-5facada48991
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065314434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.3065314434
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.756823470
Short name T688
Test name
Test status
Simulation time 26112087485 ps
CPU time 12.51 seconds
Started Jul 01 10:49:56 AM PDT 24
Finished Jul 01 10:50:09 AM PDT 24
Peak memory 201964 kb
Host smart-1604c052-2321-4db7-a100-bf01100387bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756823470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_wi
th_pre_cond.756823470
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.974147921
Short name T350
Test name
Test status
Simulation time 94597394470 ps
CPU time 227.8 seconds
Started Jul 01 10:49:47 AM PDT 24
Finished Jul 01 10:53:36 AM PDT 24
Peak memory 201856 kb
Host smart-e2c068e2-f5b4-4ba3-8bf8-d12b83cd9265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974147921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_wi
th_pre_cond.974147921
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.912172860
Short name T70
Test name
Test status
Simulation time 75209818843 ps
CPU time 49.16 seconds
Started Jul 01 10:49:41 AM PDT 24
Finished Jul 01 10:50:36 AM PDT 24
Peak memory 201748 kb
Host smart-a19c38b6-63e9-48db-b593-f6c376895fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912172860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_wi
th_pre_cond.912172860
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1387719208
Short name T528
Test name
Test status
Simulation time 25081344598 ps
CPU time 61.61 seconds
Started Jul 01 10:49:56 AM PDT 24
Finished Jul 01 10:50:58 AM PDT 24
Peak memory 201840 kb
Host smart-3245323a-70cc-4e39-b4d2-8deeb71b3e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387719208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.1387719208
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4133511101
Short name T344
Test name
Test status
Simulation time 75165227305 ps
CPU time 200.42 seconds
Started Jul 01 10:49:23 AM PDT 24
Finished Jul 01 10:52:44 AM PDT 24
Peak memory 201792 kb
Host smart-3e3b92c4-00a3-4aff-b8e8-e569cf567c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133511101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.4133511101
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3421120936
Short name T248
Test name
Test status
Simulation time 69836158878 ps
CPU time 46.56 seconds
Started Jul 01 10:49:41 AM PDT 24
Finished Jul 01 10:50:28 AM PDT 24
Peak memory 201836 kb
Host smart-55806f9d-b11f-4d14-ba99-a5d7b2c0d983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421120936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3421120936
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.694515278
Short name T604
Test name
Test status
Simulation time 2015495686 ps
CPU time 5.41 seconds
Started Jul 01 10:48:15 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201404 kb
Host smart-fa03ee2a-9e94-454c-9b5e-975b11f401ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694515278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test
.694515278
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.409528227
Short name T44
Test name
Test status
Simulation time 3056212188 ps
CPU time 7.83 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:15 AM PDT 24
Peak memory 201564 kb
Host smart-991b72e6-ca0b-446d-97de-b6ea9f4c8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409528227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.409528227
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2574901313
Short name T711
Test name
Test status
Simulation time 176608291320 ps
CPU time 218.21 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:51:36 AM PDT 24
Peak memory 201660 kb
Host smart-0556ccb2-06c4-4b9f-92fc-6caa06cd4e69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574901313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.2574901313
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.969506596
Short name T733
Test name
Test status
Simulation time 24101291495 ps
CPU time 17.46 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201860 kb
Host smart-01ff94d1-686f-41d9-99d1-13031aff1649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969506596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wit
h_pre_cond.969506596
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2494948134
Short name T237
Test name
Test status
Simulation time 687151327089 ps
CPU time 215.22 seconds
Started Jul 01 10:48:13 AM PDT 24
Finished Jul 01 10:51:49 AM PDT 24
Peak memory 201456 kb
Host smart-443890d2-39b6-4890-8b4e-00badf16ed00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494948134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2494948134
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.2301603413
Short name T150
Test name
Test status
Simulation time 5353316894 ps
CPU time 6.52 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:48:05 AM PDT 24
Peak memory 201560 kb
Host smart-8729795c-378e-4f81-be1c-aa61a39fd8bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301603413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.2301603413
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.839605462
Short name T720
Test name
Test status
Simulation time 2619710103 ps
CPU time 3.99 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:05 AM PDT 24
Peak memory 201504 kb
Host smart-f847b902-9367-4caf-bb97-afe6df6be29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839605462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.839605462
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1335943043
Short name T714
Test name
Test status
Simulation time 2489123647 ps
CPU time 2.3 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:47:56 AM PDT 24
Peak memory 201524 kb
Host smart-f7c02b26-1e2c-4357-b30a-95df20d54a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335943043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1335943043
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.283922755
Short name T579
Test name
Test status
Simulation time 2336104587 ps
CPU time 0.97 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:48:24 AM PDT 24
Peak memory 201512 kb
Host smart-2fa2a3fd-1ba5-46a8-a5cb-a33bb734a731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283922755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.283922755
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2192913238
Short name T311
Test name
Test status
Simulation time 2511416425 ps
CPU time 6.13 seconds
Started Jul 01 10:48:14 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201512 kb
Host smart-ac5d18ab-377b-4d3a-a1cb-ae6adb9dd505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192913238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.2192913238
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.3556029963
Short name T214
Test name
Test status
Simulation time 2126800094 ps
CPU time 1.87 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:47:59 AM PDT 24
Peak memory 201468 kb
Host smart-6999c5ad-90e9-4713-8b93-30a19d4b7621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556029963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3556029963
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1143467960
Short name T536
Test name
Test status
Simulation time 15460167529 ps
CPU time 13.32 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:48:12 AM PDT 24
Peak memory 201768 kb
Host smart-ee7b6da8-c1f0-4a8a-8660-ef183959809b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143467960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1143467960
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1493503708
Short name T23
Test name
Test status
Simulation time 9140419166 ps
CPU time 3.93 seconds
Started Jul 01 10:48:04 AM PDT 24
Finished Jul 01 10:48:09 AM PDT 24
Peak memory 201388 kb
Host smart-b792f136-c6b2-4500-9d91-05c1c42bbd15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493503708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1493503708
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3511982175
Short name T263
Test name
Test status
Simulation time 71122389824 ps
CPU time 16.92 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:50:05 AM PDT 24
Peak memory 201628 kb
Host smart-78e5dc6f-c6ac-4c84-83ee-a60fe3d4a44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511982175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.3511982175
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1600346230
Short name T68
Test name
Test status
Simulation time 59690896271 ps
CPU time 135.29 seconds
Started Jul 01 10:49:31 AM PDT 24
Finished Jul 01 10:51:47 AM PDT 24
Peak memory 201800 kb
Host smart-e6885116-43a0-4d53-b9b1-a2b4beb038c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600346230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.1600346230
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3484291517
Short name T680
Test name
Test status
Simulation time 64621380212 ps
CPU time 161.42 seconds
Started Jul 01 10:49:50 AM PDT 24
Finished Jul 01 10:52:32 AM PDT 24
Peak memory 201804 kb
Host smart-b2b075a8-03fe-4f2a-8c0d-3aa4d6613854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484291517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.3484291517
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3528670256
Short name T742
Test name
Test status
Simulation time 146662012992 ps
CPU time 183.2 seconds
Started Jul 01 10:49:22 AM PDT 24
Finished Jul 01 10:52:25 AM PDT 24
Peak memory 201840 kb
Host smart-3c6eef7c-2e67-4edf-af25-3b97125066c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528670256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3528670256
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.192098763
Short name T744
Test name
Test status
Simulation time 79014044976 ps
CPU time 96.24 seconds
Started Jul 01 10:50:01 AM PDT 24
Finished Jul 01 10:51:38 AM PDT 24
Peak memory 201844 kb
Host smart-44f57664-807c-4273-bfa0-e23db3c37ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192098763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_wi
th_pre_cond.192098763
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.52436754
Short name T169
Test name
Test status
Simulation time 2007251336 ps
CPU time 5.98 seconds
Started Jul 01 10:47:55 AM PDT 24
Finished Jul 01 10:48:02 AM PDT 24
Peak memory 201408 kb
Host smart-a831be1c-5d01-415e-92bb-ff62810d7aea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52436754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.52436754
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1574091324
Short name T398
Test name
Test status
Simulation time 3058491580 ps
CPU time 1.71 seconds
Started Jul 01 10:48:10 AM PDT 24
Finished Jul 01 10:48:13 AM PDT 24
Peak memory 201504 kb
Host smart-a49d4182-4970-4a98-80d5-3266d61e67d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574091324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.1574091324
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.764587097
Short name T104
Test name
Test status
Simulation time 169763061203 ps
CPU time 133.01 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:50:07 AM PDT 24
Peak memory 201788 kb
Host smart-9b6d20ab-fcec-491f-9759-0c4fd9af8ec1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764587097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_combo_detect.764587097
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.808962699
Short name T545
Test name
Test status
Simulation time 54178782389 ps
CPU time 37.02 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:44 AM PDT 24
Peak memory 201800 kb
Host smart-57d98e7d-0329-4c9f-b657-2b901602edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808962699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wit
h_pre_cond.808962699
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.4202101712
Short name T422
Test name
Test status
Simulation time 4145991610 ps
CPU time 5.44 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:32 AM PDT 24
Peak memory 201472 kb
Host smart-507340eb-fa63-47af-9623-fdbae9854986
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202101712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.4202101712
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2537542420
Short name T718
Test name
Test status
Simulation time 2551796824 ps
CPU time 6.85 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 201212 kb
Host smart-a11a107c-342e-42f6-bd68-4b0119636ff0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537542420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2537542420
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.326634851
Short name T649
Test name
Test status
Simulation time 2625241217 ps
CPU time 2.46 seconds
Started Jul 01 10:48:02 AM PDT 24
Finished Jul 01 10:48:05 AM PDT 24
Peak memory 201448 kb
Host smart-de0182c2-701d-4139-86f2-da17278b373b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326634851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.326634851
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2805711514
Short name T515
Test name
Test status
Simulation time 2536555391 ps
CPU time 1.31 seconds
Started Jul 01 10:48:00 AM PDT 24
Finished Jul 01 10:48:03 AM PDT 24
Peak memory 201536 kb
Host smart-4c67aa57-6055-4c2c-a04d-b377d61afe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805711514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.2805711514
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2075458672
Short name T183
Test name
Test status
Simulation time 2185296077 ps
CPU time 6.06 seconds
Started Jul 01 10:47:55 AM PDT 24
Finished Jul 01 10:48:03 AM PDT 24
Peak memory 201424 kb
Host smart-84422e43-32cd-4701-b413-a0727afdae5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075458672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.2075458672
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.297117674
Short name T434
Test name
Test status
Simulation time 2517839340 ps
CPU time 3.03 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:25 AM PDT 24
Peak memory 201500 kb
Host smart-3846aace-481e-4ae9-bf66-2913c2391489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297117674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.297117674
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.144698323
Short name T700
Test name
Test status
Simulation time 2108756958 ps
CPU time 5.79 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201356 kb
Host smart-2525ed6d-7de0-49a3-a7f0-602d836d0854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144698323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.144698323
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.4257406708
Short name T409
Test name
Test status
Simulation time 14155040730 ps
CPU time 9.92 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201804 kb
Host smart-3b904a7a-0e4d-433a-9822-71f2a384f43a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257406708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.4257406708
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1434609248
Short name T693
Test name
Test status
Simulation time 42801290089 ps
CPU time 48.74 seconds
Started Jul 01 10:48:11 AM PDT 24
Finished Jul 01 10:49:00 AM PDT 24
Peak memory 210208 kb
Host smart-a4e43454-4d61-4cbb-8996-9d6086d0ac51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434609248 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1434609248
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1778460219
Short name T507
Test name
Test status
Simulation time 3519990698 ps
CPU time 3.8 seconds
Started Jul 01 10:48:06 AM PDT 24
Finished Jul 01 10:48:11 AM PDT 24
Peak memory 201484 kb
Host smart-3fa8adea-7829-4e65-9a0b-ff9826e7ca0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778460219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.1778460219
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3467407053
Short name T566
Test name
Test status
Simulation time 64046669393 ps
CPU time 156.8 seconds
Started Jul 01 10:49:50 AM PDT 24
Finished Jul 01 10:52:28 AM PDT 24
Peak memory 201940 kb
Host smart-82b292b1-1cc0-4468-bbb3-12ca89cc3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467407053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.3467407053
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1539624352
Short name T554
Test name
Test status
Simulation time 27102125831 ps
CPU time 20.73 seconds
Started Jul 01 10:50:01 AM PDT 24
Finished Jul 01 10:50:22 AM PDT 24
Peak memory 201776 kb
Host smart-4bb8fc3c-dce2-485a-82d2-8febb06c3d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539624352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1539624352
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2832259083
Short name T706
Test name
Test status
Simulation time 78274147599 ps
CPU time 47.01 seconds
Started Jul 01 10:49:23 AM PDT 24
Finished Jul 01 10:50:10 AM PDT 24
Peak memory 201756 kb
Host smart-b7a6d2a1-b0ed-4939-b1f5-bd84b60bec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832259083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2832259083
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.112976833
Short name T351
Test name
Test status
Simulation time 99534461054 ps
CPU time 40.75 seconds
Started Jul 01 10:49:22 AM PDT 24
Finished Jul 01 10:50:03 AM PDT 24
Peak memory 201784 kb
Host smart-a46440d1-0617-44d6-9787-1bb650e334e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112976833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_wi
th_pre_cond.112976833
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2807053539
Short name T69
Test name
Test status
Simulation time 81569701842 ps
CPU time 21.31 seconds
Started Jul 01 10:49:21 AM PDT 24
Finished Jul 01 10:49:43 AM PDT 24
Peak memory 201872 kb
Host smart-50371fd1-9c32-4d99-9c8b-c96117b7359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807053539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.2807053539
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3331454780
Short name T243
Test name
Test status
Simulation time 23583369696 ps
CPU time 59.41 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:50:55 AM PDT 24
Peak memory 201836 kb
Host smart-96924235-04d0-4c2a-8296-9d15abd48d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331454780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.3331454780
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2530593833
Short name T79
Test name
Test status
Simulation time 139907762956 ps
CPU time 369.02 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:55:53 AM PDT 24
Peak memory 201760 kb
Host smart-6b1d76de-555b-4d97-b4a5-899a3bb0f970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530593833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.2530593833
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3985122037
Short name T379
Test name
Test status
Simulation time 29340190082 ps
CPU time 37.28 seconds
Started Jul 01 10:49:24 AM PDT 24
Finished Jul 01 10:50:02 AM PDT 24
Peak memory 201792 kb
Host smart-656a8473-3c81-4485-a5b0-fe466534407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985122037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.3985122037
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.4136375442
Short name T511
Test name
Test status
Simulation time 33391301870 ps
CPU time 89.7 seconds
Started Jul 01 10:49:45 AM PDT 24
Finished Jul 01 10:51:16 AM PDT 24
Peak memory 201804 kb
Host smart-125d0abd-fbcc-4f22-b1b5-d4f020f378e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136375442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.4136375442
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.3021733450
Short name T558
Test name
Test status
Simulation time 2014101132 ps
CPU time 6.28 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:48:01 AM PDT 24
Peak memory 201472 kb
Host smart-8578b7f7-684b-41aa-8b0f-c8c1a7769c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021733450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.3021733450
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3155465564
Short name T27
Test name
Test status
Simulation time 3138073939 ps
CPU time 8.1 seconds
Started Jul 01 10:48:20 AM PDT 24
Finished Jul 01 10:48:29 AM PDT 24
Peak memory 201600 kb
Host smart-ecd77b3c-b23d-4290-a304-e7d65ffa994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155465564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.3155465564
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.167455748
Short name T80
Test name
Test status
Simulation time 53041008216 ps
CPU time 35.6 seconds
Started Jul 01 10:47:54 AM PDT 24
Finished Jul 01 10:48:31 AM PDT 24
Peak memory 201624 kb
Host smart-ac16062d-ca27-4fdc-a53b-241568d16642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167455748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wit
h_pre_cond.167455748
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.622374174
Short name T19
Test name
Test status
Simulation time 2606390989 ps
CPU time 7.54 seconds
Started Jul 01 10:47:55 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201496 kb
Host smart-b4c2883b-45cf-40d3-b61c-78d7c9ebb822
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622374174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ec_pwr_on_rst.622374174
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3150328677
Short name T36
Test name
Test status
Simulation time 2914535193 ps
CPU time 1.74 seconds
Started Jul 01 10:48:03 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 201404 kb
Host smart-f38394ad-caac-497e-bdd5-0e75a810ddf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150328677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.3150328677
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.420673509
Short name T710
Test name
Test status
Simulation time 2617971798 ps
CPU time 4.09 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:47:58 AM PDT 24
Peak memory 201492 kb
Host smart-e545fa58-4ea8-4ecc-a0e2-f94424443531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420673509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.420673509
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1540361980
Short name T486
Test name
Test status
Simulation time 2481929297 ps
CPU time 4.03 seconds
Started Jul 01 10:47:53 AM PDT 24
Finished Jul 01 10:47:59 AM PDT 24
Peak memory 201504 kb
Host smart-1762a1be-d96d-4796-93f4-ed76b8480563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540361980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1540361980
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1287421723
Short name T721
Test name
Test status
Simulation time 2242093724 ps
CPU time 1.88 seconds
Started Jul 01 10:48:17 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201504 kb
Host smart-067726a0-c55f-4e06-8c63-4447a05bcff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287421723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1287421723
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2071197605
Short name T466
Test name
Test status
Simulation time 2509201450 ps
CPU time 6.99 seconds
Started Jul 01 10:47:55 AM PDT 24
Finished Jul 01 10:48:03 AM PDT 24
Peak memory 201476 kb
Host smart-a1eb4ba4-4b86-4e63-9fdc-109188e8f2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071197605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2071197605
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.1884329709
Short name T561
Test name
Test status
Simulation time 2167631646 ps
CPU time 1.02 seconds
Started Jul 01 10:48:02 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201484 kb
Host smart-588c9e57-e513-422f-ad00-07c2062f9d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884329709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1884329709
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.2131729292
Short name T162
Test name
Test status
Simulation time 15774557828 ps
CPU time 31.71 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:48:48 AM PDT 24
Peak memory 201620 kb
Host smart-254d39dc-6b11-4a5c-aba3-7de822abf683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131729292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.2131729292
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2477268624
Short name T791
Test name
Test status
Simulation time 3021168871 ps
CPU time 0.98 seconds
Started Jul 01 10:48:22 AM PDT 24
Finished Jul 01 10:48:26 AM PDT 24
Peak memory 201392 kb
Host smart-d3f942cd-a704-4aa9-9b80-941be8bcfbbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477268624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.2477268624
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2916611769
Short name T370
Test name
Test status
Simulation time 45826257201 ps
CPU time 60.42 seconds
Started Jul 01 10:49:40 AM PDT 24
Finished Jul 01 10:50:41 AM PDT 24
Peak memory 201760 kb
Host smart-ba5b4acd-e138-4cc0-81ec-dc35603586a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916611769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.2916611769
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2653889078
Short name T245
Test name
Test status
Simulation time 98685625530 ps
CPU time 118.62 seconds
Started Jul 01 10:49:24 AM PDT 24
Finished Jul 01 10:51:24 AM PDT 24
Peak memory 201800 kb
Host smart-afafa813-43fc-44c0-bef6-cbc8cc68a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653889078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.2653889078
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.601378851
Short name T526
Test name
Test status
Simulation time 27331898861 ps
CPU time 67.53 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:50:55 AM PDT 24
Peak memory 201736 kb
Host smart-27c103ce-4337-4ea9-9e36-f72b3a37401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601378851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wi
th_pre_cond.601378851
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2103205819
Short name T341
Test name
Test status
Simulation time 62299825870 ps
CPU time 41 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:50:24 AM PDT 24
Peak memory 201640 kb
Host smart-68e37a21-f2fd-4818-a906-b078f6c30865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103205819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.2103205819
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2124507175
Short name T589
Test name
Test status
Simulation time 82600620992 ps
CPU time 98.78 seconds
Started Jul 01 10:50:02 AM PDT 24
Finished Jul 01 10:51:41 AM PDT 24
Peak memory 201872 kb
Host smart-6c23fbef-5540-44af-8f5b-f42fd67cec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124507175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.2124507175
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1315278809
Short name T363
Test name
Test status
Simulation time 150785014871 ps
CPU time 363.37 seconds
Started Jul 01 10:49:35 AM PDT 24
Finished Jul 01 10:55:38 AM PDT 24
Peak memory 201764 kb
Host smart-90bf548c-db33-467b-992c-f2ffd0d3fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315278809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.1315278809
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.1592192056
Short name T743
Test name
Test status
Simulation time 2031029953 ps
CPU time 1.96 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201520 kb
Host smart-75afbdf4-cc00-44b2-9045-2109eebb1719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592192056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.1592192056
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.974474042
Short name T47
Test name
Test status
Simulation time 3282145631 ps
CPU time 5.07 seconds
Started Jul 01 10:48:11 AM PDT 24
Finished Jul 01 10:48:17 AM PDT 24
Peak memory 201432 kb
Host smart-a5cc2319-d57c-46e6-a282-a4303f57b3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974474042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.974474042
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.2603718337
Short name T373
Test name
Test status
Simulation time 177091368306 ps
CPU time 431.65 seconds
Started Jul 01 10:48:12 AM PDT 24
Finished Jul 01 10:55:24 AM PDT 24
Peak memory 201692 kb
Host smart-d532e7b3-67b4-4daa-b950-22694b822bfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603718337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.2603718337
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1161725278
Short name T380
Test name
Test status
Simulation time 54779953146 ps
CPU time 38.58 seconds
Started Jul 01 10:48:23 AM PDT 24
Finished Jul 01 10:49:04 AM PDT 24
Peak memory 201664 kb
Host smart-a1d18a3e-1df1-4c3d-ab37-3b1442dac0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161725278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.1161725278
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2589754870
Short name T755
Test name
Test status
Simulation time 3442759401 ps
CPU time 2.94 seconds
Started Jul 01 10:47:56 AM PDT 24
Finished Jul 01 10:48:01 AM PDT 24
Peak memory 201444 kb
Host smart-191f91be-f60a-4000-ab29-96be145e71e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589754870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.2589754870
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.2612233282
Short name T37
Test name
Test status
Simulation time 3141757819 ps
CPU time 2.35 seconds
Started Jul 01 10:48:18 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201476 kb
Host smart-0cba0308-35f9-4ba4-8950-96385991fdb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612233282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.2612233282
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.517062516
Short name T712
Test name
Test status
Simulation time 2623285396 ps
CPU time 3.43 seconds
Started Jul 01 10:48:01 AM PDT 24
Finished Jul 01 10:48:06 AM PDT 24
Peak memory 201472 kb
Host smart-7878c0c7-e1f2-4bf9-97de-0f49d51dce4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517062516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.517062516
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3111112010
Short name T475
Test name
Test status
Simulation time 2553082412 ps
CPU time 1.2 seconds
Started Jul 01 10:47:57 AM PDT 24
Finished Jul 01 10:48:00 AM PDT 24
Peak memory 201476 kb
Host smart-8021dc68-a43e-4b0e-aa32-a5ea979425c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111112010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3111112010
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3924741974
Short name T551
Test name
Test status
Simulation time 2087260648 ps
CPU time 1.8 seconds
Started Jul 01 10:48:12 AM PDT 24
Finished Jul 01 10:48:15 AM PDT 24
Peak memory 201352 kb
Host smart-928987e1-edd7-48f1-8de2-29b98b450a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924741974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.3924741974
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.743214450
Short name T673
Test name
Test status
Simulation time 2547185773 ps
CPU time 1.79 seconds
Started Jul 01 10:48:19 AM PDT 24
Finished Jul 01 10:48:21 AM PDT 24
Peak memory 201428 kb
Host smart-93c84534-1fe8-426c-ae19-63882c71aa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743214450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.743214450
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.3548650233
Short name T450
Test name
Test status
Simulation time 2112804021 ps
CPU time 4.54 seconds
Started Jul 01 10:48:13 AM PDT 24
Finished Jul 01 10:48:18 AM PDT 24
Peak memory 201340 kb
Host smart-4ddf7c12-7730-4844-97e1-34f82492edf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548650233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3548650233
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.3755185107
Short name T670
Test name
Test status
Simulation time 6789146950 ps
CPU time 4.77 seconds
Started Jul 01 10:47:58 AM PDT 24
Finished Jul 01 10:48:04 AM PDT 24
Peak memory 201284 kb
Host smart-2e005b0f-14ef-4e99-93ec-1d009a87e7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755185107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.3755185107
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1653325951
Short name T503
Test name
Test status
Simulation time 3410617298 ps
CPU time 3.61 seconds
Started Jul 01 10:48:16 AM PDT 24
Finished Jul 01 10:48:20 AM PDT 24
Peak memory 201488 kb
Host smart-0df935e5-1b27-45f6-9d05-917d2ae98e28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653325951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.1653325951
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1120223454
Short name T356
Test name
Test status
Simulation time 64435809948 ps
CPU time 89.04 seconds
Started Jul 01 10:49:28 AM PDT 24
Finished Jul 01 10:50:58 AM PDT 24
Peak memory 201884 kb
Host smart-99e561d1-4c0f-450e-8661-14b34e515565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120223454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.1120223454
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1024108135
Short name T378
Test name
Test status
Simulation time 45925196306 ps
CPU time 30.75 seconds
Started Jul 01 10:49:28 AM PDT 24
Finished Jul 01 10:50:00 AM PDT 24
Peak memory 201776 kb
Host smart-b3b571fd-d6b0-43ba-b7f3-bd48167eda73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024108135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.1024108135
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1968002213
Short name T100
Test name
Test status
Simulation time 35579963514 ps
CPU time 91.75 seconds
Started Jul 01 10:49:26 AM PDT 24
Finished Jul 01 10:50:58 AM PDT 24
Peak memory 201684 kb
Host smart-ad5b04e3-db1e-4b6e-b745-f6ae1dbb8bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968002213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.1968002213
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1251722995
Short name T354
Test name
Test status
Simulation time 83686351752 ps
CPU time 55.24 seconds
Started Jul 01 10:49:43 AM PDT 24
Finished Jul 01 10:50:40 AM PDT 24
Peak memory 201660 kb
Host smart-51158b8f-c870-4fcb-88c4-56bbe3d928b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251722995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.1251722995
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3486955321
Short name T254
Test name
Test status
Simulation time 40277176444 ps
CPU time 20.84 seconds
Started Jul 01 10:49:55 AM PDT 24
Finished Jul 01 10:50:17 AM PDT 24
Peak memory 201884 kb
Host smart-9f22aa10-ea36-4532-9a44-ee382bd1fdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486955321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.3486955321
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2180778319
Short name T340
Test name
Test status
Simulation time 188283546264 ps
CPU time 130.44 seconds
Started Jul 01 10:49:26 AM PDT 24
Finished Jul 01 10:51:37 AM PDT 24
Peak memory 201984 kb
Host smart-b9454cb6-7d0f-4986-89a2-8cb71ad49594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180778319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.2180778319
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3355069593
Short name T358
Test name
Test status
Simulation time 40772390640 ps
CPU time 56.4 seconds
Started Jul 01 10:49:26 AM PDT 24
Finished Jul 01 10:50:23 AM PDT 24
Peak memory 201840 kb
Host smart-a3a99164-f21d-42e2-9c78-ea39513080fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355069593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.3355069593
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1495612793
Short name T361
Test name
Test status
Simulation time 107103586922 ps
CPU time 54.13 seconds
Started Jul 01 10:49:46 AM PDT 24
Finished Jul 01 10:50:42 AM PDT 24
Peak memory 201764 kb
Host smart-352540a6-1455-4787-ad7b-2a345183a49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495612793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.1495612793
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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