Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2003

1

T1

8

T2

2

T3

6

auto[1]

644

1

T1

8

T2

6

T3

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1985

1

T1

8

T2

4

T3

8

auto[1]

662

1

T1

8

T2

4

T3

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1988

1

T1

16

T2

2

T3

4

auto[1]

659

1

T2

6

T3

10

T22

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2057

1

T1

16

T2

6

T3

7

auto[1]

590

1

T2

2

T3

7

T15

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2418

1

T1

16

T2

8

T3

14

auto[1]

229

1

T12

1

T36

7

T66

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2420

1

T1

16

T2

8

T3

14

auto[1]

227

1

T12

1

T68

1

T37

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2445

1

T1

8

T2

8

T3

14

auto[1]

202

1

T1

8

T9

4

T12

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2390

1

T1

16

T2

8

T3

14

auto[1]

257

1

T12

1

T68

9

T87

7

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425

1

T1

16

T2

8

T3

14

auto[1]

222

1

T9

8

T12

2

T68

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2073

1

T1

12

T2

4

T3

11

auto[1]

574

1

T1

4

T2

4

T3

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

938

1

T2

8

T3

14

T15

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

63

1

T36

7

T66

2

T229

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

68

1

T9

2

T231

2

T243

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T230

3

T91

6

T244

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

68

1

T87

7

T37

1

T230

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T68

2

T315

6

T196

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T79

1

T196

5

T322

13

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T68

2

T131

4

T244

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

84

1

T1

8

T12

3

T38

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T244

4

T323

3

T319

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T9

2

T237

1

T242

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T324

4

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T325

2

T326

1

T322

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T196

3

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T37

2

T229

2

T88

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T196

1

T321

6

T327

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

12

1

T315

2

T328

3

T329

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T325

1

T330

5

T317

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T88

5

T231

2

T331

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T12

1

T191

3

T319

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T329

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

13

1

T77

7

T332

2

T333

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T334

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T186

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

7

1

T242

2

T335

1

T334

4

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

124

1

T22

11

T9

2

T35

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

84

1

T231

3

T242

12

T315

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T2

2

T23

4

T229

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

123

1

T36

7

T89

2

T91

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

44

1

T3

4

T282

2

T237

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

63

1

T22

6

T39

9

T232

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

49

1

T23

4

T336

3

T240

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

175

1

T39

13

T23

13

T53

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

59

1

T3

4

T74

7

T176

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T12

1

T89

3

T191

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T35

1

T229

2

T230

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T66

2

T35

1

T177

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T37

2

T71

1

T245

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T2

2

T55

3

T127

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T55

3

T74

2

T316

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

177

1

T8

2

T55

11

T68

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

72

1

T1

4

T12

3

T35

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T127

5

T234

6

T337

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T1

4

T312

2

T338

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T312

7

T71

2

T242

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T23

4

T245

1

T339

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T15

2

T74

2

T320

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T127

2

T241

2

T96

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

66

1

T8

1

T230

3

T231

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T2

4

T22

1

T35

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

21

1

T3

3

T37

1

T243

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T178

3

T97

1

T340

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T3

3

T9

2

T229

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T55

3

T238

1

T336

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T318

1

T99

2

T224

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T178

2

T232

2

T311

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded