Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T7

11

T8

7

T57

23

auto[1]

1154

1

T7

9

T8

13

T57

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T7

5

T8

6

T57

12

from_0to1

561

1

T7

6

T8

5

T57

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1169

1

T7

9

T8

9

T57

21

auto[1]

1062

1

T7

11

T8

11

T57

19

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T7

10

T8

11

T57

19

auto[1]

1109

1

T7

10

T8

9

T57

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T7

1

T8

1

T30

1

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T57

2

T30

1

T41

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T7

1

T8

1

T57

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T8

1

T57

5

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

85

1

T7

1

T8

1

T57

2

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T7

1

T57

3

T35

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T7

1

T8

1

T57

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T7

2

T57

1

T30

2

auto[1]

from_1to0

auto[0]

auto[0]

84

1

T7

1

T57

1

T288

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T7

1

T8

1

T57

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T7

1

T8

2

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T30

2

T61

1

T35

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T57

2

T30

1

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T7

1

T8

1

T57

2

auto[1]

from_0to1

auto[1]

auto[0]

83

1

T8

1

T57

1

T41

4

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T8

1

T57

1

T35

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T7

13

T8

11

T57

22

auto[1]

1079

1

T7

7

T8

9

T57

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

541

1

T7

5

T8

6

T57

9

from_0to1

544

1

T7

5

T8

7

T57

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T7

9

T8

10

T57

15

auto[1]

1124

1

T7

11

T8

10

T57

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T7

6

T8

8

T57

12

auto[1]

1144

1

T7

14

T8

12

T57

28

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T7

1

T8

3

T41

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T7

1

T8

1

T57

2

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T41

1

T63

1

T280

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T7

2

T57

2

T30

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T57

1

T30

1

T63

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T7

1

T8

2

T30

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T30

1

T41

5

T35

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T7

1

T8

3

T57

5

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T57

2

T30

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T30

1

T35

1

T280

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T8

1

T57

1

T41

2

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T7

1

T8

1

T57

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T41

1

T61

1

T63

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T7

1

T57

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T7

2

T8

1

T57

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T8

1

T57

1

T41

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T7

10

T8

11

T57

29

auto[1]

1079

1

T7

10

T8

9

T57

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

556

1

T7

5

T8

4

T57

13

from_0to1

559

1

T7

4

T8

4

T57

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T7

7

T8

9

T57

18

auto[1]

1127

1

T7

13

T8

11

T57

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T7

11

T8

10

T57

13

auto[1]

1093

1

T7

9

T8

10

T57

27

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T57

1

T30

2

T41

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T57

4

T41

1

T35

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T7

2

T8

1

T57

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T7

2

T8

1

T57

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T30

1

T63

2

T288

2

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T7

1

T8

2

T57

3

auto[0]

from_0to1

auto[1]

auto[0]

95

1

T7

1

T57

3

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T7

1

T57

4

T30

2

auto[1]

from_1to0

auto[0]

auto[0]

84

1

T57

2

T30

1

T41

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T57

1

T30

1

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T7

1

T8

2

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T57

1

T41

2

T63

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T8

1

T57

1

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T41

2

T61

1

T63

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T8

1

T41

2

T35

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T7

1

T57

2

T41

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T7

11

T8

13

T57

17

auto[1]

1103

1

T7

9

T8

7

T57

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

531

1

T7

6

T8

7

T57

9

from_0to1

521

1

T7

6

T8

6

T57

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T7

10

T8

10

T57

19

auto[1]

1140

1

T7

10

T8

10

T57

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1102

1

T7

9

T8

13

T57

18

auto[1]

1129

1

T7

11

T8

7

T57

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T8

1

T41

2

T61

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T7

2

T8

1

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T8

1

T57

4

T30

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T7

1

T8

1

T30

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T7

1

T8

1

T57

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T7

1

T8

2

T41

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T7

1

T8

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

79

1

T8

1

T57

1

T30

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T8

1

T57

2

T30

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T7

1

T57

1

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T7

1

T8

1

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T7

1

T8

1

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T8

1

T30

1

T41

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T57

3

T30

1

T41

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T7

2

T57

1

T30

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T7

1

T57

3

T30

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T7

8

T8

10

T57

19

auto[1]

1150

1

T7

12

T8

10

T57

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

521

1

T7

5

T8

5

T57

8

from_0to1

512

1

T7

4

T8

6

T57

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T7

10

T8

12

T57

23

auto[1]

1084

1

T7

10

T8

8

T57

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T7

10

T8

9

T57

23

auto[1]

1084

1

T7

10

T8

11

T57

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T7

1

T57

1

T30

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T7

1

T30

1

T35

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T8

1

T57

1

T41

3

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T7

1

T8

1

T30

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T8

2

T57

2

T30

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T57

1

T41

1

T35

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T8

1

T57

1

T41

3

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T30

1

T41

2

T35

3

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T7

1

T57

1

T61

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T8

2

T57

3

T30

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T7

1

T8

1

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T57

1

T30

1

T41

2

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T8

1

T57

2

T30

2

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T7

1

T8

1

T57

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T7

1

T57

2

T63

3

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T7

2

T8

1

T41

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1102

1

T7

10

T8

9

T57

24

auto[1]

1129

1

T7

10

T8

11

T57

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

559

1

T7

6

T8

7

T57

9

from_0to1

543

1

T7

6

T8

6

T57

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T7

10

T8

14

T57

24

auto[1]

1097

1

T7

10

T8

6

T57

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T7

9

T8

9

T57

21

auto[1]

1103

1

T7

11

T8

11

T57

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T7

2

T8

2

T57

3

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T8

2

T35

1

T288

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T7

1

T57

1

T41

2

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T7

1

T8

1

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T57

2

T30

1

T41

2

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T7

1

T8

1

T57

2

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T7

1

T8

1

T57

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T7

1

T8

1

T30

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T8

1

T41

1

T35

2

auto[1]

from_1to0

auto[0]

auto[1]

86

1

T7

1

T8

1

T57

2

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T57

1

T30

2

T41

2

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T7

1

T57

1

T41

3

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T7

1

T57

2

T63

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T8

1

T30

1

T63

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T8

1

T41

1

T80

2

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T7

2

T8

1

T57

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T7

10

T8

9

T57

18

auto[1]

1104

1

T7

10

T8

11

T57

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T7

5

T8

3

T57

9

from_0to1

527

1

T7

5

T8

4

T57

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1085

1

T7

10

T8

9

T57

23

auto[1]

1146

1

T7

10

T8

11

T57

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T7

9

T8

10

T57

17

auto[1]

1104

1

T7

11

T8

10

T57

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T57

1

T30

1

T41

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T8

1

T30

1

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T7

2

T41

1

T63

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T7

1

T8

1

T57

3

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T61

1

T63

1

T35

2

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T7

1

T8

1

T57

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T7

1

T57

2

T63

2

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T7

1

T57

1

T41

2

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T57

2

T41

3

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T7

1

T57

1

T30

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T7

1

T57

1

T30

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T8

1

T57

1

T41

4

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T7

1

T57

1

T30

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T7

1

T57

3

T30

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T8

1

T41

1

T63

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T8

2

T57

1

T30

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T7

5

T8

8

T57

17

auto[1]

1100

1

T7

15

T8

12

T57

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

541

1

T7

3

T8

4

T57

9

from_0to1

535

1

T7

4

T8

5

T57

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T7

4

T8

10

T57

20

auto[1]

1126

1

T7

16

T8

10

T57

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T7

16

T8

7

T57

20

auto[1]

1152

1

T7

4

T8

13

T57

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T57

1

T41

1

T61

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T8

1

T57

1

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T30

1

T35

1

T288

2

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T57

2

T61

1

T63

2

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T8

1

T57

2

T30

1

auto[0]

from_0to1

auto[0]

auto[1]

47

1

T35

1

T288

1

T280

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T8

1

T57

2

T30

1

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T57

1

T41

3

T280

2

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T7

1

T8

1

T41

4

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T8

2

T57

2

T30

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T57

1

T41

4

T61

2

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T7

2

T57

2

T30

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T41

3

T352

1

T81

5

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T7

1

T8

1

T57

2

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T7

3

T30

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T8

2

T57

1

T41

1