Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155227	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120658

1

T1

313

T4

19

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141970	1			T1	259		T4	22		T5	2
values[0x0]	66375	1			T1	297		T4	14		T13	2
values[0x1]	67540	1			T1	297		T4	9		T2	45

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149985

1

T1

399

T4

22

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1255	1			T1	4		T3	1		T15	1
valid_sources[0x01]	1790	1			T1	3		T3	2		T15	2
valid_sources[0x02]	842	1			T1	5		T22	5		T8	6
valid_sources[0x03]	794	1			T1	6		T15	3		T22	2
valid_sources[0x04]	913	1			T1	1		T2	7		T22	6
valid_sources[0x05]	1043	1			T1	1		T2	5		T3	9
valid_sources[0x06]	823	1			T1	1		T4	2		T3	2
valid_sources[0x07]	970	1			T1	5		T4	13		T6	2
valid_sources[0x08]	1285	1			T1	5		T4	2		T7	5
valid_sources[0x09]	1052	1			T1	4		T15	1		T22	3
valid_sources[0x0a]	807	1			T1	5		T2	7		T15	2
valid_sources[0x0b]	1083	1			T1	2		T3	7		T15	2
valid_sources[0x0c]	1632	1			T1	3		T3	1		T15	2
valid_sources[0x0d]	1340	1			T1	2		T4	1		T2	7
valid_sources[0x0e]	1123	1			T1	4		T22	2		T8	7
valid_sources[0x0f]	1091	1			T1	4		T2	5		T3	2
valid_sources[0x10]	1172	1			T1	4		T2	7		T3	6
valid_sources[0x11]	1124	1			T2	2		T3	2		T15	2
valid_sources[0x12]	948	1			T1	5		T3	5		T15	1
valid_sources[0x13]	831	1			T1	3		T15	1		T22	2
valid_sources[0x14]	1167	1			T1	6		T3	1		T22	2
valid_sources[0x15]	892	1			T1	5		T2	1		T3	3
valid_sources[0x16]	1221	1			T1	7		T2	5		T3	1
valid_sources[0x17]	961	1			T1	1		T3	6		T22	1
valid_sources[0x18]	810	1			T1	4		T2	3		T22	7
valid_sources[0x19]	826	1			T1	7		T2	1		T3	2
valid_sources[0x1a]	1118	1			T1	5		T3	3		T15	1
valid_sources[0x1b]	965	1			T1	1		T4	1		T3	1
valid_sources[0x1c]	898	1			T1	3		T2	1		T7	10
valid_sources[0x1d]	984	1			T1	8		T3	4		T22	5
valid_sources[0x1e]	1258	1			T1	5		T2	17		T3	1
valid_sources[0x1f]	912	1			T1	2		T22	4		T8	2
valid_sources[0x20]	1164	1			T1	1		T2	3		T3	3
valid_sources[0x21]	895	1			T1	1		T3	10		T15	2
valid_sources[0x22]	933	1			T1	4		T4	1		T15	2
valid_sources[0x23]	948	1			T1	3		T3	1		T15	1
valid_sources[0x24]	851	1			T1	4		T2	4		T3	13
valid_sources[0x25]	1018	1			T1	5		T15	1		T22	5
valid_sources[0x26]	998	1			T1	1		T3	2		T15	1
valid_sources[0x27]	1044	1			T1	3		T3	4		T15	1
valid_sources[0x28]	875	1			T1	7		T15	1		T22	8
valid_sources[0x29]	1061	1			T1	1		T2	7		T15	2
valid_sources[0x2a]	765	1			T1	8		T3	2		T15	1
valid_sources[0x2b]	754	1			T1	2		T2	2		T3	3
valid_sources[0x2c]	881	1			T1	6		T15	1		T22	2
valid_sources[0x2d]	989	1			T1	5		T2	6		T15	3
valid_sources[0x2e]	1241	1			T1	3		T3	11		T7	268
valid_sources[0x2f]	998	1			T1	5		T14	2		T7	20
valid_sources[0x30]	984	1			T22	6		T8	1		T39	1
valid_sources[0x31]	979	1			T1	2		T4	4		T2	1
valid_sources[0x32]	952	1			T1	5		T15	1		T22	10
valid_sources[0x33]	1124	1			T1	1		T3	1		T7	87
valid_sources[0x34]	843	1			T1	4		T2	2		T3	2
valid_sources[0x35]	1123	1			T1	8		T15	2		T22	4
valid_sources[0x36]	2420	1			T1	5		T2	2		T15	4
valid_sources[0x37]	1320	1			T1	3		T15	3		T39	2
valid_sources[0x38]	954	1			T1	1		T15	3		T22	7
valid_sources[0x39]	1418	1			T1	3		T15	4		T8	8
valid_sources[0x3a]	725	1			T1	2		T3	2		T15	1
valid_sources[0x3b]	1519	1			T1	3		T3	4		T15	1
valid_sources[0x3c]	997	1			T1	5		T3	4		T22	4
valid_sources[0x3d]	823	1			T1	5		T3	6		T6	3
valid_sources[0x3e]	1214	1			T1	4		T14	1		T15	3
valid_sources[0x3f]	1099	1			T1	2		T3	9		T6	1
valid_sources[0x40]	1026	1			T1	8		T14	1		T15	3
valid_sources[0x41]	870	1			T1	6		T2	7		T3	4
valid_sources[0x42]	1798	1			T1	6		T2	2		T3	11
valid_sources[0x43]	972	1			T1	3		T3	2		T15	4
valid_sources[0x44]	980	1			T1	2		T4	3		T2	3
valid_sources[0x45]	1137	1			T1	7		T15	1		T22	2
valid_sources[0x46]	1435	1			T1	2		T22	4		T8	2
valid_sources[0x47]	925	1			T1	3		T15	4		T22	4
valid_sources[0x48]	1826	1			T1	1		T2	4		T3	4
valid_sources[0x49]	1031	1			T1	7		T3	1		T15	3
valid_sources[0x4a]	1234	1			T1	5		T15	2		T22	3
valid_sources[0x4b]	1864	1			T1	3		T2	2		T3	1
valid_sources[0x4c]	1429	1			T1	1		T2	4		T3	2
valid_sources[0x4d]	2144	1			T1	3		T3	1		T15	1
valid_sources[0x4e]	1046	1			T1	4		T2	20		T3	1
valid_sources[0x4f]	1004	1			T1	2		T2	9		T15	1
valid_sources[0x50]	969	1			T1	7		T4	1		T15	4
valid_sources[0x51]	841	1			T1	3		T2	15		T3	5
valid_sources[0x52]	712	1			T1	2		T3	3		T22	3
valid_sources[0x53]	1128	1			T1	1		T15	4		T22	2
valid_sources[0x54]	957	1			T1	2		T22	9		T8	5
valid_sources[0x55]	775	1			T1	1		T15	1		T22	2
valid_sources[0x56]	1778	1			T1	1		T15	5		T22	7
valid_sources[0x57]	797	1			T1	2		T15	3		T22	4
valid_sources[0x58]	1050	1			T1	3		T15	1		T22	4
valid_sources[0x59]	808	1			T1	2		T3	7		T15	1
valid_sources[0x5a]	1149	1			T1	2		T7	15		T15	1
valid_sources[0x5b]	928	1			T1	7		T15	1		T22	2
valid_sources[0x5c]	860	1			T1	1		T3	1		T15	3
valid_sources[0x5d]	1581	1			T1	7		T3	4		T15	1
valid_sources[0x5e]	1260	1			T1	4		T22	4		T8	8
valid_sources[0x5f]	857	1			T1	4		T15	1		T22	5
valid_sources[0x60]	768	1			T1	3		T22	2		T8	1
valid_sources[0x61]	939	1			T6	2		T22	5		T103	1
valid_sources[0x62]	2881	1			T1	4		T3	9		T22	1
valid_sources[0x63]	842	1			T1	1		T15	2		T22	1
valid_sources[0x64]	987	1			T1	2		T22	3		T8	6
valid_sources[0x65]	908	1			T1	4		T3	4		T15	3
valid_sources[0x66]	1219	1			T1	5		T2	6		T15	1
valid_sources[0x67]	843	1			T1	5		T22	1		T8	10
valid_sources[0x68]	998	1			T1	6		T22	4		T8	7
valid_sources[0x69]	1033	1			T1	5		T22	7		T8	11
valid_sources[0x6a]	1271	1			T1	5		T2	17		T3	5
valid_sources[0x6b]	891	1			T1	5		T3	1		T15	1
valid_sources[0x6c]	1010	1			T1	4		T2	4		T3	3
valid_sources[0x6d]	1035	1			T1	3		T3	3		T15	1
valid_sources[0x6e]	928	1			T1	5		T15	2		T22	4
valid_sources[0x6f]	1541	1			T1	1		T2	3		T3	6
valid_sources[0x70]	1760	1			T1	5		T3	3		T15	3
valid_sources[0x71]	873	1			T1	1		T7	9		T15	1
valid_sources[0x72]	1223	1			T1	1		T3	3		T6	1
valid_sources[0x73]	888	1			T1	4		T2	3		T22	4
valid_sources[0x74]	1202	1			T1	2		T15	3		T22	6
valid_sources[0x75]	1122	1			T1	4		T2	2		T3	5
valid_sources[0x76]	1865	1			T1	4		T3	3		T22	3
valid_sources[0x77]	994	1			T1	5		T3	5		T15	3
valid_sources[0x78]	1769	1			T1	5		T4	1		T15	2
valid_sources[0x79]	842	1			T1	5		T2	3		T15	1
valid_sources[0x7a]	1615	1			T1	4		T2	3		T15	3
valid_sources[0x7b]	1682	1			T1	6		T4	5		T22	2
valid_sources[0x7c]	935	1			T1	3		T22	3		T39	4
valid_sources[0x7d]	770	1			T1	3		T3	2		T15	2
valid_sources[0x7e]	1035	1			T1	3		T5	2		T2	11
valid_sources[0x7f]	976	1			T1	1		T2	9		T15	2
valid_sources[0x80]	940	1			T1	3		T15	4		T22	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64783

1

T1

128

T4

8

T5

2

values[0x0]

all_enables

biggest_size

32468

1

T1

110

T4

7

T2

12

values[0x1]

all_enables

biggest_size

23407

1

T1

75

T4

4

T2

19