Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T22,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T7,T22,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T22,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T22,T23
1	0	Covered	T1,T4,T5
1	1	Covered	T7,T22,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T22,T23
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T22,T23
0	1	Covered	T7,T22,T23
1	0	Covered	T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T22,T23
1	-	Covered	T7,T22,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T22,T23
DetectSt	168	Covered	T7,T22,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T22,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T22,T23
DebounceSt->IdleSt	163	Covered	T42,T43,T44
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T22,T23
IdleSt->DebounceSt	148	Covered	T7,T22,T23
StableSt->IdleSt	206	Covered	T7,T22,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T22,T23
0	1	Covered	T7,T22,T23
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T22,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T22,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T22,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T43,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T22,T23
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T22,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T22,T23
StableSt	-	-	-	-	-	-	0	Covered	T7,T22,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	241	0	0
CntIncr_A	8393152	176158	0	0
CntNoWrap_A	8393152	7743325	0	0
DetectStDropOut_A	8393152	0	0	0
DetectedOut_A	8393152	756	0	0
DetectedPulseOut_A	8393152	106	0	0
DisabledIdleSt_A	8393152	7561631	0	0
DisabledNoDetection_A	8393152	7563987	0	0
EnterDebounceSt_A	8393152	140	0	0
EnterDetectSt_A	8393152	106	0	0
EnterStableSt_A	8393152	106	0	0
PulseIsPulse_A	8393152	106	0	0
StayInStableSt	8393152	650	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8393152	6843	0	0
gen_low_level_sva.LowLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	104	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	241	0	0
T7	6580	2	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	6	0	0
T23	0	2	0	0
T24	5079	0	0	0
T33	0	6	0	0
T41	0	4	0	0
T42	0	5	0	0
T43	0	3	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	176158	0	0
T7	6580	10	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	198	0	0
T23	0	35	0	0
T24	5079	0	0	0
T33	0	261	0	0
T41	0	200	0	0
T42	0	198	0	0
T43	0	53	0	0
T44	0	107	0	0
T45	0	23623	0	0
T46	0	88	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743325	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1484	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	756	0	0
T7	6580	2	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	26	0	0
T23	0	2	0	0
T24	5079	0	0	0
T33	0	6	0	0
T41	0	15	0	0
T42	0	7	0	0
T43	0	10	0	0
T44	0	9	0	0
T45	0	7	0	0
T46	0	4	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	106	0	0
T7	6580	1	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	3	0	0
T23	0	1	0	0
T24	5079	0	0	0
T33	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7561631	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1430	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7563987	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1443	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	140	0	0
T7	6580	1	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	3	0	0
T23	0	1	0	0
T24	5079	0	0	0
T33	0	4	0	0
T41	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	106	0	0
T7	6580	1	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	3	0	0
T23	0	1	0	0
T24	5079	0	0	0
T33	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	106	0	0
T7	6580	1	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	3	0	0
T23	0	1	0	0
T24	5079	0	0	0
T33	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	106	0	0
T7	6580	1	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	3	0	0
T23	0	1	0	0
T24	5079	0	0	0
T33	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	650	0	0
T7	6580	1	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	23	0	0
T23	0	1	0	0
T24	5079	0	0	0
T33	0	4	0	0
T41	0	13	0	0
T42	0	5	0	0
T43	0	9	0	0
T44	0	8	0	0
T45	0	6	0	0
T46	0	3	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6843	0	0
T1	15395	25	0	0
T2	13478	7	0	0
T3	17732	12	0	0
T4	484	7	0	0
T5	422	1	0	0
T6	2542	7	0	0
T7	6580	25	0	0
T13	695	0	0	0
T14	491	7	0	0
T15	4614	9	0	0
T22	0	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	104	0	0
T7	6580	1	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	3	0	0
T23	0	1	0	0
T24	5079	0	0	0
T33	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T20,T21,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T20,T21
1	0	Covered	T1,T4,T5
1	1	Covered	T8,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T41
0	1	Covered	T72,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T41
0	1	Unreachable
1	0	Covered	T20,T21,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T20,T21
DetectSt	168	Covered	T20,T21,T41
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T20,T21,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T21,T41
DebounceSt->IdleSt	163	Covered	T8,T56,T72
DetectSt->IdleSt	186	Covered	T72,T84,T85
DetectSt->StableSt	191	Covered	T20,T21,T41
IdleSt->DebounceSt	148	Covered	T8,T20,T21
StableSt->IdleSt	206	Covered	T20,T21,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T20,T21
0	1	Covered	T8,T20,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T41
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T21,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T56,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T72,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T20,T21,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T21,T41
StableSt	-	-	-	-	-	-	0	Covered	T20,T21,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	191	0	0
CntIncr_A	8393152	448726	0	0
CntNoWrap_A	8393152	7743375	0	0
DetectStDropOut_A	8393152	12	0	0
DetectedOut_A	8393152	556707	0	0
DetectedPulseOut_A	8393152	59	0	0
DisabledIdleSt_A	8393152	5222570	0	0
DisabledNoDetection_A	8393152	5224971	0	0
EnterDebounceSt_A	8393152	121	0	0
EnterDetectSt_A	8393152	71	0	0
EnterStableSt_A	8393152	59	0	0
PulseIsPulse_A	8393152	59	0	0
StayInStableSt	8393152	556648	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8393152	6843	0	0
gen_low_level_sva.LowLevelEvent_A	8393152	7745969	0	0
gen_sticky_sva.StableStDropOut_A	8393152	745569	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	191	0	0
T8	15549	3	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	4	0	0
T21	0	2	0	0
T24	5079	0	0	0
T41	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T70	0	4	0	0
T71	0	2	0	0
T72	0	7	0	0
T73	408	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	448726	0	0
T8	15549	180	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	122	0	0
T21	0	30	0	0
T24	5079	0	0	0
T41	0	100	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	95	0	0
T55	0	27446	0	0
T56	0	156	0	0
T70	0	140	0	0
T71	0	24	0	0
T72	0	148	0	0
T73	408	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743375	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	12	0	0
T72	1536	2	0	0
T80	14290	0	0	0
T84	0	3	0	0
T85	0	1	0	0
T109	0	3	0	0
T110	0	3	0	0
T111	618	0	0	0
T112	7332	0	0	0
T113	522	0	0	0
T114	416	0	0	0
T115	526	0	0	0
T116	7523	0	0	0
T117	725	0	0	0
T118	441	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	556707	0	0
T20	1759	716	0	0
T21	1874	188	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	2	0	0
T52	0	128	0	0
T55	0	143128	0	0
T57	5987	0	0	0
T70	0	88	0	0
T71	0	167	0	0
T72	0	1	0	0
T80	0	332	0	0
T106	0	347	0	0
T107	422	0	0	0
T108	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	59	0	0
T20	1759	2	0	0
T21	1874	1	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	5987	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T80	0	1	0	0
T106	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	5222570	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	5224971	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	121	0	0
T8	15549	3	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T24	5079	0	0	0
T41	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	4	0	0
T73	408	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	71	0	0
T20	1759	2	0	0
T21	1874	1	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	5987	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	3	0	0
T80	0	1	0	0
T106	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	59	0	0
T20	1759	2	0	0
T21	1874	1	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	5987	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T80	0	1	0	0
T106	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	59	0	0
T20	1759	2	0	0
T21	1874	1	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T57	5987	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T80	0	1	0	0
T106	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	556648	0	0
T20	1759	714	0	0
T21	1874	187	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	127	0	0
T55	0	143127	0	0
T57	5987	0	0	0
T70	0	86	0	0
T71	0	166	0	0
T80	0	331	0	0
T81	0	280	0	0
T106	0	346	0	0
T107	422	0	0	0
T108	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6843	0	0
T1	15395	25	0	0
T2	13478	7	0	0
T3	17732	12	0	0
T4	484	7	0	0
T5	422	1	0	0
T6	2542	7	0	0
T7	6580	25	0	0
T13	695	0	0	0
T14	491	7	0	0
T15	4614	9	0	0
T22	0	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	745569	0	0
T20	1759	438	0	0
T21	1874	496	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	24	0	0
T52	0	55	0	0
T55	0	102	0	0
T57	5987	0	0	0
T70	0	76	0	0
T71	0	622	0	0
T72	0	96	0	0
T80	0	304	0	0
T106	0	74846	0	0
T107	422	0	0	0
T108	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T5,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T14
1	1	Covered	T4,T5,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T21,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T20,T21
1	0	Covered	T4,T5,T14
1	1	Covered	T8,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T41
0	1	Covered	T81,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T21,T41
0	1	Unreachable
1	0	Covered	T8,T21,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T20,T21
DetectSt	168	Covered	T8,T21,T41
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T21,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T21,T41
DebounceSt->IdleSt	163	Covered	T20,T80,T81
DetectSt->IdleSt	186	Covered	T81,T82,T83
DetectSt->StableSt	191	Covered	T8,T21,T41
IdleSt->DebounceSt	148	Covered	T8,T20,T21
StableSt->IdleSt	206	Covered	T8,T21,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T20,T21
0	1	Covered	T8,T20,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T21,T41
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T21,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T80,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T81,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T8,T21,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T21,T41
StableSt	-	-	-	-	-	-	0	Covered	T8,T21,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	219	0	0
CntIncr_A	8393152	566509	0	0
CntNoWrap_A	8393152	7743347	0	0
DetectStDropOut_A	8393152	24	0	0
DetectedOut_A	8393152	880228	0	0
DetectedPulseOut_A	8393152	49	0	0
DisabledIdleSt_A	8393152	5222570	0	0
DisabledNoDetection_A	8393152	5224971	0	0
EnterDebounceSt_A	8393152	147	0	0
EnterDetectSt_A	8393152	73	0	0
EnterStableSt_A	8393152	49	0	0
PulseIsPulse_A	8393152	49	0	0
StayInStableSt	8393152	880179	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_sticky_sva.StableStDropOut_A	8393152	453675	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	219	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	7	0	0
T21	0	2	0	0
T24	5079	0	0	0
T41	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T70	0	4	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	408	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	566509	0	0
T8	15549	33	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	371	0	0
T21	0	63	0	0
T24	5079	0	0	0
T41	0	57	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	48	0	0
T55	0	89	0	0
T56	0	72	0	0
T70	0	92	0	0
T71	0	94	0	0
T72	0	61	0	0
T73	408	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743347	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	24	0	0
T81	9538	4	0	0
T82	0	3	0	0
T83	0	3	0	0
T119	0	3	0	0
T120	0	5	0	0
T121	0	1	0	0
T122	0	4	0	0
T123	0	1	0	0
T124	504	0	0	0
T125	952	0	0	0
T126	427	0	0	0
T127	19019	0	0	0
T128	402	0	0	0
T129	818	0	0	0
T130	1569	0	0	0
T131	14270	0	0	0
T132	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	880228	0	0
T8	15549	136	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T21	0	536	0	0
T24	5079	0	0	0
T41	0	30	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	61	0	0
T55	0	533	0	0
T56	0	109	0	0
T70	0	124	0	0
T71	0	640	0	0
T72	0	215	0	0
T73	408	0	0	0
T104	0	331445	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	49	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T21	0	1	0	0
T24	5079	0	0	0
T41	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	408	0	0	0
T104	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	5222570	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	5224971	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	147	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	7	0	0
T21	0	1	0	0
T24	5079	0	0	0
T41	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	408	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	73	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T21	0	1	0	0
T24	5079	0	0	0
T41	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	408	0	0	0
T104	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	49	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T21	0	1	0	0
T24	5079	0	0	0
T41	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	408	0	0	0
T104	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	49	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T21	0	1	0	0
T24	5079	0	0	0
T41	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	408	0	0	0
T104	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	880179	0	0
T8	15549	135	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T21	0	535	0	0
T24	5079	0	0	0
T41	0	29	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	60	0	0
T55	0	532	0	0
T56	0	108	0	0
T70	0	122	0	0
T71	0	639	0	0
T72	0	214	0	0
T73	408	0	0	0
T104	0	331444	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	453675	0	0
T8	15549	205	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T21	0	118	0	0
T24	5079	0	0	0
T41	0	53	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	169	0	0
T55	0	170052	0	0
T56	0	117	0	0
T70	0	96	0	0
T71	0	87	0	0
T72	0	270	0	0
T73	408	0	0	0
T104	0	362	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T20,T21,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T20,T21
1	0	Covered	T1,T4,T5
1	1	Covered	T8,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T41
0	1	Covered	T56,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T41
0	1	Unreachable
1	0	Covered	T20,T21,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T20,T21
DetectSt	168	Covered	T20,T21,T41
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T20,T21,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T21,T41
DebounceSt->IdleSt	163	Covered	T8,T55,T56
DetectSt->IdleSt	186	Covered	T56,T80,T81
DetectSt->StableSt	191	Covered	T20,T21,T41
IdleSt->DebounceSt	148	Covered	T8,T20,T21
StableSt->IdleSt	206	Covered	T20,T21,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T20,T21
0	1	Covered	T8,T20,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T41
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T21,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T55,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T56,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T20,T21,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T21,T41
StableSt	-	-	-	-	-	-	0	Covered	T20,T21,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	192	0	0
CntIncr_A	8393152	76300	0	0
CntNoWrap_A	8393152	7743374	0	0
DetectStDropOut_A	8393152	14	0	0
DetectedOut_A	8393152	13137	0	0
DetectedPulseOut_A	8393152	61	0	0
DisabledIdleSt_A	8393152	5222570	0	0
DisabledNoDetection_A	8393152	5224971	0	0
EnterDebounceSt_A	8393152	118	0	0
EnterDetectSt_A	8393152	75	0	0
EnterStableSt_A	8393152	61	0	0
PulseIsPulse_A	8393152	61	0	0
StayInStableSt	8393152	13076	0	0
gen_high_event_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_sticky_sva.StableStDropOut_A	8393152	1740386	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	192	0	0
T8	15549	3	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	4	0	0
T21	0	2	0	0
T24	5079	0	0	0
T41	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	2	0	0
T55	0	4	0	0
T56	0	3	0	0
T70	0	4	0	0
T71	0	2	0	0
T72	0	4	0	0
T73	408	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	76300	0	0
T8	15549	189	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	186	0	0
T21	0	79	0	0
T24	5079	0	0	0
T41	0	77	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	45	0	0
T55	0	48	0	0
T56	0	200	0	0
T70	0	20	0	0
T71	0	45	0	0
T72	0	288	0	0
T73	408	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743374	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	14	0	0
T35	16707	0	0	0
T44	704	0	0	0
T56	1615	1	0	0
T63	506	0	0	0
T68	15634	0	0	0
T69	4866	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	0	3	0	0
T136	0	3	0	0
T137	0	1	0	0
T138	753	0	0	0
T139	429	0	0	0
T140	705	0	0	0
T141	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	13137	0	0
T20	1759	547	0	0
T21	1874	444	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	20	0	0
T52	0	100	0	0
T57	5987	0	0	0
T70	0	31	0	0
T71	0	278	0	0
T80	0	187	0	0
T104	0	321	0	0
T105	0	631	0	0
T106	0	97	0	0
T107	422	0	0	0
T108	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	61	0	0
T20	1759	2	0	0
T21	1874	1	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	1	0	0
T57	5987	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T80	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	5222570	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	5224971	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	118	0	0
T8	15549	3	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T20	0	2	0	0
T21	0	1	0	0
T24	5079	0	0	0
T41	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T52	0	1	0	0
T55	0	4	0	0
T56	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	4	0	0
T73	408	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	75	0	0
T20	1759	2	0	0
T21	1874	1	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	5987	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T80	0	2	0	0
T104	0	1	0	0
T105	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	61	0	0
T20	1759	2	0	0
T21	1874	1	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	1	0	0
T57	5987	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T80	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	61	0	0
T20	1759	2	0	0
T21	1874	1	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	1	0	0
T52	0	1	0	0
T57	5987	0	0	0
T70	0	2	0	0
T71	0	1	0	0
T80	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	13076	0	0
T20	1759	545	0	0
T21	1874	443	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	19	0	0
T52	0	99	0	0
T57	5987	0	0	0
T70	0	29	0	0
T71	0	277	0	0
T80	0	186	0	0
T104	0	320	0	0
T105	0	630	0	0
T106	0	96	0	0
T107	422	0	0	0
T108	422	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1740386	0	0
T20	1759	556	0	0
T21	1874	207	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	0	0	0
T40	5015	0	0	0
T41	0	46	0	0
T52	0	141	0	0
T57	5987	0	0	0
T70	0	274	0	0
T71	0	504	0	0
T80	0	246	0	0
T104	0	389706	0	0
T105	0	243	0	0
T106	0	75185	0	0
T107	422	0	0	0
T108	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T30,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T30,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T30,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T23,T30
1	0	Covered	T1,T4,T5
1	1	Covered	T8,T30,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T35
0	1	Covered	T8,T35,T71
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T30,T35
1	-	Covered	T8,T35,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T30,T35
DetectSt	168	Covered	T8,T30,T35
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T30,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T30,T35
DebounceSt->IdleSt	163	Covered	T75,T76
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T30,T35
IdleSt->DebounceSt	148	Covered	T8,T30,T35
StableSt->IdleSt	206	Covered	T8,T30,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T30,T35
0	1	Covered	T8,T30,T35
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T30,T35
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T30,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T30,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T30,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T30,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T35,T71
StableSt	-	-	-	-	-	-	0	Covered	T8,T30,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	70	0	0
CntIncr_A	8393152	1870	0	0
CntNoWrap_A	8393152	7743496	0	0
DetectStDropOut_A	8393152	0	0	0
DetectedOut_A	8393152	2755	0	0
DetectedPulseOut_A	8393152	34	0	0
DisabledIdleSt_A	8393152	7707366	0	0
DisabledNoDetection_A	8393152	7709715	0	0
EnterDebounceSt_A	8393152	36	0	0
EnterDetectSt_A	8393152	34	0	0
EnterStableSt_A	8393152	34	0	0
PulseIsPulse_A	8393152	34	0	0
StayInStableSt	8393152	2702	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	70	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	2	0	0
T35	0	4	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	4	0	0
T73	408	0	0	0
T80	0	4	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	4	0	0
T146	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1870	0	0
T8	15549	82	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	40	0	0
T35	0	48	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	127	0	0
T73	408	0	0	0
T80	0	188	0	0
T142	0	15	0	0
T143	0	51	0	0
T144	0	44	0	0
T145	0	127	0	0
T146	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743496	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2755	0	0
T8	15549	141	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	156	0	0
T35	0	121	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	58	0	0
T73	408	0	0	0
T80	0	78	0	0
T142	0	110	0	0
T143	0	240	0	0
T144	0	59	0	0
T145	0	37	0	0
T146	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	34	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T35	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	2	0	0
T73	408	0	0	0
T80	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7707366	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7709715	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	36	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T35	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	2	0	0
T73	408	0	0	0
T80	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	34	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T35	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	2	0	0
T73	408	0	0	0
T80	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	34	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T35	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	2	0	0
T73	408	0	0	0
T80	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	34	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T35	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	2	0	0
T73	408	0	0	0
T80	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2702	0	0
T8	15549	140	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	154	0	0
T35	0	118	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	55	0	0
T73	408	0	0	0
T80	0	75	0	0
T142	0	108	0	0
T143	0	238	0	0
T144	0	57	0	0
T145	0	34	0	0
T146	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	15	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T35	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	1	0	0
T73	408	0	0	0
T80	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T145	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T23,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T23,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T23,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T30
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T23,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T23,T30
0	1	Covered	T78,T150,T146
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T23,T30
0	1	Covered	T6,T30,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T23,T30
1	-	Covered	T6,T30,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T23,T30
DetectSt	168	Covered	T6,T23,T30
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T23,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T23,T30
DebounceSt->IdleSt	163	Covered	T30,T151,T145
DetectSt->IdleSt	186	Covered	T78,T150,T146
DetectSt->StableSt	191	Covered	T6,T23,T30
IdleSt->DebounceSt	148	Covered	T6,T23,T30
StableSt->IdleSt	206	Covered	T6,T30,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T23,T30
0	1	Covered	T6,T23,T30
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T23,T30
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T23,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T23,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T151,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T23,T30
DetectSt	-	-	-	-	1	-	-	Covered	T78,T150,T146
DetectSt	-	-	-	-	0	1	-	Covered	T6,T23,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T30,T35
StableSt	-	-	-	-	-	-	0	Covered	T6,T23,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	138	0	0
CntIncr_A	8393152	3590	0	0
CntNoWrap_A	8393152	7743428	0	0
DetectStDropOut_A	8393152	5	0	0
DetectedOut_A	8393152	4493	0	0
DetectedPulseOut_A	8393152	59	0	0
DisabledIdleSt_A	8393152	7714578	0	0
DisabledNoDetection_A	8393152	7716919	0	0
EnterDebounceSt_A	8393152	75	0	0
EnterDetectSt_A	8393152	64	0	0
EnterStableSt_A	8393152	59	0	0
PulseIsPulse_A	8393152	59	0	0
StayInStableSt	8393152	4412	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8393152	2583	0	0
gen_low_level_sva.LowLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	138	0	0
T6	2542	2	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	2	0	0
T24	5079	0	0	0
T30	0	5	0	0
T31	0	2	0	0
T33	0	2	0	0
T35	0	4	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	4	0	0
T142	0	2	0	0
T152	0	4	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3590	0	0
T6	2542	33	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	81	0	0
T24	5079	0	0	0
T30	0	226	0	0
T31	0	29	0	0
T33	0	34	0	0
T35	0	48	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	138	0	0
T142	0	15	0	0
T152	0	42	0	0
T153	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743428	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	536	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	5	0	0
T71	75048	0	0	0
T72	1536	0	0	0
T78	964	1	0	0
T146	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	688	0	0	0
T157	407	0	0	0
T158	3427	0	0	0
T159	498	0	0	0
T160	744	0	0	0
T161	422	0	0	0
T162	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	4493	0	0
T6	2542	108	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	38	0	0
T24	5079	0	0	0
T30	0	182	0	0
T31	0	39	0	0
T33	0	85	0	0
T35	0	78	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	110	0	0
T142	0	45	0	0
T152	0	104	0	0
T153	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	59	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	1	0	0
T142	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7714578	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	210	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7716919	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	213	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	75	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	2	0	0
T142	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	64	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	2	0	0
T142	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	59	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	1	0	0
T142	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	59	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	1	0	0
T142	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	4412	0	0
T6	2542	107	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	36	0	0
T24	5079	0	0	0
T30	0	179	0	0
T31	0	38	0	0
T33	0	83	0	0
T35	0	76	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	109	0	0
T142	0	44	0	0
T152	0	102	0	0
T153	0	104	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2583	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	4	0	0
T5	422	2	0	0
T6	2542	8	0	0
T7	6580	26	0	0
T8	0	36	0	0
T13	695	0	0	0
T14	491	6	0	0
T15	4614	0	0	0
T22	36195	21	0	0
T49	0	6	0	0
T50	0	3	0	0
T102	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	37	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T35	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T71	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T116	0	1	0	0
T142	0	1	0	0
T152	0	2	0	0