Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T30,T32 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T1,T4,T5 |
VC_COV_UNR |
1 | Covered | T6,T30,T32 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T30,T32 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T8,T11 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T6,T30,T32 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T30,T35 |
0 | 1 | Covered | T32,T163 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T30,T35 |
0 | 1 | Covered | T6,T30,T35 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T6,T30,T35 |
1 | - | Covered | T6,T30,T35 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T6,T30,T32 |
DetectSt |
168 |
Covered |
T6,T30,T32 |
IdleSt |
163 |
Covered |
T1,T4,T5 |
StableSt |
191 |
Covered |
T6,T30,T35 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T6,T30,T32 |
DebounceSt->IdleSt |
163 |
Covered |
T32,T75,T164 |
DetectSt->IdleSt |
186 |
Covered |
T32,T163 |
DetectSt->StableSt |
191 |
Covered |
T6,T30,T35 |
IdleSt->DebounceSt |
148 |
Covered |
T6,T30,T32 |
StableSt->IdleSt |
206 |
Covered |
T6,T30,T35 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
10 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T6,T30,T32 |
|
0 |
1 |
Covered |
T6,T30,T32 |
|
0 |
0 |
Excluded |
T1,T4,T5 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T30,T32 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T30,T32 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T75,T76 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T6,T30,T32 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T32,T164,T165 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T6,T30,T32 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T32,T163 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T6,T30,T35 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T6,T30,T35 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T6,T30,T35 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
83 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
6 |
0 |
0 |
T80 |
0 |
4 |
0 |
0 |
T116 |
0 |
6 |
0 |
0 |
T166 |
0 |
2 |
0 |
0 |
T167 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2407 |
0 |
0 |
T6 |
2542 |
33 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
12 |
0 |
0 |
T32 |
0 |
134 |
0 |
0 |
T33 |
0 |
34 |
0 |
0 |
T35 |
0 |
24 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
155 |
0 |
0 |
T80 |
0 |
104 |
0 |
0 |
T116 |
0 |
230 |
0 |
0 |
T166 |
0 |
80 |
0 |
0 |
T167 |
0 |
48 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7743483 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
536 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2 |
0 |
0 |
T32 |
835 |
1 |
0 |
0 |
T44 |
704 |
0 |
0 |
0 |
T56 |
1615 |
0 |
0 |
0 |
T60 |
493 |
0 |
0 |
0 |
T63 |
506 |
0 |
0 |
0 |
T65 |
810 |
0 |
0 |
0 |
T74 |
22882 |
0 |
0 |
0 |
T138 |
753 |
0 |
0 |
0 |
T163 |
0 |
1 |
0 |
0 |
T168 |
454 |
0 |
0 |
0 |
T169 |
754 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
3632 |
0 |
0 |
T6 |
2542 |
103 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
4 |
0 |
0 |
T33 |
0 |
46 |
0 |
0 |
T35 |
0 |
179 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
238 |
0 |
0 |
T80 |
0 |
205 |
0 |
0 |
T116 |
0 |
568 |
0 |
0 |
T166 |
0 |
37 |
0 |
0 |
T167 |
0 |
43 |
0 |
0 |
T170 |
0 |
38 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
37 |
0 |
0 |
T6 |
2542 |
1 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T80 |
0 |
2 |
0 |
0 |
T116 |
0 |
3 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7695949 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
48 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7698284 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
50 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
44 |
0 |
0 |
T6 |
2542 |
1 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T80 |
0 |
2 |
0 |
0 |
T116 |
0 |
3 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
39 |
0 |
0 |
T6 |
2542 |
1 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T80 |
0 |
2 |
0 |
0 |
T116 |
0 |
3 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
37 |
0 |
0 |
T6 |
2542 |
1 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T80 |
0 |
2 |
0 |
0 |
T116 |
0 |
3 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
37 |
0 |
0 |
T6 |
2542 |
1 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
3 |
0 |
0 |
T80 |
0 |
2 |
0 |
0 |
T116 |
0 |
3 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
3572 |
0 |
0 |
T6 |
2542 |
102 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T33 |
0 |
44 |
0 |
0 |
T35 |
0 |
178 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
232 |
0 |
0 |
T80 |
0 |
202 |
0 |
0 |
T116 |
0 |
563 |
0 |
0 |
T166 |
0 |
35 |
0 |
0 |
T167 |
0 |
41 |
0 |
0 |
T170 |
0 |
36 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7745969 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
542 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
14 |
0 |
0 |
T6 |
2542 |
1 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T89 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T143 |
0 |
1 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T171 |
0 |
1 |
0 |
0 |
T172 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T8,T11,T34 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T1,T4,T5 |
VC_COV_UNR |
1 | Covered | T8,T11,T34 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T8,T11,T34 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T11,T34 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T8,T11,T34 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T11,T34 |
0 | 1 | Covered | T35,T71,T151 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T8,T11,T34 |
0 | 1 | Covered | T34,T32,T35 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T8,T11,T34 |
1 | - | Covered | T34,T32,T35 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T8,T11,T34 |
DetectSt |
168 |
Covered |
T8,T11,T34 |
IdleSt |
163 |
Covered |
T1,T4,T5 |
StableSt |
191 |
Covered |
T8,T11,T34 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T8,T11,T34 |
DebounceSt->IdleSt |
163 |
Covered |
T33,T71,T75 |
DetectSt->IdleSt |
186 |
Covered |
T35,T71,T151 |
DetectSt->StableSt |
191 |
Covered |
T8,T11,T34 |
IdleSt->DebounceSt |
148 |
Covered |
T8,T11,T34 |
StableSt->IdleSt |
206 |
Covered |
T8,T34,T32 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
10 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T8,T11,T34 |
|
0 |
1 |
Covered |
T8,T11,T34 |
|
0 |
0 |
Excluded |
T1,T4,T5 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T11,T34 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T8,T11,T34 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T75,T76 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T8,T11,T34 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T33,T71,T173 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T8,T11,T34 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T35,T71,T151 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T8,T11,T34 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T34,T32,T35 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T8,T11,T34 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
148 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
2 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
6 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T35 |
0 |
6 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
2 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T174 |
0 |
4 |
0 |
0 |
T175 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
4158 |
0 |
0 |
T8 |
15549 |
82 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
87 |
0 |
0 |
T23 |
0 |
81 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
201 |
0 |
0 |
T33 |
0 |
74 |
0 |
0 |
T34 |
0 |
71 |
0 |
0 |
T35 |
0 |
65 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
77 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T174 |
0 |
190 |
0 |
0 |
T175 |
0 |
71 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7743418 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
538 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
3 |
0 |
0 |
T31 |
760 |
0 |
0 |
0 |
T33 |
7851 |
0 |
0 |
0 |
T35 |
16707 |
1 |
0 |
0 |
T45 |
24267 |
0 |
0 |
0 |
T69 |
4866 |
0 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T141 |
404 |
0 |
0 |
0 |
T142 |
611 |
0 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T176 |
16234 |
0 |
0 |
0 |
T177 |
12238 |
0 |
0 |
0 |
T178 |
16971 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7560 |
0 |
0 |
T8 |
15549 |
41 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
109 |
0 |
0 |
T23 |
0 |
39 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
144 |
0 |
0 |
T34 |
0 |
22 |
0 |
0 |
T35 |
0 |
45 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
128 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T80 |
0 |
445 |
0 |
0 |
T174 |
0 |
319 |
0 |
0 |
T175 |
0 |
69 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
68 |
0 |
0 |
T8 |
15549 |
1 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
1 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T80 |
0 |
4 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7688688 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
538 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7691026 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
542 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
78 |
0 |
0 |
T8 |
15549 |
1 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
1 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
71 |
0 |
0 |
T8 |
15549 |
1 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
1 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T71 |
0 |
1 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
68 |
0 |
0 |
T8 |
15549 |
1 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
1 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T80 |
0 |
4 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
68 |
0 |
0 |
T8 |
15549 |
1 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
1 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
3 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T80 |
0 |
4 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7459 |
0 |
0 |
T8 |
15549 |
39 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
107 |
0 |
0 |
T23 |
0 |
37 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T32 |
0 |
140 |
0 |
0 |
T34 |
0 |
21 |
0 |
0 |
T35 |
0 |
42 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T65 |
0 |
126 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
T80 |
0 |
439 |
0 |
0 |
T174 |
0 |
316 |
0 |
0 |
T175 |
0 |
68 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2943 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
5 |
0 |
0 |
T5 |
422 |
2 |
0 |
0 |
T6 |
2542 |
7 |
0 |
0 |
T7 |
6580 |
22 |
0 |
0 |
T8 |
0 |
37 |
0 |
0 |
T13 |
695 |
3 |
0 |
0 |
T14 |
491 |
7 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
24 |
0 |
0 |
T47 |
0 |
3 |
0 |
0 |
T49 |
0 |
7 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7745969 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
542 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
35 |
0 |
0 |
T21 |
1874 |
0 |
0 |
0 |
T23 |
62999 |
0 |
0 |
0 |
T30 |
4653 |
0 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T34 |
621 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T40 |
5015 |
0 |
0 |
0 |
T41 |
14549 |
0 |
0 |
0 |
T57 |
5987 |
0 |
0 |
0 |
T58 |
492 |
0 |
0 |
0 |
T80 |
0 |
2 |
0 |
0 |
T89 |
0 |
1 |
0 |
0 |
T107 |
422 |
0 |
0 |
0 |
T108 |
422 |
0 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T150 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
T179 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 44 | 95.65 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 30 | 93.75 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
0 |
1 |
187 |
0 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
| Total | Covered | Percent |
Conditions | 21 | 18 | 85.71 |
Logical | 21 | 18 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T11,T34 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T1,T4,T5 |
VC_COV_UNR |
1 | Covered | T6,T11,T34 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T11,T34 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T11,T34 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T6,T11,T34 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T11,T34 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T11,T34 |
0 | 1 | Covered | T6,T30,T65 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T6,T11,T34 |
1 | - | Covered | T6,T30,T65 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
5 |
83.33 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T6,T11,T34 |
DetectSt |
168 |
Covered |
T6,T11,T34 |
IdleSt |
163 |
Covered |
T1,T4,T5 |
StableSt |
191 |
Covered |
T6,T11,T34 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T6,T11,T34 |
DebounceSt->IdleSt |
163 |
Covered |
T180,T75,T84 |
DetectSt->IdleSt |
186 |
Not Covered |
|
DetectSt->StableSt |
191 |
Covered |
T6,T11,T34 |
IdleSt->DebounceSt |
148 |
Covered |
T6,T11,T34 |
StableSt->IdleSt |
206 |
Covered |
T6,T30,T65 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
19 |
95.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
9 |
90.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T6,T11,T34 |
|
0 |
1 |
Covered |
T6,T11,T34 |
|
0 |
0 |
Excluded |
T1,T4,T5 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T11,T34 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T11,T34 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T75,T76 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T6,T11,T34 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T84,T173,T165 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T6,T11,T34 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Not Covered |
|
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T6,T11,T34 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T6,T30,T65 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T6,T11,T34 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
143 |
0 |
0 |
T6 |
2542 |
6 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
4 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T35 |
0 |
4 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
2 |
0 |
0 |
T142 |
0 |
4 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
T175 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
35064 |
0 |
0 |
T6 |
2542 |
99 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
87 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
186 |
0 |
0 |
T34 |
0 |
71 |
0 |
0 |
T35 |
0 |
48 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
77 |
0 |
0 |
T142 |
0 |
30 |
0 |
0 |
T152 |
0 |
21 |
0 |
0 |
T174 |
0 |
95 |
0 |
0 |
T175 |
0 |
71 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7743423 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
532 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
6186 |
0 |
0 |
T6 |
2542 |
126 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
41 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
399 |
0 |
0 |
T34 |
0 |
141 |
0 |
0 |
T35 |
0 |
146 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
39 |
0 |
0 |
T142 |
0 |
100 |
0 |
0 |
T152 |
0 |
72 |
0 |
0 |
T174 |
0 |
9 |
0 |
0 |
T175 |
0 |
178 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
68 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7691453 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
210 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7693794 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
213 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
76 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
68 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
68 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
68 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
6087 |
0 |
0 |
T6 |
2542 |
122 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
39 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
396 |
0 |
0 |
T34 |
0 |
139 |
0 |
0 |
T35 |
0 |
143 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
38 |
0 |
0 |
T142 |
0 |
97 |
0 |
0 |
T152 |
0 |
71 |
0 |
0 |
T174 |
0 |
8 |
0 |
0 |
T175 |
0 |
176 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7745969 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
542 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
37 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 45 | 97.83 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 31 | 96.88 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
0 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T30,T32 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T1,T4,T5 |
VC_COV_UNR |
1 | Covered | T6,T30,T32 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T30,T32 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T8,T11 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T6,T30,T32 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T32,T35 |
0 | 1 | Covered | T30,T145 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T32,T35 |
0 | 1 | Covered | T6,T32,T35 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T6,T32,T35 |
1 | - | Covered | T6,T32,T35 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T6,T30,T32 |
DetectSt |
168 |
Covered |
T6,T30,T32 |
IdleSt |
163 |
Covered |
T1,T4,T5 |
StableSt |
191 |
Covered |
T6,T32,T35 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T6,T30,T32 |
DebounceSt->IdleSt |
163 |
Covered |
T75,T76 |
DetectSt->IdleSt |
186 |
Covered |
T30,T145 |
DetectSt->StableSt |
191 |
Covered |
T6,T32,T35 |
IdleSt->DebounceSt |
148 |
Covered |
T6,T30,T32 |
StableSt->IdleSt |
206 |
Covered |
T6,T32,T35 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
19 |
95.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
9 |
90.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T6,T30,T32 |
|
0 |
1 |
Covered |
T6,T30,T32 |
|
0 |
0 |
Excluded |
T1,T4,T5 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T30,T32 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T30,T32 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T75,T76 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T6,T30,T32 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Not Covered |
|
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T6,T30,T32 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T30,T145 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T6,T32,T35 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T6,T32,T35 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T6,T32,T35 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
78 |
0 |
0 |
T6 |
2542 |
4 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T31 |
0 |
2 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T35 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
2 |
0 |
0 |
T80 |
0 |
2 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T166 |
0 |
2 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2290 |
0 |
0 |
T6 |
2542 |
66 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
93 |
0 |
0 |
T31 |
0 |
29 |
0 |
0 |
T32 |
0 |
134 |
0 |
0 |
T35 |
0 |
24 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
69 |
0 |
0 |
T80 |
0 |
94 |
0 |
0 |
T152 |
0 |
21 |
0 |
0 |
T166 |
0 |
80 |
0 |
0 |
T174 |
0 |
95 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7743488 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
534 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2 |
0 |
0 |
T30 |
4653 |
1 |
0 |
0 |
T40 |
5015 |
0 |
0 |
0 |
T41 |
14549 |
0 |
0 |
0 |
T42 |
710 |
0 |
0 |
0 |
T58 |
492 |
0 |
0 |
0 |
T59 |
493 |
0 |
0 |
0 |
T108 |
422 |
0 |
0 |
0 |
T145 |
0 |
1 |
0 |
0 |
T181 |
421 |
0 |
0 |
0 |
T182 |
421 |
0 |
0 |
0 |
T183 |
403 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2559 |
0 |
0 |
T6 |
2542 |
28 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T31 |
0 |
40 |
0 |
0 |
T32 |
0 |
81 |
0 |
0 |
T35 |
0 |
78 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
236 |
0 |
0 |
T80 |
0 |
300 |
0 |
0 |
T116 |
0 |
109 |
0 |
0 |
T152 |
0 |
139 |
0 |
0 |
T166 |
0 |
50 |
0 |
0 |
T174 |
0 |
298 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
36 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7694739 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
210 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7697082 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
213 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
40 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
38 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
36 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
36 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
2 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2504 |
0 |
0 |
T6 |
2542 |
26 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T31 |
0 |
39 |
0 |
0 |
T32 |
0 |
78 |
0 |
0 |
T35 |
0 |
77 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
234 |
0 |
0 |
T80 |
0 |
298 |
0 |
0 |
T116 |
0 |
106 |
0 |
0 |
T152 |
0 |
137 |
0 |
0 |
T166 |
0 |
49 |
0 |
0 |
T174 |
0 |
296 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
6548 |
0 |
0 |
T1 |
15395 |
31 |
0 |
0 |
T2 |
13478 |
10 |
0 |
0 |
T3 |
17732 |
10 |
0 |
0 |
T4 |
484 |
6 |
0 |
0 |
T5 |
422 |
1 |
0 |
0 |
T6 |
2542 |
6 |
0 |
0 |
T7 |
6580 |
32 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
5 |
0 |
0 |
T15 |
4614 |
14 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7745969 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
542 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
17 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T164 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T171 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T34,T23 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T1,T4,T5 |
VC_COV_UNR |
1 | Covered | T6,T34,T23 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T34,T23 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T34,T23 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T6,T34,T23 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T34,T23 |
0 | 1 | Covered | T151 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T34,T23 |
0 | 1 | Covered | T6,T34,T30 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T6,T34,T23 |
1 | - | Covered | T6,T34,T30 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T6,T34,T23 |
DetectSt |
168 |
Covered |
T6,T34,T23 |
IdleSt |
163 |
Covered |
T1,T4,T5 |
StableSt |
191 |
Covered |
T6,T34,T23 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T6,T34,T23 |
DebounceSt->IdleSt |
163 |
Covered |
T6,T71,T184 |
DetectSt->IdleSt |
186 |
Covered |
T151 |
DetectSt->StableSt |
191 |
Covered |
T6,T34,T23 |
IdleSt->DebounceSt |
148 |
Covered |
T6,T34,T23 |
StableSt->IdleSt |
206 |
Covered |
T6,T34,T30 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
10 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T6,T34,T23 |
|
0 |
1 |
Covered |
T6,T34,T23 |
|
0 |
0 |
Excluded |
T1,T4,T5 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T34,T23 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T34,T23 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T75,T76 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T6,T34,T23 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T6,T71,T184 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T6,T34,T23 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T151 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T6,T34,T23 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T6,T34,T30 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T6,T34,T23 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
155 |
0 |
0 |
T6 |
2542 |
5 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
4 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
2 |
0 |
0 |
T65 |
0 |
2 |
0 |
0 |
T142 |
0 |
2 |
0 |
0 |
T152 |
0 |
4 |
0 |
0 |
T167 |
0 |
2 |
0 |
0 |
T174 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
4511 |
0 |
0 |
T6 |
2542 |
99 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
81 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
52 |
0 |
0 |
T34 |
0 |
71 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
88 |
0 |
0 |
T65 |
0 |
77 |
0 |
0 |
T142 |
0 |
15 |
0 |
0 |
T152 |
0 |
42 |
0 |
0 |
T167 |
0 |
48 |
0 |
0 |
T174 |
0 |
95 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7743411 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
533 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
1 |
0 |
0 |
T150 |
4678 |
0 |
0 |
0 |
T151 |
2880 |
1 |
0 |
0 |
T185 |
5116 |
0 |
0 |
0 |
T186 |
28652 |
0 |
0 |
0 |
T187 |
672 |
0 |
0 |
0 |
T188 |
422 |
0 |
0 |
0 |
T189 |
183481 |
0 |
0 |
0 |
T190 |
598 |
0 |
0 |
0 |
T191 |
13622 |
0 |
0 |
0 |
T192 |
422 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
5682 |
0 |
0 |
T6 |
2542 |
97 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
39 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
111 |
0 |
0 |
T34 |
0 |
22 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
42 |
0 |
0 |
T65 |
0 |
38 |
0 |
0 |
T142 |
0 |
43 |
0 |
0 |
T152 |
0 |
177 |
0 |
0 |
T167 |
0 |
114 |
0 |
0 |
T174 |
0 |
162 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
72 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7701290 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
210 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7703628 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
213 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
82 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
73 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
72 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
72 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
2 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T167 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
5579 |
0 |
0 |
T6 |
2542 |
94 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
37 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
108 |
0 |
0 |
T34 |
0 |
21 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T64 |
0 |
40 |
0 |
0 |
T65 |
0 |
36 |
0 |
0 |
T142 |
0 |
42 |
0 |
0 |
T152 |
0 |
174 |
0 |
0 |
T167 |
0 |
112 |
0 |
0 |
T174 |
0 |
160 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7745969 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
542 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
41 |
0 |
0 |
T6 |
2542 |
1 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T152 |
0 |
1 |
0 |
0 |
T170 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
58 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T4,T5 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T11,T34 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T1,T4,T5 |
VC_COV_UNR |
1 | Covered | T6,T11,T34 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T4,T5 |
1 | Covered | T6,T11,T34 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T11,T34 |
1 | 0 | Covered | T1,T4,T5 |
1 | 1 | Covered | T6,T11,T34 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T11,T34 |
0 | 1 | Covered | T99,T193 |
1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T6,T11,T34 |
0 | 1 | Covered | T6,T166,T80 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T6,T11,T34 |
1 | - | Covered | T6,T166,T80 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T6,T11,T34 |
DetectSt |
168 |
Covered |
T6,T11,T34 |
IdleSt |
163 |
Covered |
T1,T4,T5 |
StableSt |
191 |
Covered |
T6,T11,T34 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T6,T11,T34 |
DebounceSt->IdleSt |
163 |
Covered |
T75,T149,T194 |
DetectSt->IdleSt |
186 |
Covered |
T99,T193 |
DetectSt->StableSt |
191 |
Covered |
T6,T11,T34 |
IdleSt->DebounceSt |
148 |
Covered |
T6,T11,T34 |
StableSt->IdleSt |
206 |
Covered |
T6,T166,T71 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
10 |
10 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T6,T11,T34 |
|
0 |
1 |
Covered |
T6,T11,T34 |
|
0 |
0 |
Excluded |
T1,T4,T5 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T11,T34 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T11,T34 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T75,T76 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T6,T11,T34 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T149,T194,T195 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T6,T11,T34 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T99,T193 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T6,T11,T34 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Excluded |
|
VC_COV_UNR |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T6,T166,T80 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T6,T11,T34 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
89 |
0 |
0 |
T6 |
2542 |
6 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
2 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
2 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
4 |
0 |
0 |
T78 |
0 |
2 |
0 |
0 |
T80 |
0 |
2 |
0 |
0 |
T116 |
0 |
2 |
0 |
0 |
T117 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T166 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2595 |
0 |
0 |
T6 |
2542 |
121 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
87 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
71 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
169 |
0 |
0 |
T78 |
0 |
69 |
0 |
0 |
T80 |
0 |
96 |
0 |
0 |
T116 |
0 |
52 |
0 |
0 |
T117 |
0 |
57 |
0 |
0 |
T151 |
0 |
20 |
0 |
0 |
T166 |
0 |
80 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7743477 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
532 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2 |
0 |
0 |
T99 |
28754 |
1 |
0 |
0 |
T121 |
851 |
0 |
0 |
0 |
T193 |
0 |
1 |
0 |
0 |
T196 |
17485 |
0 |
0 |
0 |
T197 |
507 |
0 |
0 |
0 |
T198 |
720 |
0 |
0 |
0 |
T199 |
495 |
0 |
0 |
0 |
T200 |
525 |
0 |
0 |
0 |
T201 |
24808 |
0 |
0 |
0 |
T202 |
492 |
0 |
0 |
0 |
T203 |
510 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2816 |
0 |
0 |
T6 |
2542 |
123 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
42 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
46 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
103 |
0 |
0 |
T78 |
0 |
41 |
0 |
0 |
T80 |
0 |
43 |
0 |
0 |
T116 |
0 |
125 |
0 |
0 |
T117 |
0 |
42 |
0 |
0 |
T151 |
0 |
38 |
0 |
0 |
T166 |
0 |
172 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
40 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7690844 |
0 |
0 |
T1 |
15395 |
14971 |
0 |
0 |
T2 |
13478 |
13063 |
0 |
0 |
T3 |
17732 |
17284 |
0 |
0 |
T4 |
484 |
83 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
2542 |
48 |
0 |
0 |
T7 |
6580 |
1486 |
0 |
0 |
T13 |
695 |
294 |
0 |
0 |
T14 |
491 |
90 |
0 |
0 |
T15 |
4614 |
4213 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7693178 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
50 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
47 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
42 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
40 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
40 |
0 |
0 |
T6 |
2542 |
3 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T116 |
0 |
1 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T151 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
2750 |
0 |
0 |
T6 |
2542 |
119 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
40 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T34 |
0 |
44 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T71 |
0 |
99 |
0 |
0 |
T78 |
0 |
39 |
0 |
0 |
T80 |
0 |
42 |
0 |
0 |
T116 |
0 |
123 |
0 |
0 |
T117 |
0 |
40 |
0 |
0 |
T151 |
0 |
36 |
0 |
0 |
T166 |
0 |
171 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
6247 |
0 |
0 |
T1 |
15395 |
28 |
0 |
0 |
T2 |
13478 |
12 |
0 |
0 |
T3 |
17732 |
14 |
0 |
0 |
T4 |
484 |
6 |
0 |
0 |
T5 |
422 |
3 |
0 |
0 |
T6 |
2542 |
6 |
0 |
0 |
T7 |
6580 |
25 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
6 |
0 |
0 |
T15 |
4614 |
10 |
0 |
0 |
T22 |
0 |
31 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
7745969 |
0 |
0 |
T1 |
15395 |
14975 |
0 |
0 |
T2 |
13478 |
13067 |
0 |
0 |
T3 |
17732 |
17291 |
0 |
0 |
T4 |
484 |
84 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
2542 |
542 |
0 |
0 |
T7 |
6580 |
1499 |
0 |
0 |
T13 |
695 |
295 |
0 |
0 |
T14 |
491 |
91 |
0 |
0 |
T15 |
4614 |
4214 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8393152 |
14 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T80 |
0 |
1 |
0 |
0 |
T84 |
0 |
1 |
0 |
0 |
T166 |
0 |
1 |
0 |
0 |
T172 |
0 |
2 |
0 |
0 |
T204 |
0 |
1 |
0 |
0 |
T205 |
0 |
1 |
0 |
0 |
T206 |
0 |
1 |
0 |
0 |
T207 |
0 |
1 |
0 |
0 |
T208 |
0 |
1 |
0 |
0 |