Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T11,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T11,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T11,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T34
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T11,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T30
0	1	Covered	T30,T33,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T30
0	1	Covered	T6,T30,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T11,T30
1	-	Covered	T6,T30,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T11,T30
DetectSt	168	Covered	T6,T11,T30
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T11,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T11,T30
DebounceSt->IdleSt	163	Covered	T6,T163,T75
DetectSt->IdleSt	186	Covered	T30,T33,T151
DetectSt->StableSt	191	Covered	T6,T11,T30
IdleSt->DebounceSt	148	Covered	T6,T11,T30
StableSt->IdleSt	206	Covered	T6,T30,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T11,T30
0	1	Covered	T6,T11,T30
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T30
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T11,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T11,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T163,T209
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T11,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T33,T151
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T30,T33
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	178	0	0
CntIncr_A	8393152	19177	0	0
CntNoWrap_A	8393152	7743388	0	0
DetectStDropOut_A	8393152	6	0	0
DetectedOut_A	8393152	6013	0	0
DetectedPulseOut_A	8393152	78	0	0
DisabledIdleSt_A	8393152	7676660	0	0
DisabledNoDetection_A	8393152	7678989	0	0
EnterDebounceSt_A	8393152	94	0	0
EnterDetectSt_A	8393152	84	0	0
EnterStableSt_A	8393152	78	0	0
PulseIsPulse_A	8393152	78	0	0
StayInStableSt	8393152	5902	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	178	0	0
T6	2542	5	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	2	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	8	0	0
T31	0	4	0	0
T33	0	4	0	0
T35	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	2	0	0
T142	0	4	0	0
T153	0	2	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	19177	0	0
T6	2542	99	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	87	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	291	0	0
T31	0	58	0	0
T33	0	108	0	0
T35	0	24	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	88	0	0
T142	0	30	0	0
T153	0	53	0	0
T175	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743388	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	533	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6	0	0
T30	4653	1	0	0
T33	0	1	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T42	710	0	0	0
T58	492	0	0	0
T59	493	0	0	0
T100	0	1	0	0
T108	422	0	0	0
T110	0	1	0	0
T151	0	1	0	0
T181	421	0	0	0
T182	421	0	0	0
T183	403	0	0	0
T184	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6013	0	0
T6	2542	27	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	109	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	277	0	0
T31	0	148	0	0
T33	0	4	0	0
T35	0	274	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	43	0	0
T142	0	97	0	0
T153	0	106	0	0
T175	0	179	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	78	0	0
T6	2542	2	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	1	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7676660	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	210	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7678989	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	213	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	94	0	0
T6	2542	3	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	1	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	4	0	0
T31	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	84	0	0
T6	2542	2	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	1	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	4	0	0
T31	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	78	0	0
T6	2542	2	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	1	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	78	0	0
T6	2542	2	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	1	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T142	0	2	0	0
T153	0	1	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	5902	0	0
T6	2542	25	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T11	0	107	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	273	0	0
T31	0	146	0	0
T33	0	3	0	0
T35	0	272	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	41	0	0
T142	0	94	0	0
T153	0	104	0	0
T175	0	177	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	45	0	0
T6	2542	2	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T33	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	2	0	0
T80	0	2	0	0
T89	0	2	0	0
T104	0	1	0	0
T116	0	1	0	0
T142	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T30,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T30,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T30,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T57,T30
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T30,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T33
0	1	Covered	T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T30,T33
0	1	Covered	T30,T116,T179
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T30,T33
1	-	Covered	T30,T116,T179

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T30,T33
DetectSt	168	Covered	T6,T30,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T30,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T30,T33
DebounceSt->IdleSt	163	Covered	T75,T172,T76
DetectSt->IdleSt	186	Covered	T78
DetectSt->StableSt	191	Covered	T6,T30,T33
IdleSt->DebounceSt	148	Covered	T6,T30,T33
StableSt->IdleSt	206	Covered	T6,T30,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T30,T33
0	1	Covered	T6,T30,T33
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T30,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T30,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T30,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T172,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T30,T33
DetectSt	-	-	-	-	1	-	-	Covered	T78
DetectSt	-	-	-	-	0	1	-	Covered	T6,T30,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T116,T179
StableSt	-	-	-	-	-	-	0	Covered	T6,T30,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	100	0	0
CntIncr_A	8393152	2952	0	0
CntNoWrap_A	8393152	7743466	0	0
DetectStDropOut_A	8393152	1	0	0
DetectedOut_A	8393152	3374	0	0
DetectedPulseOut_A	8393152	47	0	0
DisabledIdleSt_A	8393152	7698561	0	0
DisabledNoDetection_A	8393152	7700906	0	0
EnterDebounceSt_A	8393152	52	0	0
EnterDetectSt_A	8393152	48	0	0
EnterStableSt_A	8393152	47	0	0
PulseIsPulse_A	8393152	47	0	0
StayInStableSt	8393152	3300	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8393152	6277	0	0
gen_low_level_sva.LowLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	100	0	0
T6	2542	2	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	6	0	0
T33	0	4	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	4	0	0
T80	0	2	0	0
T116	0	2	0	0
T150	0	2	0	0
T166	0	2	0	0
T179	0	2	0	0
T180	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2952	0	0
T6	2542	55	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	279	0	0
T33	0	108	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	138	0	0
T80	0	10	0	0
T116	0	52	0	0
T150	0	12	0	0
T166	0	80	0	0
T179	0	99	0	0
T180	0	103	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743466	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	536	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1	0	0
T71	75048	0	0	0
T72	1536	0	0	0
T78	964	1	0	0
T156	688	0	0	0
T157	407	0	0	0
T158	3427	0	0	0
T159	498	0	0	0
T160	744	0	0	0
T161	422	0	0	0
T162	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3374	0	0
T6	2542	40	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	128	0	0
T33	0	88	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	41	0	0
T80	0	38	0	0
T116	0	43	0	0
T150	0	2	0	0
T166	0	168	0	0
T179	0	92	0	0
T180	0	148	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	47	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T33	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T116	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7698561	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	376	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7700906	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	379	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	52	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T33	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	2	0	0
T80	0	1	0	0
T116	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	48	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T33	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	2	0	0
T80	0	1	0	0
T116	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	47	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T33	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T116	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	47	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T33	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T116	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3300	0	0
T6	2542	38	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T30	0	124	0	0
T33	0	84	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T78	0	39	0	0
T80	0	36	0	0
T116	0	42	0	0
T150	0	1	0	0
T166	0	166	0	0
T179	0	91	0	0
T180	0	145	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6277	0	0
T1	15395	23	0	0
T2	13478	15	0	0
T3	17732	10	0	0
T4	484	10	0	0
T5	422	3	0	0
T6	2542	7	0	0
T7	6580	22	0	0
T13	695	0	0	0
T14	491	8	0	0
T15	4614	9	0	0
T22	0	28	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	20	0	0
T30	4653	2	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T42	710	0	0	0
T58	492	0	0	0
T59	493	0	0	0
T108	422	0	0	0
T116	0	1	0	0
T150	0	1	0	0
T171	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	421	0	0	0
T182	421	0	0	0
T183	403	0	0	0
T205	0	1	0	0
T206	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T30,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T34,T30,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T34,T30,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T57,T30
1	0	Covered	T1,T4,T5
1	1	Covered	T34,T30,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T30,T32
0	1	Covered	T71
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T30,T32
0	1	Covered	T34,T30,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T30,T32
1	-	Covered	T34,T30,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T30,T32
DetectSt	168	Covered	T34,T30,T32
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T34,T30,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T30,T32
DebounceSt->IdleSt	163	Covered	T152,T180,T75
DetectSt->IdleSt	186	Covered	T71
DetectSt->StableSt	191	Covered	T34,T30,T32
IdleSt->DebounceSt	148	Covered	T34,T30,T32
StableSt->IdleSt	206	Covered	T34,T30,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T30,T32
0	1	Covered	T34,T30,T32
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T30,T32
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T30,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T30,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T152,T212,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T30,T32
DetectSt	-	-	-	-	1	-	-	Covered	T71
DetectSt	-	-	-	-	0	1	-	Covered	T34,T30,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T30,T32
StableSt	-	-	-	-	-	-	0	Covered	T34,T30,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	114	0	0
CntIncr_A	8393152	29071	0	0
CntNoWrap_A	8393152	7743452	0	0
DetectStDropOut_A	8393152	1	0	0
DetectedOut_A	8393152	4010	0	0
DetectedPulseOut_A	8393152	52	0	0
DisabledIdleSt_A	8393152	7682134	0	0
DisabledNoDetection_A	8393152	7684481	0	0
EnterDebounceSt_A	8393152	62	0	0
EnterDetectSt_A	8393152	53	0	0
EnterStableSt_A	8393152	52	0	0
PulseIsPulse_A	8393152	52	0	0
StayInStableSt	8393152	3934	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	114	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	4	0	0
T31	0	4	0	0
T32	0	4	0	0
T34	621	2	0	0
T35	0	4	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	6	0	0
T78	0	4	0	0
T80	0	2	0	0
T107	422	0	0	0
T108	422	0	0	0
T152	0	1	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	29071	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	52	0	0
T31	0	58	0	0
T32	0	134	0	0
T34	621	71	0	0
T35	0	41	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	162	0	0
T78	0	138	0	0
T80	0	60	0	0
T107	422	0	0	0
T108	422	0	0	0
T152	0	21	0	0
T166	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743452	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1	0	0
T71	75048	1	0	0
T72	1536	0	0	0
T80	14290	0	0	0
T111	618	0	0	0
T112	7332	0	0	0
T113	522	0	0	0
T114	416	0	0	0
T115	526	0	0	0
T161	422	0	0	0
T162	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	4010	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	46	0	0
T31	0	30	0	0
T32	0	179	0	0
T34	621	22	0	0
T35	0	227	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	122	0	0
T78	0	80	0	0
T80	0	27	0	0
T107	422	0	0	0
T108	422	0	0	0
T115	0	41	0	0
T166	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	52	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	621	1	0	0
T35	0	2	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	2	0	0
T78	0	2	0	0
T80	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0
T115	0	1	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7682134	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7684481	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	62	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	621	1	0	0
T35	0	2	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	3	0	0
T78	0	2	0	0
T80	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0
T152	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	53	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	621	1	0	0
T35	0	2	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	3	0	0
T78	0	2	0	0
T80	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0
T115	0	1	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	52	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	621	1	0	0
T35	0	2	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	2	0	0
T78	0	2	0	0
T80	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0
T115	0	1	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	52	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	621	1	0	0
T35	0	2	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	2	0	0
T78	0	2	0	0
T80	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0
T115	0	1	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3934	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	44	0	0
T31	0	28	0	0
T32	0	176	0	0
T34	621	21	0	0
T35	0	224	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T71	0	118	0	0
T78	0	77	0	0
T80	0	26	0	0
T107	422	0	0	0
T108	422	0	0	0
T115	0	39	0	0
T166	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	28	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T34	621	1	0	0
T35	0	1	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T58	492	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T107	422	0	0	0
T108	422	0	0	0
T116	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T30,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T30,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T30,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T8,T30,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T32
0	1	Covered	T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T32
0	1	Covered	T8,T30,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T30,T32
1	-	Covered	T8,T30,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T30,T32
DetectSt	168	Covered	T8,T30,T32
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T30,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T30,T32
DebounceSt->IdleSt	163	Covered	T75,T76
DetectSt->IdleSt	186	Covered	T213
DetectSt->StableSt	191	Covered	T8,T30,T32
IdleSt->DebounceSt	148	Covered	T8,T30,T32
StableSt->IdleSt	206	Covered	T8,T30,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T30,T32
0	1	Covered	T8,T30,T32
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T30,T32
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T30,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T30,T32
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T30,T32
DetectSt	-	-	-	-	1	-	-	Covered	T213
DetectSt	-	-	-	-	0	1	-	Covered	T8,T30,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T30,T32
StableSt	-	-	-	-	-	-	0	Covered	T8,T30,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	92	0	0
CntIncr_A	8393152	2414	0	0
CntNoWrap_A	8393152	7743474	0	0
DetectStDropOut_A	8393152	1	0	0
DetectedOut_A	8393152	3002	0	0
DetectedPulseOut_A	8393152	44	0	0
DisabledIdleSt_A	8393152	7677774	0	0
DisabledNoDetection_A	8393152	7680112	0	0
EnterDebounceSt_A	8393152	47	0	0
EnterDetectSt_A	8393152	45	0	0
EnterStableSt_A	8393152	44	0	0
PulseIsPulse_A	8393152	44	0	0
StayInStableSt	8393152	2931	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8393152	6236	0	0
gen_low_level_sva.LowLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	92	0	0
T8	15549	4	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	6	0	0
T31	0	4	0	0
T32	0	2	0	0
T35	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	2	0	0
T116	0	2	0	0
T117	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2414	0	0
T8	15549	164	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	145	0	0
T31	0	58	0	0
T32	0	67	0	0
T35	0	24	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	60	0	0
T116	0	89	0	0
T117	0	57	0	0
T150	0	12	0	0
T151	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743474	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1	0	0
T83	64203	0	0	0
T213	4919	1	0	0
T214	38480	0	0	0
T215	430	0	0	0
T216	20400	0	0	0
T217	522	0	0	0
T218	36606	0	0	0
T219	674	0	0	0
T220	780	0	0	0
T221	4867	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3002	0	0
T8	15549	183	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	154	0	0
T31	0	201	0	0
T32	0	44	0	0
T35	0	40	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	40	0	0
T116	0	41	0	0
T117	0	201	0	0
T150	0	54	0	0
T151	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	44	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7677774	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	376	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7680112	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	379	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	47	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	45	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	44	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	44	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2931	0	0
T8	15549	180	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	149	0	0
T31	0	198	0	0
T32	0	43	0	0
T35	0	38	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T80	0	38	0	0
T116	0	39	0	0
T117	0	199	0	0
T150	0	52	0	0
T151	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6236	0	0
T1	15395	27	0	0
T2	13478	13	0	0
T3	17732	12	0	0
T4	484	5	0	0
T5	422	3	0	0
T6	2542	3	0	0
T7	6580	26	0	0
T13	695	0	0	0
T14	491	7	0	0
T15	4614	7	0	0
T22	0	25	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	17	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T73	408	0	0	0
T146	0	1	0	0
T164	0	1	0	0
T204	0	1	0	0
T206	0	1	0	0
T222	0	1	0	0
T223	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T23
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T8,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T23
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T23
0	1	Covered	T6,T8,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T23
1	-	Covered	T6,T8,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T23
DetectSt	168	Covered	T6,T8,T23
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T23
DebounceSt->IdleSt	163	Covered	T75,T209,T224
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T8,T23
IdleSt->DebounceSt	148	Covered	T6,T8,T23
StableSt->IdleSt	206	Covered	T6,T8,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T23
0	1	Covered	T6,T8,T23
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T23
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T209,T224,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T23
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T23
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	145	0	0
CntIncr_A	8393152	37563	0	0
CntNoWrap_A	8393152	7743421	0	0
DetectStDropOut_A	8393152	0	0	0
DetectedOut_A	8393152	6229	0	0
DetectedPulseOut_A	8393152	70	0	0
DisabledIdleSt_A	8393152	7673968	0	0
DisabledNoDetection_A	8393152	7676307	0	0
EnterDebounceSt_A	8393152	76	0	0
EnterDetectSt_A	8393152	70	0	0
EnterStableSt_A	8393152	70	0	0
PulseIsPulse_A	8393152	70	0	0
StayInStableSt	8393152	6124	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	145	0	0
T6	2542	2	0	0
T7	6580	0	0	0
T8	15549	4	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	2	0	0
T24	5079	0	0	0
T30	0	6	0	0
T32	0	4	0	0
T35	0	2	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	2	0	0
T65	0	2	0	0
T142	0	2	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	37563	0	0
T6	2542	55	0	0
T7	6580	0	0	0
T8	15549	164	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	81	0	0
T24	5079	0	0	0
T30	0	173	0	0
T32	0	134	0	0
T35	0	17	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	88	0	0
T65	0	77	0	0
T142	0	15	0	0
T174	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743421	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	536	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6229	0	0
T6	2542	5	0	0
T7	6580	0	0	0
T8	15549	206	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	29	0	0
T24	5079	0	0	0
T30	0	200	0	0
T32	0	283	0	0
T35	0	48	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	42	0	0
T65	0	128	0	0
T142	0	55	0	0
T174	0	539	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	70	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T142	0	1	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7673968	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	376	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7676307	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	379	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	76	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T142	0	1	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	70	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T142	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	70	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T142	0	1	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	70	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	3	0	0
T32	0	2	0	0
T35	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T142	0	1	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6124	0	0
T6	2542	4	0	0
T7	6580	0	0	0
T8	15549	203	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	28	0	0
T24	5079	0	0	0
T30	0	196	0	0
T32	0	280	0	0
T35	0	46	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T64	0	40	0	0
T65	0	126	0	0
T142	0	53	0	0
T174	0	537	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	35	0	0
T6	2542	1	0	0
T7	6580	0	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	1	0	0
T24	5079	0	0	0
T30	0	2	0	0
T32	0	1	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T80	0	1	0	0
T117	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T34,T30
1	0	Covered	T1,T4,T5
1	1	Covered	T8,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T31
0	1	Covered	T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T30,T31
0	1	Covered	T8,T71,T80
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T30,T31
1	-	Covered	T8,T71,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T30,T31
DetectSt	168	Covered	T8,T30,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T30,T31
DebounceSt->IdleSt	163	Covered	T30,T116,T75
DetectSt->IdleSt	186	Covered	T213
DetectSt->StableSt	191	Covered	T8,T30,T31
IdleSt->DebounceSt	148	Covered	T8,T30,T31
StableSt->IdleSt	206	Covered	T8,T71,T80

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T30,T31
0	1	Covered	T8,T30,T31
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T30,T31
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T116,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T213
DetectSt	-	-	-	-	0	1	-	Covered	T8,T30,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T71,T80
StableSt	-	-	-	-	-	-	0	Covered	T8,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	72	0	0
CntIncr_A	8393152	2407	0	0
CntNoWrap_A	8393152	7743494	0	0
DetectStDropOut_A	8393152	1	0	0
DetectedOut_A	8393152	2240	0	0
DetectedPulseOut_A	8393152	32	0	0
DisabledIdleSt_A	8393152	7720399	0	0
DisabledNoDetection_A	8393152	7722745	0	0
EnterDebounceSt_A	8393152	39	0	0
EnterDetectSt_A	8393152	33	0	0
EnterStableSt_A	8393152	32	0	0
PulseIsPulse_A	8393152	32	0	0
StayInStableSt	8393152	2191	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8393152	6843	0	0
gen_low_level_sva.LowLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	72	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	3	0	0
T31	0	2	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	6	0	0
T73	408	0	0	0
T80	0	2	0	0
T116	0	3	0	0
T143	0	2	0	0
T144	0	2	0	0
T226	0	4	0	0
T227	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2407	0	0
T8	15549	82	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	133	0	0
T31	0	29	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	250	0	0
T73	408	0	0	0
T80	0	96	0	0
T116	0	178	0	0
T143	0	51	0	0
T144	0	44	0	0
T226	0	42	0	0
T227	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7743494	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1	0	0
T83	64203	0	0	0
T213	4919	1	0	0
T214	38480	0	0	0
T215	430	0	0	0
T216	20400	0	0	0
T217	522	0	0	0
T218	36606	0	0	0
T219	674	0	0	0
T220	780	0	0	0
T221	4867	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2240	0	0
T8	15549	17	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	45	0	0
T31	0	160	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	354	0	0
T73	408	0	0	0
T80	0	220	0	0
T116	0	41	0	0
T143	0	147	0	0
T144	0	60	0	0
T226	0	87	0	0
T227	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	32	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	3	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T226	0	2	0	0
T227	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7720399	0	0
T1	15395	14971	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7722745	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	39	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	3	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	2	0	0
T143	0	1	0	0
T144	0	1	0	0
T226	0	2	0	0
T227	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	33	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	3	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T226	0	2	0	0
T227	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	32	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	3	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T226	0	2	0	0
T227	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	32	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	3	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T226	0	2	0	0
T227	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	2191	0	0
T8	15549	16	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T30	0	43	0	0
T31	0	158	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	349	0	0
T73	408	0	0	0
T80	0	219	0	0
T116	0	40	0	0
T143	0	145	0	0
T144	0	58	0	0
T226	0	84	0	0
T227	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	6843	0	0
T1	15395	25	0	0
T2	13478	7	0	0
T3	17732	12	0	0
T4	484	7	0	0
T5	422	1	0	0
T6	2542	7	0	0
T7	6580	25	0	0
T13	695	0	0	0
T14	491	7	0	0
T15	4614	9	0	0
T22	0	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	15	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T10	490	0	0	0
T11	605	0	0	0
T24	5079	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T71	0	1	0	0
T73	408	0	0	0
T80	0	1	0	0
T116	0	1	0	0
T171	0	2	0	0
T172	0	1	0	0
T193	0	1	0	0
T206	0	2	0	0
T207	0	1	0	0
T226	0	1	0	0