Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T9,T24
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T24
1	0	Covered	T1,T9,T12
1	1	Covered	T1,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T24
0	1	Covered	T24,T40,T67
1	0	Covered	T87,T38,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T12
0	1	Covered	T1,T9,T12
1	0	Covered	T76,T228

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T12
1	-	Covered	T1,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T24
DetectSt	168	Covered	T1,T9,T24
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T24
DebounceSt->IdleSt	163	Covered	T75,T76
DetectSt->IdleSt	186	Covered	T24,T40,T67
DetectSt->StableSt	191	Covered	T1,T9,T12
IdleSt->DebounceSt	148	Covered	T1,T9,T24
StableSt->IdleSt	206	Covered	T1,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T9,T24
0	1	Covered	T1,T9,T24
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T24
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T9,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T24,T40,T67
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T24
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	3331	0	0
CntIncr_A	8393152	98440	0	0
CntNoWrap_A	8393152	7740235	0	0
DetectStDropOut_A	8393152	478	0	0
DetectedOut_A	8393152	76140	0	0
DetectedPulseOut_A	8393152	937	0	0
DisabledIdleSt_A	8393152	7317938	0	0
DisabledNoDetection_A	8393152	7320137	0	0
EnterDebounceSt_A	8393152	1668	0	0
EnterDetectSt_A	8393152	1663	0	0
EnterStableSt_A	8393152	937	0	0
PulseIsPulse_A	8393152	937	0	0
StayInStableSt	8393152	75095	0	0
gen_high_event_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	826	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3331	0	0
T1	15395	46	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	54	0	0
T12	0	42	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	36	0	0
T36	0	54	0	0
T40	0	52	0	0
T66	0	50	0	0
T67	0	44	0	0
T68	0	10	0	0
T69	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	98440	0	0
T1	15395	1127	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	1701	0	0
T12	0	1869	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	862	0	0
T36	0	675	0	0
T40	0	1253	0	0
T66	0	1350	0	0
T67	0	1121	0	0
T68	0	390	0	0
T69	0	1132	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7740235	0	0
T1	15395	14925	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	478	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	16103	0	0	0
T24	5079	18	0	0
T40	0	26	0	0
T50	426	0	0	0
T51	431	0	0	0
T67	0	22	0	0
T69	0	25	0	0
T73	408	0	0	0
T86	0	3	0	0
T87	0	6	0	0
T88	0	14	0	0
T90	0	10	0	0
T91	0	9	0	0
T92	0	12	0	0
T101	408	0	0	0
T102	422	0	0	0
T103	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	76140	0	0
T1	15395	3653	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	1843	0	0
T12	0	1328	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	2552	0	0
T37	0	1640	0	0
T66	0	1562	0	0
T68	0	774	0	0
T229	0	993	0	0
T230	0	2195	0	0
T231	0	1018	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	937	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	27	0	0
T12	0	21	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	27	0	0
T37	0	21	0	0
T66	0	25	0	0
T68	0	5	0	0
T229	0	32	0	0
T230	0	30	0	0
T231	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7317938	0	0
T1	15395	8060	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7320137	0	0
T1	15395	8060	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1668	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	27	0	0
T12	0	21	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	18	0	0
T36	0	27	0	0
T40	0	26	0	0
T66	0	25	0	0
T67	0	22	0	0
T68	0	5	0	0
T69	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1663	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	27	0	0
T12	0	21	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	18	0	0
T36	0	27	0	0
T40	0	26	0	0
T66	0	25	0	0
T67	0	22	0	0
T68	0	5	0	0
T69	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	937	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	27	0	0
T12	0	21	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	27	0	0
T37	0	21	0	0
T66	0	25	0	0
T68	0	5	0	0
T229	0	32	0	0
T230	0	30	0	0
T231	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	937	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	27	0	0
T12	0	21	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	27	0	0
T37	0	21	0	0
T66	0	25	0	0
T68	0	5	0	0
T229	0	32	0	0
T230	0	30	0	0
T231	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	75095	0	0
T1	15395	3627	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	1814	0	0
T12	0	1307	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	2518	0	0
T37	0	1617	0	0
T66	0	1537	0	0
T68	0	767	0	0
T229	0	960	0	0
T230	0	2163	0	0
T231	0	995	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	826	0	0
T1	15395	20	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	25	0	0
T12	0	21	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	20	0	0
T37	0	19	0	0
T66	0	25	0	0
T68	0	3	0	0
T229	0	31	0	0
T230	0	28	0	0
T231	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T15,T89,T93
1	0	Covered	T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Covered	T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T7
1	-	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T7
DetectSt	168	Covered	T1,T3,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T7
DebounceSt->IdleSt	163	Covered	T3,T22,T51
DetectSt->IdleSt	186	Covered	T15,T89,T93
DetectSt->StableSt	191	Covered	T1,T3,T7
IdleSt->DebounceSt	148	Covered	T1,T3,T7
StableSt->IdleSt	206	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T22,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T15,T89,T93
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	936	0	0
CntIncr_A	8393152	48511	0	0
CntNoWrap_A	8393152	7742630	0	0
DetectStDropOut_A	8393152	79	0	0
DetectedOut_A	8393152	15084	0	0
DetectedPulseOut_A	8393152	352	0	0
DisabledIdleSt_A	8393152	7372027	0	0
DisabledNoDetection_A	8393152	7373669	0	0
EnterDebounceSt_A	8393152	504	0	0
EnterDetectSt_A	8393152	432	0	0
EnterStableSt_A	8393152	352	0	0
PulseIsPulse_A	8393152	352	0	0
StayInStableSt	8393152	14690	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	308	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	936	0	0
T1	15395	6	0	0
T2	13478	0	0	0
T3	17732	9	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	4	0	0
T8	0	2	0	0
T9	0	4	0	0
T10	0	2	0	0
T12	0	4	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	4	0	0
T22	0	25	0	0
T51	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	48511	0	0
T1	15395	177	0	0
T2	13478	0	0	0
T3	17732	504	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	50	0	0
T8	0	25	0	0
T9	0	158	0	0
T10	0	25	0	0
T12	0	230	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	100	0	0
T22	0	1105	0	0
T51	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7742630	0	0
T1	15395	14965	0	0
T2	13478	13063	0	0
T3	17732	17275	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1482	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4209	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	79	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T10	490	0	0	0
T15	4614	2	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T89	0	2	0	0
T93	0	1	0	0
T94	0	3	0	0
T95	0	1	0	0
T96	0	13	0	0
T97	0	1	0	0
T98	0	4	0	0
T99	0	12	0	0
T100	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	15084	0	0
T1	15395	519	0	0
T2	13478	0	0	0
T3	17732	23	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	6	0	0
T8	0	4	0	0
T9	0	63	0	0
T10	0	3	0	0
T12	0	104	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	0	749	0	0
T23	0	149	0	0
T39	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	352	0	0
T1	15395	3	0	0
T2	13478	0	0	0
T3	17732	4	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	2	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	0	11	0	0
T23	0	4	0	0
T39	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7372027	0	0
T1	15395	11321	0	0
T2	13478	8058	0	0
T3	17732	14100	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1338	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7373669	0	0
T1	15395	11322	0	0
T2	13478	8058	0	0
T3	17732	14100	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1349	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	504	0	0
T1	15395	3	0	0
T2	13478	0	0	0
T3	17732	5	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	2	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	2	0	0
T22	0	14	0	0
T51	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	432	0	0
T1	15395	3	0	0
T2	13478	0	0	0
T3	17732	4	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	2	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	2	0	0
T22	0	11	0	0
T39	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	352	0	0
T1	15395	3	0	0
T2	13478	0	0	0
T3	17732	4	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	2	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	0	11	0	0
T23	0	4	0	0
T39	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	352	0	0
T1	15395	3	0	0
T2	13478	0	0	0
T3	17732	4	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	2	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	0	11	0	0
T23	0	4	0	0
T39	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	14690	0	0
T1	15395	516	0	0
T2	13478	0	0	0
T3	17732	19	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	4	0	0
T8	0	3	0	0
T9	0	61	0	0
T10	0	2	0	0
T12	0	102	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	0	738	0	0
T23	0	145	0	0
T39	0	73	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	308	0	0
T1	15395	3	0	0
T2	13478	0	0	0
T3	17732	4	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	2	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T12	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	0	11	0	0
T23	0	4	0	0
T39	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T9,T24
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T24
1	0	Covered	T1,T9,T12
1	1	Covered	T1,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T24
0	1	Covered	T24,T40,T36
1	0	Covered	T9,T36,T66

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T68
0	1	Covered	T1,T12,T68
1	0	Covered	T36,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T12,T36
1	-	Covered	T1,T12,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T24
DetectSt	168	Covered	T1,T9,T24
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T12,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T24
DebounceSt->IdleSt	163	Covered	T75,T76
DetectSt->IdleSt	186	Covered	T9,T24,T40
DetectSt->StableSt	191	Covered	T1,T12,T36
IdleSt->DebounceSt	148	Covered	T1,T9,T24
StableSt->IdleSt	206	Covered	T1,T12,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T9,T24
0	1	Covered	T1,T9,T24
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T24
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T9,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T9,T24,T40
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T36
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T24
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T36
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T68
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	3198	0	0
CntIncr_A	8393152	96897	0	0
CntNoWrap_A	8393152	7740368	0	0
DetectStDropOut_A	8393152	436	0	0
DetectedOut_A	8393152	79318	0	0
DetectedPulseOut_A	8393152	934	0	0
DisabledIdleSt_A	8393152	7311077	0	0
DisabledNoDetection_A	8393152	7313261	0	0
EnterDebounceSt_A	8393152	1601	0	0
EnterDetectSt_A	8393152	1597	0	0
EnterStableSt_A	8393152	934	0	0
PulseIsPulse_A	8393152	934	0	0
StayInStableSt	8393152	78261	0	0
gen_high_event_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	808	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3198	0	0
T1	15395	46	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	30	0	0
T12	0	6	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	18	0	0
T36	0	56	0	0
T40	0	14	0	0
T66	0	12	0	0
T67	0	12	0	0
T68	0	6	0	0
T69	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	96897	0	0
T1	15395	1219	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	1169	0	0
T12	0	165	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	428	0	0
T36	0	1323	0	0
T40	0	331	0	0
T66	0	386	0	0
T67	0	300	0	0
T68	0	219	0	0
T69	0	756	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7740368	0	0
T1	15395	14925	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	436	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	16103	0	0	0
T24	5079	9	0	0
T36	0	14	0	0
T38	0	8	0	0
T40	0	7	0	0
T50	426	0	0	0
T51	431	0	0	0
T67	0	6	0	0
T69	0	17	0	0
T73	408	0	0	0
T86	0	28	0	0
T90	0	15	0	0
T92	0	25	0	0
T101	408	0	0	0
T102	422	0	0	0
T103	405	0	0	0
T112	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	79318	0	0
T1	15395	3561	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T12	0	146	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	2	0	0
T37	0	1140	0	0
T68	0	366	0	0
T87	0	3078	0	0
T88	0	1402	0	0
T229	0	1725	0	0
T230	0	824	0	0
T231	0	553	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	934	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T12	0	3	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	2	0	0
T37	0	30	0	0
T68	0	3	0	0
T87	0	27	0	0
T88	0	11	0	0
T229	0	24	0	0
T230	0	16	0	0
T231	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7311077	0	0
T1	15395	8060	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7313261	0	0
T1	15395	8060	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1601	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	15	0	0
T12	0	3	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	9	0	0
T36	0	28	0	0
T40	0	7	0	0
T66	0	6	0	0
T67	0	6	0	0
T68	0	3	0	0
T69	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1597	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	15	0	0
T12	0	3	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	9	0	0
T36	0	28	0	0
T40	0	7	0	0
T66	0	6	0	0
T67	0	6	0	0
T68	0	3	0	0
T69	0	17	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	934	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T12	0	3	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	2	0	0
T37	0	30	0	0
T68	0	3	0	0
T87	0	27	0	0
T88	0	11	0	0
T229	0	24	0	0
T230	0	16	0	0
T231	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	934	0	0
T1	15395	23	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T12	0	3	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T36	0	2	0	0
T37	0	30	0	0
T68	0	3	0	0
T87	0	27	0	0
T88	0	11	0	0
T229	0	24	0	0
T230	0	16	0	0
T231	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	78261	0	0
T1	15395	3535	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T12	0	143	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T37	0	1109	0	0
T68	0	363	0	0
T87	0	3044	0	0
T88	0	1391	0	0
T91	0	1741	0	0
T229	0	1700	0	0
T230	0	806	0	0
T231	0	538	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	808	0	0
T1	15395	20	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T12	0	3	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T37	0	29	0	0
T68	0	3	0	0
T87	0	20	0	0
T88	0	11	0	0
T91	0	5	0	0
T229	0	23	0	0
T230	0	14	0	0
T231	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T39,T177,T232
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T75,T233

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T3,T8,T39
DetectSt->IdleSt	186	Covered	T39,T177,T232
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T8,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T39,T177,T232
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	970	0	0
CntIncr_A	8393152	57209	0	0
CntNoWrap_A	8393152	7742596	0	0
DetectStDropOut_A	8393152	56	0	0
DetectedOut_A	8393152	18660	0	0
DetectedPulseOut_A	8393152	405	0	0
DisabledIdleSt_A	8393152	7357438	0	0
DisabledNoDetection_A	8393152	7359096	0	0
EnterDebounceSt_A	8393152	505	0	0
EnterDetectSt_A	8393152	465	0	0
EnterStableSt_A	8393152	405	0	0
PulseIsPulse_A	8393152	405	0	0
StayInStableSt	8393152	18207	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	355	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	970	0	0
T1	15395	2	0	0
T2	13478	4	0	0
T3	17732	7	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	5	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	4	0	0
T22	0	12	0	0
T23	0	9	0	0
T39	0	3	0	0
T55	0	6	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	57209	0	0
T1	15395	57	0	0
T2	13478	282	0	0
T3	17732	370	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	270	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	88	0	0
T22	0	864	0	0
T23	0	773	0	0
T39	0	224	0	0
T55	0	516	0	0
T74	0	304	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7742596	0	0
T1	15395	14969	0	0
T2	13478	13059	0	0
T3	17732	17277	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4209	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	56	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T39	40823	1	0	0
T40	5015	0	0	0
T41	14549	0	0	0
T57	5987	0	0	0
T97	0	6	0	0
T107	422	0	0	0
T108	422	0	0	0
T145	0	2	0	0
T177	0	4	0	0
T209	0	4	0	0
T224	0	3	0	0
T232	0	11	0	0
T234	0	1	0	0
T235	0	6	0	0
T236	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	18660	0	0
T1	15395	175	0	0
T2	13478	74	0	0
T3	17732	34	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	9	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	11	0	0
T22	0	62	0	0
T23	0	88	0	0
T35	0	92	0	0
T55	0	54	0	0
T74	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	405	0	0
T1	15395	1	0	0
T2	13478	2	0	0
T3	17732	3	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	2	0	0
T22	0	6	0	0
T23	0	4	0	0
T35	0	1	0	0
T55	0	3	0	0
T74	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7357438	0	0
T1	15395	11413	0	0
T2	13478	8058	0	0
T3	17732	14100	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7359096	0	0
T1	15395	11414	0	0
T2	13478	8058	0	0
T3	17732	14100	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	505	0	0
T1	15395	1	0	0
T2	13478	2	0	0
T3	17732	4	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	3	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	2	0	0
T22	0	6	0	0
T23	0	5	0	0
T39	0	2	0	0
T55	0	3	0	0
T74	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	465	0	0
T1	15395	1	0	0
T2	13478	2	0	0
T3	17732	3	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	2	0	0
T22	0	6	0	0
T23	0	4	0	0
T39	0	1	0	0
T55	0	3	0	0
T74	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	405	0	0
T1	15395	1	0	0
T2	13478	2	0	0
T3	17732	3	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	2	0	0
T22	0	6	0	0
T23	0	4	0	0
T35	0	1	0	0
T55	0	3	0	0
T74	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	405	0	0
T1	15395	1	0	0
T2	13478	2	0	0
T3	17732	3	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	2	0	0
T22	0	6	0	0
T23	0	4	0	0
T35	0	1	0	0
T55	0	3	0	0
T74	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	18207	0	0
T1	15395	174	0	0
T2	13478	72	0	0
T3	17732	31	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	7	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	9	0	0
T22	0	56	0	0
T23	0	84	0	0
T35	0	91	0	0
T55	0	51	0	0
T74	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	355	0	0
T1	15395	1	0	0
T2	13478	2	0	0
T3	17732	3	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	0	2	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	2	0	0
T22	0	6	0	0
T23	0	4	0	0
T35	0	1	0	0
T55	0	3	0	0
T74	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T9,T24
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T24
1	0	Covered	T1,T9,T12
1	1	Covered	T1,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T24
0	1	Covered	T24,T40,T36
1	0	Covered	T1,T36,T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T66
0	1	Covered	T9,T12,T66
1	0	Covered	T36,T38,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T36
1	-	Covered	T9,T12,T66

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T24
DetectSt	168	Covered	T1,T9,T24
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T12,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T24
DebounceSt->IdleSt	163	Covered	T75,T76
DetectSt->IdleSt	186	Covered	T1,T24,T40
DetectSt->StableSt	191	Covered	T9,T12,T36
IdleSt->DebounceSt	148	Covered	T1,T9,T24
StableSt->IdleSt	206	Covered	T9,T12,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T9,T24
0	1	Covered	T1,T9,T24
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T24
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T9,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T1,T24,T40
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T36
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T24
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T36
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T66
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	3254	0	0
CntIncr_A	8393152	101132	0	0
CntNoWrap_A	8393152	7740312	0	0
DetectStDropOut_A	8393152	528	0	0
DetectedOut_A	8393152	56662	0	0
DetectedPulseOut_A	8393152	800	0	0
DisabledIdleSt_A	8393152	7330863	0	0
DisabledNoDetection_A	8393152	7333090	0	0
EnterDebounceSt_A	8393152	1629	0	0
EnterDetectSt_A	8393152	1625	0	0
EnterStableSt_A	8393152	800	0	0
PulseIsPulse_A	8393152	800	0	0
StayInStableSt	8393152	55782	0	0
gen_high_event_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	705	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3254	0	0
T1	15395	18	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	30	0	0
T12	0	10	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	36	0	0
T36	0	48	0	0
T40	0	26	0	0
T66	0	28	0	0
T67	0	34	0	0
T68	0	30	0	0
T69	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	101132	0	0
T1	15395	642	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	1005	0	0
T12	0	315	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	862	0	0
T36	0	1139	0	0
T40	0	620	0	0
T66	0	756	0	0
T67	0	858	0	0
T68	0	1170	0	0
T69	0	308	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7740312	0	0
T1	15395	14953	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	528	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	16103	0	0	0
T24	5079	18	0	0
T36	0	10	0	0
T38	0	8	0	0
T40	0	13	0	0
T50	426	0	0	0
T51	431	0	0	0
T67	0	17	0	0
T69	0	7	0	0
T73	408	0	0	0
T86	0	16	0	0
T87	0	11	0	0
T88	0	7	0	0
T90	0	31	0	0
T101	408	0	0	0
T102	422	0	0	0
T103	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	56662	0	0
T9	11992	774	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	0	368	0	0
T24	5079	0	0	0
T36	0	2	0	0
T38	0	4	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T66	0	313	0	0
T68	0	2774	0	0
T73	408	0	0	0
T101	408	0	0	0
T112	0	1407	0	0
T229	0	1569	0	0
T230	0	199	0	0
T231	0	1632	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	800	0	0
T9	11992	15	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	0	5	0	0
T24	5079	0	0	0
T36	0	2	0	0
T38	0	4	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T66	0	14	0	0
T68	0	15	0	0
T73	408	0	0	0
T101	408	0	0	0
T112	0	24	0	0
T229	0	32	0	0
T230	0	13	0	0
T231	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7330863	0	0
T1	15395	11210	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7333090	0	0
T1	15395	11213	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1629	0	0
T1	15395	9	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	15	0	0
T12	0	5	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	18	0	0
T36	0	24	0	0
T40	0	13	0	0
T66	0	14	0	0
T67	0	17	0	0
T68	0	15	0	0
T69	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1625	0	0
T1	15395	9	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	15	0	0
T12	0	5	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	18	0	0
T36	0	24	0	0
T40	0	13	0	0
T66	0	14	0	0
T67	0	17	0	0
T68	0	15	0	0
T69	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	800	0	0
T9	11992	15	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	0	5	0	0
T24	5079	0	0	0
T36	0	2	0	0
T38	0	4	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T66	0	14	0	0
T68	0	15	0	0
T73	408	0	0	0
T101	408	0	0	0
T112	0	24	0	0
T229	0	32	0	0
T230	0	13	0	0
T231	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	800	0	0
T9	11992	15	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	0	5	0	0
T24	5079	0	0	0
T36	0	2	0	0
T38	0	4	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T66	0	14	0	0
T68	0	15	0	0
T73	408	0	0	0
T101	408	0	0	0
T112	0	24	0	0
T229	0	32	0	0
T230	0	13	0	0
T231	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	55782	0	0
T9	11992	757	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	0	362	0	0
T24	5079	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T66	0	299	0	0
T68	0	2757	0	0
T73	408	0	0	0
T101	408	0	0	0
T112	0	1383	0	0
T131	0	938	0	0
T229	0	1536	0	0
T230	0	186	0	0
T231	0	1605	0	0
T237	0	590	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	705	0	0
T9	11992	13	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	0	4	0	0
T24	5079	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T51	431	0	0	0
T66	0	14	0	0
T68	0	13	0	0
T73	408	0	0	0
T101	408	0	0	0
T112	0	24	0	0
T131	0	4	0	0
T229	0	31	0	0
T230	0	13	0	0
T231	0	23	0	0
T237	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T3,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T15
0	1	Covered	T15,T74,T176
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T22
0	1	Covered	T2,T3,T22
1	0	Covered	T68,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T22
1	-	Covered	T2,T3,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T15
DetectSt	168	Covered	T2,T3,T15
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T3,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T15
DebounceSt->IdleSt	163	Covered	T15,T39,T35
DetectSt->IdleSt	186	Covered	T15,T74,T176
DetectSt->StableSt	191	Covered	T2,T3,T22
IdleSt->DebounceSt	148	Covered	T2,T3,T15
StableSt->IdleSt	206	Covered	T2,T3,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T15
0	1	Covered	T2,T3,T15
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T15
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T39,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T15
DetectSt	-	-	-	-	1	-	-	Covered	T15,T74,T176
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T22
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T15
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T22
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	816	0	0
CntIncr_A	8393152	48189	0	0
CntNoWrap_A	8393152	7742750	0	0
DetectStDropOut_A	8393152	86	0	0
DetectedOut_A	8393152	13002	0	0
DetectedPulseOut_A	8393152	297	0	0
DisabledIdleSt_A	8393152	7375149	0	0
DisabledNoDetection_A	8393152	7376854	0	0
EnterDebounceSt_A	8393152	429	0	0
EnterDetectSt_A	8393152	387	0	0
EnterStableSt_A	8393152	297	0	0
PulseIsPulse_A	8393152	297	0	0
StayInStableSt	8393152	12683	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	272	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	816	0	0
T2	13478	4	0	0
T3	17732	8	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	4	0	0
T12	0	2	0	0
T14	491	0	0	0
T15	4614	26	0	0
T22	36195	2	0	0
T23	0	8	0	0
T39	0	27	0	0
T47	571	0	0	0
T55	0	6	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	48189	0	0
T2	13478	324	0	0
T3	17732	400	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	152	0	0
T12	0	75	0	0
T14	491	0	0	0
T15	4614	647	0	0
T22	36195	116	0	0
T23	0	464	0	0
T39	0	1332	0	0
T47	571	0	0	0
T55	0	357	0	0
T74	0	314	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7742750	0	0
T1	15395	14971	0	0
T2	13478	13059	0	0
T3	17732	17276	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4187	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	86	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T10	490	0	0	0
T15	4614	12	0	0
T22	36195	0	0	0
T24	5079	0	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T74	0	2	0	0
T96	0	8	0	0
T99	0	5	0	0
T127	0	9	0	0
T176	0	8	0	0
T238	0	1	0	0
T239	0	3	0	0
T240	0	1	0	0
T241	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	13002	0	0
T2	13478	32	0	0
T3	17732	100	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	68	0	0
T12	0	90	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	38	0	0
T23	0	306	0	0
T35	0	62	0	0
T39	0	589	0	0
T47	571	0	0	0
T55	0	214	0	0
T68	0	292	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	297	0	0
T2	13478	2	0	0
T3	17732	4	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	2	0	0
T12	0	1	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	1	0	0
T23	0	4	0	0
T35	0	1	0	0
T39	0	13	0	0
T47	571	0	0	0
T55	0	3	0	0
T68	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7375149	0	0
T1	15395	14971	0	0
T2	13478	8058	0	0
T3	17732	14100	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7376854	0	0
T1	15395	14975	0	0
T2	13478	8058	0	0
T3	17732	14100	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	429	0	0
T2	13478	2	0	0
T3	17732	4	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	2	0	0
T12	0	1	0	0
T14	491	0	0	0
T15	4614	14	0	0
T22	36195	1	0	0
T23	0	4	0	0
T39	0	14	0	0
T47	571	0	0	0
T55	0	3	0	0
T74	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	387	0	0
T2	13478	2	0	0
T3	17732	4	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	2	0	0
T12	0	1	0	0
T14	491	0	0	0
T15	4614	12	0	0
T22	36195	1	0	0
T23	0	4	0	0
T39	0	13	0	0
T47	571	0	0	0
T55	0	3	0	0
T74	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	297	0	0
T2	13478	2	0	0
T3	17732	4	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	2	0	0
T12	0	1	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	1	0	0
T23	0	4	0	0
T35	0	1	0	0
T39	0	13	0	0
T47	571	0	0	0
T55	0	3	0	0
T68	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	297	0	0
T2	13478	2	0	0
T3	17732	4	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	2	0	0
T12	0	1	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	1	0	0
T23	0	4	0	0
T35	0	1	0	0
T39	0	13	0	0
T47	571	0	0	0
T55	0	3	0	0
T68	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	12683	0	0
T2	13478	30	0	0
T3	17732	96	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	66	0	0
T12	0	88	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	37	0	0
T23	0	302	0	0
T35	0	61	0	0
T39	0	576	0	0
T47	571	0	0	0
T55	0	211	0	0
T68	0	288	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	272	0	0
T2	13478	2	0	0
T3	17732	4	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	0	0	0
T9	11992	2	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	1	0	0
T23	0	4	0	0
T35	0	1	0	0
T39	0	13	0	0
T47	571	0	0	0
T55	0	3	0	0
T68	0	3	0	0
T177	0	3	0	0