Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T9,T24
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T24
1	0	Covered	T1,T9,T12
1	1	Covered	T1,T9,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T24
0	1	Covered	T24,T40,T36
1	0	Covered	T1,T9,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T38
0	1	Covered	T12,T37,T38
1	0	Covered	T79,T228

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T37,T38
1	-	Covered	T12,T37,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T24
DetectSt	168	Covered	T1,T9,T24
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T24
DebounceSt->IdleSt	163	Covered	T75,T76
DetectSt->IdleSt	186	Covered	T1,T9,T24
DetectSt->StableSt	191	Covered	T12,T37,T38
IdleSt->DebounceSt	148	Covered	T1,T9,T24
StableSt->IdleSt	206	Covered	T12,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T9,T24
0	1	Covered	T1,T9,T24
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T24
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T9,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T24
DetectSt	-	-	-	-	1	-	-	Covered	T1,T9,T24
DetectSt	-	-	-	-	0	1	-	Covered	T12,T37,T38
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T24
StableSt	-	-	-	-	-	-	1	Covered	T12,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T12,T37,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	3427	0	0
CntIncr_A	8393152	112369	0	0
CntNoWrap_A	8393152	7740139	0	0
DetectStDropOut_A	8393152	487	0	0
DetectedOut_A	8393152	64439	0	0
DetectedPulseOut_A	8393152	883	0	0
DisabledIdleSt_A	8393152	7323949	0	0
DisabledNoDetection_A	8393152	7326171	0	0
EnterDebounceSt_A	8393152	1716	0	0
EnterDetectSt_A	8393152	1712	0	0
EnterStableSt_A	8393152	883	0	0
PulseIsPulse_A	8393152	883	0	0
StayInStableSt	8393152	63471	0	0
gen_high_event_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	793	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	3427	0	0
T1	15395	22	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	54	0	0
T12	0	66	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	36	0	0
T36	0	48	0	0
T40	0	30	0	0
T66	0	14	0	0
T67	0	60	0	0
T68	0	54	0	0
T69	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	112369	0	0
T1	15395	788	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	2108	0	0
T12	0	2640	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	862	0	0
T36	0	1136	0	0
T40	0	709	0	0
T66	0	450	0	0
T67	0	1528	0	0
T68	0	3876	0	0
T69	0	932	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7740139	0	0
T1	15395	14949	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	487	0	0
T10	490	0	0	0
T11	605	0	0	0
T12	16103	0	0	0
T24	5079	18	0	0
T36	0	10	0	0
T40	0	15	0	0
T50	426	0	0	0
T51	431	0	0	0
T67	0	30	0	0
T68	0	12	0	0
T69	0	21	0	0
T73	408	0	0	0
T86	0	23	0	0
T90	0	3	0	0
T91	0	15	0	0
T101	408	0	0	0
T102	422	0	0	0
T103	405	0	0	0
T237	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	64439	0	0
T12	16103	2000	0	0
T20	1759	0	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T37	0	192	0	0
T38	0	2541	0	0
T39	40823	0	0	0
T57	5987	0	0	0
T88	0	1533	0	0
T107	422	0	0	0
T108	422	0	0	0
T112	0	82	0	0
T186	0	748	0	0
T229	0	1847	0	0
T242	0	481	0	0
T243	0	1909	0	0
T244	0	1185	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	883	0	0
T12	16103	33	0	0
T20	1759	0	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T37	0	6	0	0
T38	0	26	0	0
T39	40823	0	0	0
T57	5987	0	0	0
T88	0	25	0	0
T107	422	0	0	0
T108	422	0	0	0
T112	0	13	0	0
T186	0	11	0	0
T229	0	22	0	0
T242	0	5	0	0
T243	0	26	0	0
T244	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7323949	0	0
T1	15395	11210	0	0
T2	13478	13063	0	0
T3	17732	17284	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4213	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7326171	0	0
T1	15395	11213	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1716	0	0
T1	15395	11	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	27	0	0
T12	0	33	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	18	0	0
T36	0	24	0	0
T40	0	15	0	0
T66	0	7	0	0
T67	0	30	0	0
T68	0	27	0	0
T69	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	1712	0	0
T1	15395	11	0	0
T2	13478	0	0	0
T3	17732	0	0	0
T4	484	0	0	0
T5	422	0	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T9	0	27	0	0
T12	0	33	0	0
T13	695	0	0	0
T14	491	0	0	0
T15	4614	0	0	0
T24	0	18	0	0
T36	0	24	0	0
T40	0	15	0	0
T66	0	7	0	0
T67	0	30	0	0
T68	0	27	0	0
T69	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	883	0	0
T12	16103	33	0	0
T20	1759	0	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T37	0	6	0	0
T38	0	26	0	0
T39	40823	0	0	0
T57	5987	0	0	0
T88	0	25	0	0
T107	422	0	0	0
T108	422	0	0	0
T112	0	13	0	0
T186	0	11	0	0
T229	0	22	0	0
T242	0	5	0	0
T243	0	26	0	0
T244	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	883	0	0
T12	16103	33	0	0
T20	1759	0	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T37	0	6	0	0
T38	0	26	0	0
T39	40823	0	0	0
T57	5987	0	0	0
T88	0	25	0	0
T107	422	0	0	0
T108	422	0	0	0
T112	0	13	0	0
T186	0	11	0	0
T229	0	22	0	0
T242	0	5	0	0
T243	0	26	0	0
T244	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	63471	0	0
T12	16103	1964	0	0
T20	1759	0	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T37	0	186	0	0
T38	0	2509	0	0
T39	40823	0	0	0
T57	5987	0	0	0
T88	0	1508	0	0
T107	422	0	0	0
T108	422	0	0	0
T112	0	69	0	0
T186	0	735	0	0
T229	0	1823	0	0
T242	0	474	0	0
T243	0	1881	0	0
T244	0	1175	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	793	0	0
T12	16103	30	0	0
T20	1759	0	0	0
T21	1874	0	0	0
T23	62999	0	0	0
T30	4653	0	0	0
T34	621	0	0	0
T37	0	6	0	0
T38	0	20	0	0
T39	40823	0	0	0
T57	5987	0	0	0
T88	0	25	0	0
T107	422	0	0	0
T108	422	0	0	0
T112	0	13	0	0
T186	0	9	0	0
T229	0	20	0	0
T242	0	3	0	0
T243	0	24	0	0
T244	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T3,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T15
0	1	Covered	T15,T22,T176
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T8
0	1	Covered	T2,T3,T8
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T8
1	-	Covered	T2,T3,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T15
DetectSt	168	Covered	T2,T3,T15
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T15
DebounceSt->IdleSt	163	Covered	T15,T8,T55
DetectSt->IdleSt	186	Covered	T15,T22,T176
DetectSt->StableSt	191	Covered	T2,T3,T8
IdleSt->DebounceSt	148	Covered	T2,T3,T15
StableSt->IdleSt	206	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T15
0	1	Covered	T2,T3,T15
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T15
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T8,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T15
DetectSt	-	-	-	-	1	-	-	Covered	T15,T22,T176
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T8
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T15
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8393152	870	0	0
CntIncr_A	8393152	49152	0	0
CntNoWrap_A	8393152	7742696	0	0
DetectStDropOut_A	8393152	14	0	0
DetectedOut_A	8393152	18277	0	0
DetectedPulseOut_A	8393152	393	0	0
DisabledIdleSt_A	8393152	7366166	0	0
DisabledNoDetection_A	8393152	7367875	0	0
EnterDebounceSt_A	8393152	459	0	0
EnterDetectSt_A	8393152	411	0	0
EnterStableSt_A	8393152	393	0	0
PulseIsPulse_A	8393152	393	0	0
StayInStableSt	8393152	17868	0	0
gen_high_level_sva.HighLevelEvent_A	8393152	7745969	0	0
gen_not_sticky_sva.StableStDropOut_A	8393152	371	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	870	0	0
T2	13478	8	0	0
T3	17732	6	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	3	0	0
T9	11992	0	0	0
T12	0	4	0	0
T14	491	0	0	0
T15	4614	7	0	0
T22	36195	2	0	0
T23	0	26	0	0
T35	0	2	0	0
T47	571	0	0	0
T55	0	23	0	0
T74	0	15	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	49152	0	0
T2	13478	448	0	0
T3	17732	321	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	141	0	0
T9	11992	0	0	0
T12	0	164	0	0
T14	491	0	0	0
T15	4614	169	0	0
T22	36195	154	0	0
T23	0	1807	0	0
T35	0	125	0	0
T47	571	0	0	0
T55	0	1240	0	0
T74	0	1006	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7742696	0	0
T1	15395	14971	0	0
T2	13478	13055	0	0
T3	17732	17278	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	4206	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	14	0	0
T8	15549	0	0	0
T9	11992	0	0	0
T10	490	0	0	0
T15	4614	3	0	0
T22	36195	1	0	0
T24	5079	0	0	0
T47	571	0	0	0
T48	402	0	0	0
T49	449	0	0	0
T50	426	0	0	0
T176	0	1	0	0
T245	0	1	0	0
T246	0	3	0	0
T247	0	3	0	0
T248	0	1	0	0
T249	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	18277	0	0
T2	13478	266	0	0
T3	17732	54	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	21	0	0
T9	11992	0	0	0
T12	0	168	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	708	0	0
T35	0	75	0	0
T47	571	0	0	0
T55	0	950	0	0
T74	0	184	0	0
T177	0	70	0	0
T178	0	637	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	393	0	0
T2	13478	4	0	0
T3	17732	3	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T12	0	2	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	13	0	0
T35	0	1	0	0
T47	571	0	0	0
T55	0	11	0	0
T74	0	7	0	0
T177	0	2	0	0
T178	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7366166	0	0
T1	15395	14971	0	0
T2	13478	8058	0	0
T3	17732	14100	0	0
T4	484	83	0	0
T5	422	21	0	0
T6	2542	538	0	0
T7	6580	1486	0	0
T13	695	294	0	0
T14	491	90	0	0
T15	4614	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7367875	0	0
T1	15395	14975	0	0
T2	13478	8058	0	0
T3	17732	14100	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	459	0	0
T2	13478	4	0	0
T3	17732	3	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	2	0	0
T9	11992	0	0	0
T12	0	2	0	0
T14	491	0	0	0
T15	4614	4	0	0
T22	36195	1	0	0
T23	0	13	0	0
T35	0	1	0	0
T47	571	0	0	0
T55	0	12	0	0
T74	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	411	0	0
T2	13478	4	0	0
T3	17732	3	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T12	0	2	0	0
T14	491	0	0	0
T15	4614	3	0	0
T22	36195	1	0	0
T23	0	13	0	0
T35	0	1	0	0
T47	571	0	0	0
T55	0	11	0	0
T74	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	393	0	0
T2	13478	4	0	0
T3	17732	3	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T12	0	2	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	13	0	0
T35	0	1	0	0
T47	571	0	0	0
T55	0	11	0	0
T74	0	7	0	0
T177	0	2	0	0
T178	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	393	0	0
T2	13478	4	0	0
T3	17732	3	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T12	0	2	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	13	0	0
T35	0	1	0	0
T47	571	0	0	0
T55	0	11	0	0
T74	0	7	0	0
T177	0	2	0	0
T178	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	17868	0	0
T2	13478	262	0	0
T3	17732	51	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	20	0	0
T9	11992	0	0	0
T12	0	166	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	695	0	0
T35	0	74	0	0
T47	571	0	0	0
T55	0	939	0	0
T74	0	177	0	0
T177	0	68	0	0
T178	0	625	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	7745969	0	0
T1	15395	14975	0	0
T2	13478	13067	0	0
T3	17732	17291	0	0
T4	484	84	0	0
T5	422	22	0	0
T6	2542	542	0	0
T7	6580	1499	0	0
T13	695	295	0	0
T14	491	91	0	0
T15	4614	4214	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8393152	371	0	0
T2	13478	4	0	0
T3	17732	3	0	0
T6	2542	0	0	0
T7	6580	0	0	0
T8	15549	1	0	0
T9	11992	0	0	0
T12	0	2	0	0
T14	491	0	0	0
T15	4614	0	0	0
T22	36195	0	0	0
T23	0	13	0	0
T35	0	1	0	0
T47	571	0	0	0
T55	0	11	0	0
T74	0	7	0	0
T177	0	2	0	0
T178	0	12	0	0