Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1187778030	11702	0	0
auto_block_debounce_ctl_rd_A	1187778030	2246	0	0
auto_block_out_ctl_rd_A	1187778030	2478	0	0
com_det_ctl_0_rd_A	1187778030	3442	0	0
com_det_ctl_1_rd_A	1187778030	3559	0	0
com_det_ctl_2_rd_A	1187778030	3536	0	0
com_det_ctl_3_rd_A	1187778030	3445	0	0
com_out_ctl_0_rd_A	1187778030	4053	0	0
com_out_ctl_1_rd_A	1187778030	4147	0	0
com_out_ctl_2_rd_A	1187778030	4004	0	0
com_out_ctl_3_rd_A	1187778030	4176	0	0
com_pre_det_ctl_0_rd_A	1187778030	1751	0	0
com_pre_det_ctl_1_rd_A	1187778030	1731	0	0
com_pre_det_ctl_2_rd_A	1187778030	1633	0	0
com_pre_det_ctl_3_rd_A	1187778030	1805	0	0
com_pre_sel_ctl_0_rd_A	1187778030	3848	0	0
com_pre_sel_ctl_1_rd_A	1187778030	4156	0	0
com_pre_sel_ctl_2_rd_A	1187778030	4098	0	0
com_pre_sel_ctl_3_rd_A	1187778030	4181	0	0
com_sel_ctl_0_rd_A	1187778030	4179	0	0
com_sel_ctl_1_rd_A	1187778030	3940	0	0
com_sel_ctl_2_rd_A	1187778030	4081	0	0
com_sel_ctl_3_rd_A	1187778030	4231	0	0
ec_rst_ctl_rd_A	1187778030	2600	0	0
intr_enable_rd_A	1187778030	2548	0	0
key_intr_ctl_rd_A	1187778030	3648	0	0
key_intr_debounce_ctl_rd_A	1187778030	1788	0	0
key_invert_ctl_rd_A	1187778030	4918	0	0
pin_allowed_ctl_rd_A	1187778030	5764	0	0
pin_out_ctl_rd_A	1187778030	4796	0	0
pin_out_value_rd_A	1187778030	5031	0	0
regwen_rd_A	1187778030	2133	0	0
ulp_ac_debounce_ctl_rd_A	1187778030	1835	0	0
ulp_ctl_rd_A	1187778030	1870	0	0
ulp_lid_debounce_ctl_rd_A	1187778030	1858	0	0
ulp_pwrb_debounce_ctl_rd_A	1187778030	1856	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	11702	0	0
T7	275914	16	0	0
T8	702789	9	0	0
T9	149902	0	0	0
T15	207628	0	0	0
T22	108588	6	0	0
T24	228598	0	0	0
T30	0	7	0	0
T33	0	4	0	0
T35	0	22	0	0
T41	0	29	0	0
T47	160184	0	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T53	0	18	0	0
T57	0	7	0	0
T282	0	15	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	2246	0	0
T8	702789	9	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T23	0	11	0	0
T24	228598	0	0	0
T33	0	28	0	0
T35	0	40	0	0
T42	0	19	0	0
T46	0	15	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	23	0	0
T73	51071	0	0	0
T158	0	10	0	0
T160	0	6	0	0
T283	0	18	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	2478	0	0
T8	702789	8	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T23	0	12	0	0
T24	228598	0	0	0
T33	0	35	0	0
T35	0	42	0	0
T42	0	5	0	0
T46	0	1	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	38	0	0
T73	51071	0	0	0
T158	0	10	0	0
T160	0	15	0	0
T283	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	3442	0	0
T1	384892	30	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	30	0	0
T12	0	39	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	85	0	0
T23	0	66	0	0
T33	0	13	0	0
T35	0	63	0	0
T57	0	37	0	0
T68	0	56	0	0
T74	0	77	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	3559	0	0
T1	384892	37	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	23	0	0
T12	0	42	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	79	0	0
T23	0	43	0	0
T33	0	9	0	0
T35	0	88	0	0
T57	0	40	0	0
T68	0	41	0	0
T74	0	64	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	3536	0	0
T1	384892	37	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	19	0	0
T12	0	35	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	66	0	0
T23	0	64	0	0
T33	0	9	0	0
T35	0	80	0	0
T57	0	41	0	0
T68	0	58	0	0
T74	0	47	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	3445	0	0
T1	384892	44	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	23	0	0
T12	0	26	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	59	0	0
T23	0	60	0	0
T33	0	2	0	0
T35	0	79	0	0
T57	0	33	0	0
T68	0	47	0	0
T74	0	64	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4053	0	0
T1	384892	41	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	42	0	0
T12	0	57	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	93	0	0
T23	0	69	0	0
T33	0	9	0	0
T35	0	62	0	0
T57	0	31	0	0
T68	0	71	0	0
T74	0	54	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4147	0	0
T1	384892	62	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	46	0	0
T12	0	21	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	80	0	0
T23	0	76	0	0
T33	0	13	0	0
T35	0	70	0	0
T57	0	48	0	0
T68	0	55	0	0
T74	0	81	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4004	0	0
T1	384892	34	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	31	0	0
T12	0	22	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	103	0	0
T23	0	65	0	0
T33	0	6	0	0
T35	0	84	0	0
T57	0	32	0	0
T68	0	66	0	0
T74	0	74	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4176	0	0
T1	384892	72	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	52	0	0
T12	0	29	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	63	0	0
T23	0	91	0	0
T33	0	7	0	0
T35	0	76	0	0
T57	0	44	0	0
T68	0	53	0	0
T74	0	53	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1751	0	0
T8	702789	8	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	17	0	0
T35	0	29	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	35	0	0
T73	51071	0	0	0
T81	0	8	0	0
T84	0	20	0	0
T89	0	13	0	0
T150	0	6	0	0
T180	0	13	0	0
T284	0	10	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1731	0	0
T8	702789	28	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	3	0	0
T35	0	38	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	46	0	0
T73	51071	0	0	0
T81	0	11	0	0
T84	0	17	0	0
T89	0	13	0	0
T150	0	18	0	0
T180	0	26	0	0
T284	0	19	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1633	0	0
T8	702789	8	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	14	0	0
T35	0	29	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	40	0	0
T73	51071	0	0	0
T81	0	3	0	0
T84	0	20	0	0
T89	0	22	0	0
T150	0	2	0	0
T180	0	11	0	0
T284	0	21	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1805	0	0
T8	702789	17	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	11	0	0
T35	0	27	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	47	0	0
T73	51071	0	0	0
T81	0	3	0	0
T84	0	18	0	0
T89	0	8	0	0
T150	0	13	0	0
T180	0	15	0	0
T284	0	21	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	3848	0	0
T1	384892	25	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	12	0	0
T12	0	48	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	66	0	0
T23	0	103	0	0
T33	0	13	0	0
T35	0	59	0	0
T57	0	36	0	0
T68	0	48	0	0
T74	0	62	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4156	0	0
T1	384892	56	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	34	0	0
T12	0	42	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	65	0	0
T23	0	51	0	0
T33	0	16	0	0
T35	0	84	0	0
T57	0	49	0	0
T68	0	52	0	0
T74	0	65	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4098	0	0
T1	384892	37	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	22	0	0
T12	0	30	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	77	0	0
T23	0	60	0	0
T33	0	14	0	0
T35	0	52	0	0
T57	0	31	0	0
T68	0	62	0	0
T74	0	78	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4181	0	0
T1	384892	38	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	25	0	0
T12	0	32	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	59	0	0
T23	0	59	0	0
T33	0	3	0	0
T35	0	40	0	0
T57	0	35	0	0
T68	0	51	0	0
T74	0	73	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4179	0	0
T1	384892	62	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	28	0	0
T12	0	35	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	74	0	0
T23	0	66	0	0
T33	0	11	0	0
T35	0	83	0	0
T57	0	34	0	0
T68	0	51	0	0
T74	0	81	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	3940	0	0
T1	384892	54	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	32	0	0
T12	0	26	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	69	0	0
T23	0	89	0	0
T33	0	11	0	0
T35	0	54	0	0
T57	0	37	0	0
T68	0	58	0	0
T74	0	66	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4081	0	0
T1	384892	66	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	45	0	0
T12	0	44	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	57	0	0
T23	0	44	0	0
T33	0	11	0	0
T35	0	54	0	0
T57	0	37	0	0
T68	0	51	0	0
T74	0	76	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4231	0	0
T1	384892	59	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	39	0	0
T12	0	39	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	79	0	0
T23	0	79	0	0
T33	0	22	0	0
T35	0	81	0	0
T57	0	37	0	0
T68	0	40	0	0
T74	0	58	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	2600	0	0
T1	384892	21	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	0	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	27	0	0
T12	0	6	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	0	0	0
T23	0	70	0	0
T35	0	44	0	0
T57	0	36	0	0
T68	0	10	0	0
T74	0	24	0	0
T140	0	9	0	0
T169	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	2548	0	0
T8	702789	22	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	6	0	0
T35	0	20	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	61	0	0
T73	51071	0	0	0
T81	0	13	0	0
T89	0	21	0	0
T150	0	17	0	0
T158	0	17	0	0
T180	0	21	0	0
T284	0	40	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	3648	0	0
T8	702789	39	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T23	0	2	0	0
T24	228598	0	0	0
T33	0	22	0	0
T35	0	45	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	39	0	0
T73	51071	0	0	0
T81	0	12	0	0
T89	0	9	0	0
T150	0	18	0	0
T152	0	1	0	0
T166	0	3	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1788	0	0
T8	702789	10	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	13	0	0
T35	0	44	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	33	0	0
T73	51071	0	0	0
T81	0	10	0	0
T84	0	16	0	0
T89	0	9	0	0
T150	0	5	0	0
T180	0	8	0	0
T284	0	15	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4918	0	0
T2	242604	0	0	0
T3	212787	0	0	0
T4	239899	54	0	0
T5	200267	0	0	0
T6	110932	0	0	0
T7	275914	0	0	0
T8	0	125	0	0
T13	24363	0	0	0
T14	118171	0	0	0
T15	207628	0	0	0
T22	108588	0	0	0
T33	0	24	0	0
T35	0	238	0	0
T57	0	97	0	0
T81	0	16	0	0
T89	0	25	0	0
T285	0	39	0	0
T286	0	64	0	0
T287	0	53	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	5764	0	0
T8	702789	73	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	12	0	0
T35	0	176	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	159	0	0
T73	51071	0	0	0
T81	0	278	0	0
T89	0	12	0	0
T124	0	74	0	0
T150	0	75	0	0
T288	0	37	0	0
T289	0	85	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	4796	0	0
T8	702789	44	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	14	0	0
T35	0	162	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	123	0	0
T73	51071	0	0	0
T81	0	271	0	0
T89	0	19	0	0
T124	0	53	0	0
T150	0	72	0	0
T288	0	27	0	0
T289	0	56	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	5031	0	0
T8	702789	72	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	11	0	0
T35	0	144	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	152	0	0
T73	51071	0	0	0
T81	0	309	0	0
T89	0	8	0	0
T124	0	78	0	0
T150	0	50	0	0
T288	0	55	0	0
T289	0	82	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	2133	0	0
T8	702789	35	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T24	228598	0	0	0
T33	0	13	0	0
T35	0	49	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T57	0	30	0	0
T73	51071	0	0	0
T81	0	9	0	0
T84	0	18	0	0
T89	0	10	0	0
T150	0	17	0	0
T180	0	18	0	0
T284	0	19	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1835	0	0
T8	702789	20	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T20	0	4	0	0
T24	228598	0	0	0
T33	0	13	0	0
T35	0	32	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T54	0	7	0	0
T57	0	49	0	0
T70	0	10	0	0
T73	51071	0	0	0
T81	0	15	0	0
T89	0	8	0	0
T105	0	10	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1870	0	0
T8	702789	14	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T20	0	14	0	0
T24	228598	0	0	0
T33	0	18	0	0
T35	0	21	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T54	0	7	0	0
T57	0	19	0	0
T70	0	8	0	0
T73	51071	0	0	0
T89	0	9	0	0
T105	0	9	0	0
T106	0	6	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1858	0	0
T8	702789	37	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T20	0	7	0	0
T24	228598	0	0	0
T33	0	12	0	0
T35	0	45	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T54	0	11	0	0
T57	0	31	0	0
T70	0	16	0	0
T73	51071	0	0	0
T81	0	10	0	0
T89	0	2	0	0
T105	0	5	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1187778030	1856	0	0
T8	702789	14	0	0
T9	149902	0	0	0
T10	56389	0	0	0
T11	180460	0	0	0
T20	0	5	0	0
T24	228598	0	0	0
T33	0	14	0	0
T35	0	30	0	0
T48	197272	0	0	0
T49	105734	0	0	0
T50	53316	0	0	0
T51	209255	0	0	0
T54	0	2	0	0
T57	0	31	0	0
T70	0	2	0	0
T73	51071	0	0	0
T81	0	20	0	0
T89	0	7	0	0
T105	0	12	0	0