Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T13,T2 |
1 | 0 | Covered | T1,T13,T2 |
1 | 1 | Covered | T8,T20,T21 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T13,T2 |
1 | 0 | Covered | T8,T20,T21 |
1 | 1 | Covered | T1,T13,T2 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
228255 |
0 |
0 |
T1 |
9206601 |
68 |
0 |
0 |
T2 |
6402050 |
64 |
0 |
0 |
T3 |
5762975 |
112 |
0 |
0 |
T4 |
6009575 |
0 |
0 |
0 |
T5 |
5017225 |
0 |
0 |
0 |
T6 |
2950324 |
0 |
0 |
0 |
T7 |
8474820 |
20 |
0 |
0 |
T8 |
4294479 |
36 |
0 |
0 |
T9 |
959372 |
51 |
0 |
0 |
T10 |
56389 |
4 |
0 |
0 |
T11 |
180460 |
0 |
0 |
0 |
T12 |
0 |
52 |
0 |
0 |
T13 |
626450 |
0 |
0 |
0 |
T14 |
2966550 |
0 |
0 |
0 |
T15 |
6367260 |
16 |
0 |
0 |
T22 |
1013481 |
226 |
0 |
0 |
T23 |
0 |
16 |
0 |
0 |
T24 |
1396983 |
17 |
0 |
0 |
T33 |
0 |
30 |
0 |
0 |
T39 |
0 |
216 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
30 |
0 |
0 |
T42 |
0 |
14 |
0 |
0 |
T43 |
0 |
16 |
0 |
0 |
T44 |
0 |
14 |
0 |
0 |
T45 |
0 |
12 |
0 |
0 |
T46 |
0 |
16 |
0 |
0 |
T47 |
803775 |
0 |
0 |
0 |
T48 |
1185642 |
0 |
0 |
0 |
T49 |
636649 |
0 |
0 |
0 |
T50 |
268284 |
0 |
0 |
0 |
T51 |
209255 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
231449 |
0 |
0 |
T1 |
9206601 |
68 |
0 |
0 |
T2 |
6402050 |
64 |
0 |
0 |
T3 |
5762975 |
112 |
0 |
0 |
T4 |
6009575 |
0 |
0 |
0 |
T5 |
5017225 |
0 |
0 |
0 |
T6 |
2950324 |
0 |
0 |
0 |
T7 |
8474820 |
22 |
0 |
0 |
T8 |
3607239 |
36 |
0 |
0 |
T9 |
821462 |
51 |
0 |
0 |
T10 |
490 |
4 |
0 |
0 |
T11 |
605 |
0 |
0 |
0 |
T12 |
0 |
52 |
0 |
0 |
T13 |
626450 |
0 |
0 |
0 |
T14 |
2966550 |
0 |
0 |
0 |
T15 |
6367260 |
16 |
0 |
0 |
T22 |
1013481 |
226 |
0 |
0 |
T23 |
0 |
16 |
0 |
0 |
T24 |
1173464 |
17 |
0 |
0 |
T33 |
0 |
30 |
0 |
0 |
T39 |
0 |
216 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T41 |
0 |
30 |
0 |
0 |
T42 |
0 |
14 |
0 |
0 |
T43 |
0 |
16 |
0 |
0 |
T44 |
0 |
14 |
0 |
0 |
T45 |
0 |
12 |
0 |
0 |
T46 |
0 |
16 |
0 |
0 |
T47 |
803775 |
0 |
0 |
0 |
T48 |
988772 |
0 |
0 |
0 |
T49 |
531364 |
0 |
0 |
0 |
T50 |
215394 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T13,T2 |
1 | 0 | Covered | T1,T13,T2 |
1 | 1 | Covered | T29,T308,T296 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T13,T2 |
1 | 0 | Covered | T29,T308,T296 |
1 | 1 | Covered | T1,T13,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1898 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T13 |
695 |
1 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
16 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1988 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T13 |
24363 |
1 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
16 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T13,T2 |
1 | 0 | Covered | T1,T13,T2 |
1 | 1 | Covered | T29,T308,T296 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T13,T2 |
1 | 0 | Covered | T29,T308,T296 |
1 | 1 | Covered | T1,T13,T2 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1979 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T13 |
24363 |
1 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
16 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1979 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T13 |
695 |
1 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
16 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T7,T8,T20 |
1 | 1 | Covered | T20,T21,T54 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T20,T21,T54 |
1 | 1 | Covered | T7,T8,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
899 |
0 |
0 |
T7 |
6580 |
1 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
992 |
0 |
0 |
T7 |
275914 |
1 |
0 |
0 |
T8 |
702789 |
2 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T7,T8,T20 |
1 | 1 | Covered | T20,T21,T54 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T20,T21,T54 |
1 | 1 | Covered | T7,T8,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
983 |
0 |
0 |
T7 |
275914 |
1 |
0 |
0 |
T8 |
702789 |
2 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
983 |
0 |
0 |
T7 |
6580 |
1 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T7,T8,T20 |
1 | 1 | Covered | T20,T21,T54 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T20,T21,T54 |
1 | 1 | Covered | T7,T8,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
894 |
0 |
0 |
T7 |
6580 |
1 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
985 |
0 |
0 |
T7 |
275914 |
1 |
0 |
0 |
T8 |
702789 |
2 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T7,T8,T20 |
1 | 1 | Covered | T20,T21,T54 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T20,T21,T54 |
1 | 1 | Covered | T7,T8,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
977 |
0 |
0 |
T7 |
275914 |
1 |
0 |
0 |
T8 |
702789 |
2 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
977 |
0 |
0 |
T7 |
6580 |
1 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T7,T8,T20 |
1 | 1 | Covered | T20,T21,T54 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T20,T21,T54 |
1 | 1 | Covered | T7,T8,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
900 |
0 |
0 |
T7 |
6580 |
1 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
989 |
0 |
0 |
T7 |
275914 |
1 |
0 |
0 |
T8 |
702789 |
2 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T7,T8,T20 |
1 | 1 | Covered | T20,T21,T54 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T8,T20 |
1 | 0 | Covered | T20,T21,T54 |
1 | 1 | Covered | T7,T8,T20 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
978 |
0 |
0 |
T7 |
275914 |
1 |
0 |
0 |
T8 |
702789 |
2 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
978 |
0 |
0 |
T7 |
6580 |
1 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
3 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
1 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
1 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T8,T20,T21 |
1 | 0 | Covered | T8,T20,T21 |
1 | 1 | Covered | T8,T20,T21 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T8,T20,T21 |
1 | 0 | Covered | T8,T20,T21 |
1 | 1 | Covered | T8,T20,T21 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
871 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
0 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T56 |
0 |
2 |
0 |
0 |
T70 |
0 |
4 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T72 |
0 |
2 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
965 |
0 |
0 |
T8 |
702789 |
2 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T10 |
56389 |
0 |
0 |
0 |
T11 |
180460 |
0 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T51 |
209255 |
0 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T56 |
0 |
2 |
0 |
0 |
T70 |
0 |
4 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T72 |
0 |
2 |
0 |
0 |
T73 |
51071 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T8,T20,T21 |
1 | 0 | Covered | T8,T20,T21 |
1 | 1 | Covered | T8,T20,T21 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T8,T20,T21 |
1 | 0 | Covered | T8,T20,T21 |
1 | 1 | Covered | T8,T20,T21 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
955 |
0 |
0 |
T8 |
702789 |
2 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T10 |
56389 |
0 |
0 |
0 |
T11 |
180460 |
0 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T51 |
209255 |
0 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T56 |
0 |
2 |
0 |
0 |
T70 |
0 |
4 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T72 |
0 |
2 |
0 |
0 |
T73 |
51071 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
955 |
0 |
0 |
T8 |
15549 |
2 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T10 |
490 |
0 |
0 |
0 |
T11 |
605 |
0 |
0 |
0 |
T20 |
0 |
4 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T41 |
0 |
2 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T51 |
431 |
0 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
T55 |
0 |
2 |
0 |
0 |
T56 |
0 |
2 |
0 |
0 |
T70 |
0 |
4 |
0 |
0 |
T71 |
0 |
2 |
0 |
0 |
T72 |
0 |
2 |
0 |
0 |
T73 |
408 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T20 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T3,T20 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1130 |
0 |
0 |
T1 |
15395 |
3 |
0 |
0 |
T2 |
13478 |
6 |
0 |
0 |
T3 |
17732 |
8 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T39 |
0 |
13 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1227 |
0 |
0 |
T1 |
384892 |
3 |
0 |
0 |
T2 |
242604 |
6 |
0 |
0 |
T3 |
212787 |
8 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T23 |
0 |
6 |
0 |
0 |
T39 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T4,T14,T7 |
1 | 0 | Covered | T4,T14,T7 |
1 | 1 | Covered | T4,T14,T7 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T4,T14,T7 |
1 | 0 | Covered | T4,T14,T7 |
1 | 1 | Covered | T4,T14,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
2662 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
20 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
20 |
0 |
0 |
T8 |
0 |
40 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
20 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T35 |
0 |
60 |
0 |
0 |
T41 |
0 |
60 |
0 |
0 |
T57 |
0 |
20 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
2760 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
20 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
20 |
0 |
0 |
T8 |
0 |
40 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
20 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T35 |
0 |
60 |
0 |
0 |
T41 |
0 |
60 |
0 |
0 |
T57 |
0 |
20 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T4,T14,T7 |
1 | 0 | Covered | T4,T14,T7 |
1 | 1 | Covered | T4,T14,T7 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T4,T14,T7 |
1 | 0 | Covered | T4,T14,T7 |
1 | 1 | Covered | T4,T14,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
2750 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
20 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
20 |
0 |
0 |
T8 |
0 |
40 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
20 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T35 |
0 |
60 |
0 |
0 |
T41 |
0 |
60 |
0 |
0 |
T57 |
0 |
20 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
2750 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
20 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
20 |
0 |
0 |
T8 |
0 |
40 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
20 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T35 |
0 |
60 |
0 |
0 |
T41 |
0 |
60 |
0 |
0 |
T57 |
0 |
20 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T4,T14,T7 |
1 | 0 | Covered | T4,T14,T7 |
1 | 1 | Covered | T7,T22,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T4,T14,T7 |
1 | 0 | Covered | T7,T22,T8 |
1 | 1 | Covered | T4,T14,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
6155 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
1 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
41 |
0 |
0 |
T8 |
0 |
102 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
40 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T41 |
0 |
63 |
0 |
0 |
T57 |
0 |
61 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
6253 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
1 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
41 |
0 |
0 |
T8 |
0 |
102 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
1 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
40 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T41 |
0 |
63 |
0 |
0 |
T57 |
0 |
61 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T4,T14,T7 |
1 | 0 | Covered | T4,T14,T7 |
1 | 1 | Covered | T7,T22,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T4,T14,T7 |
1 | 0 | Covered | T7,T22,T8 |
1 | 1 | Covered | T4,T14,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
6239 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
1 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
41 |
0 |
0 |
T8 |
0 |
102 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
1 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
40 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T41 |
0 |
63 |
0 |
0 |
T57 |
0 |
61 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
6239 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
1 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
41 |
0 |
0 |
T8 |
0 |
102 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
40 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T41 |
0 |
63 |
0 |
0 |
T57 |
0 |
61 |
0 |
0 |
T58 |
0 |
1 |
0 |
0 |
T59 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T13 |
1 | 0 | Covered | T1,T4,T13 |
1 | 1 | Covered | T7,T22,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T13 |
1 | 0 | Covered | T7,T22,T8 |
1 | 1 | Covered | T1,T4,T13 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7352 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
1 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
43 |
0 |
0 |
T13 |
695 |
1 |
0 |
0 |
T14 |
491 |
1 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
56 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7447 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
1 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
43 |
0 |
0 |
T13 |
24363 |
1 |
0 |
0 |
T14 |
118171 |
1 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
56 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T13 |
1 | 0 | Covered | T1,T4,T13 |
1 | 1 | Covered | T7,T22,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T4,T13 |
1 | 0 | Covered | T7,T22,T8 |
1 | 1 | Covered | T1,T4,T13 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7433 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
1 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
43 |
0 |
0 |
T13 |
24363 |
1 |
0 |
0 |
T14 |
118171 |
1 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
56 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7433 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
1 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
43 |
0 |
0 |
T13 |
695 |
1 |
0 |
0 |
T14 |
491 |
1 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
56 |
0 |
0 |
T47 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T8 |
1 | 0 | Covered | T7,T22,T8 |
1 | 1 | Covered | T7,T22,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T8 |
1 | 0 | Covered | T7,T22,T8 |
1 | 1 | Covered | T7,T22,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
6039 |
0 |
0 |
T7 |
6580 |
40 |
0 |
0 |
T8 |
15549 |
100 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
40 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T41 |
0 |
60 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T53 |
0 |
20 |
0 |
0 |
T57 |
0 |
60 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
T62 |
0 |
20 |
0 |
0 |
T63 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
6144 |
0 |
0 |
T7 |
275914 |
40 |
0 |
0 |
T8 |
702789 |
100 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
40 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T41 |
0 |
60 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T53 |
0 |
20 |
0 |
0 |
T57 |
0 |
60 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
T62 |
0 |
20 |
0 |
0 |
T63 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T8 |
1 | 0 | Covered | T7,T22,T8 |
1 | 1 | Covered | T7,T22,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T8 |
1 | 0 | Covered | T7,T22,T8 |
1 | 1 | Covered | T7,T22,T8 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
6127 |
0 |
0 |
T7 |
275914 |
40 |
0 |
0 |
T8 |
702789 |
100 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
40 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T41 |
0 |
60 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
T53 |
0 |
20 |
0 |
0 |
T57 |
0 |
60 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
T62 |
0 |
20 |
0 |
0 |
T63 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
6127 |
0 |
0 |
T7 |
6580 |
40 |
0 |
0 |
T8 |
15549 |
100 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
40 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
20 |
0 |
0 |
T41 |
0 |
60 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
T53 |
0 |
20 |
0 |
0 |
T57 |
0 |
60 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
T62 |
0 |
20 |
0 |
0 |
T63 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T6,T8,T11 |
1 | 0 | Covered | T6,T8,T11 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T6,T8,T11 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T6,T8,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
918 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
1 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1010 |
0 |
0 |
T6 |
110932 |
2 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
702789 |
1 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T6,T8,T11 |
1 | 0 | Covered | T6,T8,T11 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T6,T8,T11 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T6,T8,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1000 |
0 |
0 |
T6 |
110932 |
2 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
702789 |
1 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1000 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
15549 |
1 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
0 |
0 |
0 |
T23 |
0 |
1 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T57 |
0 |
1 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
T65 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T308 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T308 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1936 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
2027 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
2 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T308 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T308 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
2018 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
2 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
2018 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
2 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T23 |
1 | 0 | Covered | T7,T22,T23 |
1 | 1 | Covered | T7,T22,T23 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T23 |
1 | 0 | Covered | T7,T22,T23 |
1 | 1 | Covered | T7,T22,T23 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1225 |
0 |
0 |
T7 |
6580 |
4 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
4 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T33 |
0 |
9 |
0 |
0 |
T41 |
0 |
9 |
0 |
0 |
T42 |
0 |
4 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1320 |
0 |
0 |
T7 |
275914 |
5 |
0 |
0 |
T8 |
702789 |
0 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
4 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T33 |
0 |
9 |
0 |
0 |
T41 |
0 |
9 |
0 |
0 |
T42 |
0 |
4 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T23 |
1 | 0 | Covered | T7,T22,T23 |
1 | 1 | Covered | T7,T22,T23 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T23 |
1 | 0 | Covered | T7,T22,T23 |
1 | 1 | Covered | T7,T22,T23 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1311 |
0 |
0 |
T7 |
275914 |
4 |
0 |
0 |
T8 |
702789 |
0 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
4 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T33 |
0 |
9 |
0 |
0 |
T41 |
0 |
9 |
0 |
0 |
T42 |
0 |
4 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1311 |
0 |
0 |
T7 |
6580 |
4 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
4 |
0 |
0 |
T23 |
0 |
5 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T33 |
0 |
9 |
0 |
0 |
T41 |
0 |
9 |
0 |
0 |
T42 |
0 |
4 |
0 |
0 |
T43 |
0 |
5 |
0 |
0 |
T44 |
0 |
4 |
0 |
0 |
T45 |
0 |
4 |
0 |
0 |
T46 |
0 |
5 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T23 |
1 | 0 | Covered | T7,T22,T23 |
1 | 1 | Covered | T7,T22,T23 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T23 |
1 | 0 | Covered | T7,T22,T23 |
1 | 1 | Covered | T7,T22,T23 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1069 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
3 |
0 |
0 |
T23 |
0 |
3 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T41 |
0 |
6 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
3 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1162 |
0 |
0 |
T7 |
275914 |
3 |
0 |
0 |
T8 |
702789 |
0 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
3 |
0 |
0 |
T23 |
0 |
3 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T41 |
0 |
6 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
3 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T23 |
1 | 0 | Covered | T7,T22,T23 |
1 | 1 | Covered | T7,T22,T23 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T7,T22,T23 |
1 | 0 | Covered | T7,T22,T23 |
1 | 1 | Covered | T7,T22,T23 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1151 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
702789 |
0 |
0 |
0 |
T9 |
149902 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T22 |
108588 |
3 |
0 |
0 |
T23 |
0 |
3 |
0 |
0 |
T24 |
228598 |
0 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T41 |
0 |
6 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
3 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
160184 |
0 |
0 |
0 |
T48 |
197272 |
0 |
0 |
0 |
T49 |
105734 |
0 |
0 |
0 |
T50 |
53316 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1151 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
15549 |
0 |
0 |
0 |
T9 |
11992 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T22 |
36195 |
3 |
0 |
0 |
T23 |
0 |
3 |
0 |
0 |
T24 |
5079 |
0 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T41 |
0 |
6 |
0 |
0 |
T42 |
0 |
3 |
0 |
0 |
T43 |
0 |
3 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
T45 |
0 |
2 |
0 |
0 |
T46 |
0 |
3 |
0 |
0 |
T47 |
571 |
0 |
0 |
0 |
T48 |
402 |
0 |
0 |
0 |
T49 |
449 |
0 |
0 |
0 |
T50 |
426 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7165 |
0 |
0 |
T1 |
15395 |
54 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
53 |
0 |
0 |
T12 |
0 |
75 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
58 |
0 |
0 |
T40 |
0 |
50 |
0 |
0 |
T66 |
0 |
56 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
65 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7261 |
0 |
0 |
T1 |
384892 |
54 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
53 |
0 |
0 |
T12 |
0 |
75 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
58 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
56 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
65 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7254 |
0 |
0 |
T1 |
384892 |
54 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
53 |
0 |
0 |
T12 |
0 |
75 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
58 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
56 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
65 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7254 |
0 |
0 |
T1 |
15395 |
54 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
53 |
0 |
0 |
T12 |
0 |
75 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
58 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
56 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
65 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7209 |
0 |
0 |
T1 |
15395 |
54 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
93 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
50 |
0 |
0 |
T66 |
0 |
81 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
67 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7304 |
0 |
0 |
T1 |
384892 |
54 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
93 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
81 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
67 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7295 |
0 |
0 |
T1 |
384892 |
54 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
93 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
81 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
67 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7295 |
0 |
0 |
T1 |
15395 |
54 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
93 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
81 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
67 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7342 |
0 |
0 |
T1 |
15395 |
77 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
65 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
50 |
0 |
0 |
T66 |
0 |
67 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
55 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7442 |
0 |
0 |
T1 |
384892 |
77 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
65 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
67 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
55 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7433 |
0 |
0 |
T1 |
384892 |
77 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
65 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
67 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
55 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7433 |
0 |
0 |
T1 |
15395 |
77 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
65 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
67 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
55 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7248 |
0 |
0 |
T1 |
15395 |
77 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
50 |
0 |
0 |
T66 |
0 |
81 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
70 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7342 |
0 |
0 |
T1 |
384892 |
77 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
81 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
70 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7332 |
0 |
0 |
T1 |
384892 |
77 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
81 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
70 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7332 |
0 |
0 |
T1 |
15395 |
77 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T36 |
0 |
85 |
0 |
0 |
T40 |
0 |
51 |
0 |
0 |
T66 |
0 |
81 |
0 |
0 |
T67 |
0 |
51 |
0 |
0 |
T68 |
0 |
70 |
0 |
0 |
T69 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1138 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1232 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1221 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1221 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T75,T76,T308 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T75,T76,T308 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1117 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1210 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T75,T76,T308 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T75,T76,T308 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1199 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1199 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1139 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1233 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1222 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1222 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1166 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1260 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T9,T24 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T9,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1251 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
0 |
0 |
0 |
T3 |
212787 |
0 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1251 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
0 |
0 |
0 |
T3 |
17732 |
0 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
0 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T36 |
0 |
8 |
0 |
0 |
T40 |
0 |
1 |
0 |
0 |
T66 |
0 |
1 |
0 |
0 |
T67 |
0 |
1 |
0 |
0 |
T68 |
0 |
3 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7879 |
0 |
0 |
T1 |
15395 |
54 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
53 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7975 |
0 |
0 |
T1 |
384892 |
54 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
53 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7964 |
0 |
0 |
T1 |
384892 |
54 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
53 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7964 |
0 |
0 |
T1 |
15395 |
54 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
53 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7833 |
0 |
0 |
T1 |
15395 |
54 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
93 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7926 |
0 |
0 |
T1 |
384892 |
54 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
93 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7916 |
0 |
0 |
T1 |
384892 |
54 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
93 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7916 |
0 |
0 |
T1 |
15395 |
54 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
93 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
8005 |
0 |
0 |
T1 |
15395 |
77 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
65 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
8098 |
0 |
0 |
T1 |
384892 |
77 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
65 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
8089 |
0 |
0 |
T1 |
384892 |
77 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
65 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
8089 |
0 |
0 |
T1 |
15395 |
77 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
65 |
0 |
0 |
T12 |
0 |
91 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7868 |
0 |
0 |
T1 |
15395 |
77 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7962 |
0 |
0 |
T1 |
384892 |
77 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T9,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T9,T24 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
7951 |
0 |
0 |
T1 |
384892 |
77 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
7951 |
0 |
0 |
T1 |
15395 |
77 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
80 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
51 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1841 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1934 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1924 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1924 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1783 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1872 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1861 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1861 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1779 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1872 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1862 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1862 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1756 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1849 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1839 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1839 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1830 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1922 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1912 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1912 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
2 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
14 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1739 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1834 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1824 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1824 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1753 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1846 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1835 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1835 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1774 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1863 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T75,T76,T29 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T4,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T76,T29 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T4,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1187778030 |
1858 |
0 |
0 |
T1 |
384892 |
4 |
0 |
0 |
T2 |
242604 |
4 |
0 |
0 |
T3 |
212787 |
7 |
0 |
0 |
T4 |
239899 |
0 |
0 |
0 |
T5 |
200267 |
0 |
0 |
0 |
T6 |
110932 |
0 |
0 |
0 |
T7 |
275914 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
24363 |
0 |
0 |
0 |
T14 |
118171 |
0 |
0 |
0 |
T15 |
207628 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
8642903 |
1858 |
0 |
0 |
T1 |
15395 |
4 |
0 |
0 |
T2 |
13478 |
4 |
0 |
0 |
T3 |
17732 |
7 |
0 |
0 |
T4 |
484 |
0 |
0 |
0 |
T5 |
422 |
0 |
0 |
0 |
T6 |
2542 |
0 |
0 |
0 |
T7 |
6580 |
0 |
0 |
0 |
T8 |
0 |
2 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
695 |
0 |
0 |
0 |
T14 |
491 |
0 |
0 |
0 |
T15 |
4614 |
1 |
0 |
0 |
T22 |
0 |
13 |
0 |
0 |
T24 |
0 |
1 |
0 |
0 |
T39 |
0 |
18 |
0 |
0 |