| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| sysrst_ctrl_combo_detect_det_cg_0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_detect_det_cg_1 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_detect_det_cg_2 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_detect_det_cg_3 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_detect_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 15 | 1 | T99 | 14 | T290 | 1 | - | - | ||||
| mid_range | 398 | 1 | T38 | 1 | T32 | 9 | T95 | 1 | ||||
| min_range | 574 | 1 | T2 | 14 | T13 | 1 | T16 | 7 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 25 | 1 | T386 | 4 | T197 | 2 | T387 | 9 | ||||
| mid_range | 450 | 1 | T32 | 9 | T127 | 6 | T55 | 1 | ||||
| min_range | 512 | 1 | T2 | 14 | T13 | 1 | T16 | 7 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 9 | 1 | T248 | 2 | T100 | 1 | T81 | 2 | ||||
| mid_range | 405 | 1 | T2 | 14 | T55 | 1 | T77 | 7 | ||||
| min_range | 573 | 1 | T13 | 1 | T16 | 7 | T8 | 6 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 26 | 1 | T32 | 9 | T249 | 2 | T197 | 2 | ||||
| mid_range | 348 | 1 | T31 | 1 | T360 | 5 | T269 | 5 | ||||
| min_range | 613 | 1 | T2 | 14 | T13 | 1 | T16 | 7 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |