Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 99.33 96.81 100.00 97.44 98.74 99.61 94.30


Total tests in report: 909
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
50.98 50.98 67.08 67.08 48.96 48.96 86.30 86.30 23.08 23.08 69.28 69.28 57.61 57.61 4.56 4.56 /workspace/coverage/default/13.sysrst_ctrl_stress_all.621876597
67.60 16.62 84.19 17.11 73.08 24.12 92.47 6.16 40.38 17.31 84.81 15.53 78.52 20.91 19.77 15.21 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4060933595
75.54 7.94 89.21 5.02 80.16 7.08 95.43 2.97 53.21 12.82 89.17 4.36 87.57 9.06 34.04 14.27 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1019997973
80.01 4.47 89.92 0.71 81.14 0.99 96.00 0.57 56.41 3.21 89.50 0.33 88.44 0.87 58.67 24.63 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2138443673
83.81 3.79 94.94 5.02 88.78 7.63 97.37 1.37 58.97 2.56 94.57 5.06 91.71 3.28 60.31 1.64 /workspace/coverage/default/7.sysrst_ctrl_stress_all.1147973452
87.01 3.20 96.36 1.42 90.67 1.90 97.37 0.00 75.64 16.67 96.12 1.55 92.49 0.77 60.41 0.10 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3444601827
89.35 2.34 97.39 1.03 91.41 0.73 97.37 0.00 84.62 8.97 96.89 0.78 95.18 2.70 62.59 2.18 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.4281140297
90.80 1.46 97.48 0.09 91.73 0.33 97.37 0.00 85.90 1.28 97.01 0.11 95.28 0.10 70.86 8.28 /workspace/coverage/default/40.sysrst_ctrl_stress_all.3940323729
92.06 1.25 97.56 0.07 93.00 1.26 98.06 0.68 85.90 0.00 97.12 0.11 95.38 0.10 77.40 6.54 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1645973837
93.11 1.05 98.17 0.62 93.78 0.78 98.17 0.11 87.82 1.92 97.45 0.33 96.44 1.06 79.93 2.53 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.848920190
93.78 0.67 98.38 0.21 94.06 0.28 98.17 0.00 89.74 1.92 97.78 0.33 97.30 0.87 81.02 1.09 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2818751239
94.22 0.44 98.58 0.21 94.19 0.13 98.17 0.00 91.67 1.92 97.89 0.11 97.59 0.29 81.42 0.40 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.40096440
94.65 0.43 98.68 0.09 94.24 0.05 98.17 0.00 92.95 1.28 98.00 0.11 97.78 0.19 82.71 1.29 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3831674797
95.01 0.36 98.71 0.04 94.26 0.03 98.17 0.00 92.95 0.00 98.04 0.04 97.78 0.00 85.13 2.43 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1402498325
95.31 0.30 98.71 0.00 94.31 0.05 98.17 0.00 92.95 0.00 98.04 0.00 97.78 0.00 87.22 2.08 /workspace/coverage/default/44.sysrst_ctrl_stress_all.2198528203
95.59 0.28 98.71 0.00 94.34 0.03 99.77 1.60 92.95 0.00 98.04 0.00 97.88 0.10 87.46 0.25 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2456623354
95.84 0.25 98.81 0.09 94.41 0.08 99.77 0.00 94.23 1.28 98.15 0.11 98.07 0.19 87.46 0.00 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2683320673
96.02 0.18 98.88 0.07 94.54 0.13 99.77 0.00 94.87 0.64 98.26 0.11 98.36 0.29 87.46 0.00 /workspace/coverage/default/23.sysrst_ctrl_stress_all.2619727383
96.19 0.17 98.92 0.04 94.54 0.00 99.77 0.00 94.87 0.00 98.26 0.00 98.36 0.00 88.60 1.14 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2678805551
96.34 0.15 98.92 0.00 95.48 0.94 99.77 0.00 94.87 0.00 98.26 0.00 98.36 0.00 88.70 0.10 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.321372395
96.48 0.14 99.01 0.09 95.50 0.03 99.77 0.00 95.51 0.64 98.41 0.15 98.46 0.10 88.70 0.00 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.1229263042
96.62 0.14 99.01 0.00 95.50 0.00 99.77 0.00 95.51 0.00 98.41 0.00 98.46 0.00 89.69 0.99 /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2471382189
96.76 0.13 99.05 0.04 95.53 0.03 99.77 0.00 96.15 0.64 98.45 0.04 98.55 0.10 89.79 0.10 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3112029537
96.88 0.12 99.09 0.04 95.55 0.03 99.77 0.00 96.79 0.64 98.48 0.04 98.65 0.10 89.79 0.00 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1398392985
97.00 0.12 99.12 0.04 95.58 0.03 99.77 0.00 97.44 0.64 98.52 0.04 98.75 0.10 89.79 0.00 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1794388948
97.11 0.11 99.12 0.00 95.68 0.10 99.77 0.00 97.44 0.00 98.52 0.00 99.33 0.58 89.89 0.10 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2522241408
97.19 0.08 99.12 0.00 95.68 0.00 99.77 0.00 97.44 0.00 98.52 0.00 99.33 0.00 90.49 0.59 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3373438643
97.27 0.08 99.12 0.00 95.68 0.00 99.77 0.00 97.44 0.00 98.52 0.00 99.33 0.00 91.03 0.55 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3269896291
97.34 0.07 99.16 0.04 95.73 0.05 99.77 0.00 97.44 0.00 98.60 0.07 99.42 0.10 91.28 0.25 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2981994324
97.41 0.07 99.20 0.04 95.88 0.15 99.77 0.00 97.44 0.00 98.67 0.07 99.61 0.19 91.28 0.00 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1631816748
97.47 0.06 99.20 0.00 96.31 0.43 99.77 0.00 97.44 0.00 98.67 0.00 99.61 0.00 91.28 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1210392682
97.53 0.06 99.22 0.02 96.31 0.00 99.77 0.00 97.44 0.00 98.67 0.00 99.61 0.00 91.67 0.40 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2734816290
97.58 0.05 99.27 0.06 96.39 0.08 100.00 0.23 97.44 0.00 98.67 0.00 99.61 0.00 91.67 0.00 /workspace/coverage/default/12.sysrst_ctrl_alert_test.1399534083
97.63 0.05 99.27 0.00 96.71 0.33 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 91.67 0.00 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1064291811
97.67 0.04 99.27 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 91.97 0.30 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1013386611
97.70 0.04 99.27 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 92.22 0.25 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.949688532
97.73 0.03 99.27 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 92.42 0.20 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3399677454
97.76 0.03 99.27 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 92.62 0.20 /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.36889612
97.79 0.03 99.27 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 92.81 0.20 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2778196954
97.81 0.02 99.27 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 92.96 0.15 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.566983425
97.83 0.02 99.27 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 93.11 0.15 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.121080288
97.85 0.02 99.27 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 93.26 0.15 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1578219083
97.87 0.02 99.29 0.02 96.71 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 93.36 0.10 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1083653214
97.89 0.02 99.33 0.04 96.71 0.00 100.00 0.00 97.44 0.00 98.74 0.07 99.61 0.00 93.36 0.00 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.754255207
97.90 0.01 99.33 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.46 0.10 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1104751829
97.91 0.01 99.33 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.56 0.10 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.670988212
97.93 0.01 99.33 0.00 96.71 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.66 0.10 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1022415879
97.94 0.01 99.33 0.00 96.79 0.08 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.66 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.627751058
97.95 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.71 0.05 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.302906670
97.95 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.76 0.05 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1955675752
97.96 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.81 0.05 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.853416830
97.97 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.86 0.05 /workspace/coverage/default/17.sysrst_ctrl_combo_detect.893059267
97.97 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.90 0.05 /workspace/coverage/default/17.sysrst_ctrl_stress_all.3694544058
97.98 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 93.95 0.05 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2732545924
97.99 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 94.00 0.05 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.525095070
98.00 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 94.05 0.05 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1483176937
98.00 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 94.10 0.05 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.492380999
98.01 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 94.15 0.05 /workspace/coverage/default/43.sysrst_ctrl_stress_all.3350516556
98.02 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 94.20 0.05 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.375997430
98.02 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 94.25 0.05 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.745902205
98.03 0.01 99.33 0.00 96.79 0.00 100.00 0.00 97.44 0.00 98.74 0.00 99.61 0.00 94.30 0.05 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3970119023

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.152401729
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1116563258
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1773017889
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1491017467
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2929329704
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1319678910
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.976842672
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1936447234
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1345340030
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.916787595
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1302758133
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3221435180
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2784633796
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3017443738
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3253244252
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2116414879
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153628386
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.153864091
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2123445698
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1387475205
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.672146625
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2483809210
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1688588572
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1183026306
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1954193670
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2745844417
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2422282568
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.396797936
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.629667738
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3790872406
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3151292244
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2640272509
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.960528687
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.134432635
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3548800365
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3445009298
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.916910138
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2128876046
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.489724840
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1421345853
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1094070977
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3510724708
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1431368101
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.719399537
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4174670295
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1421505932
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2843327690
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.736296017
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3188497642
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.463611750
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.641686534
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3855943004
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1519538976
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.258209785
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1922412837
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.767289970
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4211114254
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1864032435
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.861522164
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.507769121
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.28936351
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1509567361
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3636809115
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1264828024
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.873788103
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.4245601819
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3627702842
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1058423773
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2440611659
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3006362340
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3145311447
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3799146921
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2923551176
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3292361008
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3982127679
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2617638586
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1965251511
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1568454756
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3251768830
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4130246087
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2091342177
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1319388143
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.148751729
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4245584922
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3172801858
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.316855805
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2041763585
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3581309683
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.4097619283
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2826467120
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3843869065
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4044500739
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.271287408
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2511656234
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4215981044
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3507390312
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1690481388
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.684450333
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3388887020
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/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2646145607
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.123042586
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3312839629
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3684753896
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.706674848
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1575010046
/workspace/coverage/default/43.sysrst_ctrl_smoke.327726601
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.836671324
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4247261436
/workspace/coverage/default/44.sysrst_ctrl_alert_test.1988442772
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3256349259
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.908091451
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.814869459
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1105626113
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3759391279
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1329854220
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.4018513433
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4003085180
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1421098463
/workspace/coverage/default/44.sysrst_ctrl_smoke.2112066094
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1625079992
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2316746712
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3735568548
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3467210652
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3374764802
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.1732870026
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3587962472
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3591858310
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.56725139
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.141962559
/workspace/coverage/default/45.sysrst_ctrl_smoke.2640011333
/workspace/coverage/default/45.sysrst_ctrl_stress_all.1308358906
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4190377414
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1503045738
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1815305210
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3951002307
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3394163132
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1096068038
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1767685284
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.1113555547
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1705341979
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1481973404
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2588599602
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1228554042
/workspace/coverage/default/46.sysrst_ctrl_smoke.3664103212
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2078849480
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1550620422
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.187974619
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2977775312
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1464441845
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3719531944
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1684569704
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1611615642
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3770604161
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.310738297
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1178929786
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2745314602
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3345509841
/workspace/coverage/default/47.sysrst_ctrl_smoke.2147382163
/workspace/coverage/default/47.sysrst_ctrl_stress_all.952413965
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4068009545
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1838724027
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3424420095
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2561225453
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3259938452
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1902699725
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3251588705
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1203779451
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2943836408
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1636516813
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3282634224
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.341161980
/workspace/coverage/default/48.sysrst_ctrl_smoke.2981783825
/workspace/coverage/default/48.sysrst_ctrl_stress_all.840305386
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1045752821
/workspace/coverage/default/49.sysrst_ctrl_alert_test.17663370
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2306060744
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.446544662
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.539532839
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3154859634
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2767798235
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.760565818
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3461520883
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1248127368
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2059608611
/workspace/coverage/default/49.sysrst_ctrl_smoke.1942711231
/workspace/coverage/default/49.sysrst_ctrl_stress_all.784927972
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.401429088
/workspace/coverage/default/5.sysrst_ctrl_alert_test.765926787
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.4035150508
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3655304910
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.720206108
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1010405413
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.551172007
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.19119748
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1448881097
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1686239514
/workspace/coverage/default/5.sysrst_ctrl_smoke.3487228035
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2169224971
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3706350025
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2909048118
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3205581156
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.114252662
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.163059385
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.876167317
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4015007670
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2288658210
/workspace/coverage/default/6.sysrst_ctrl_alert_test.2756588555
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1473251076
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1557194883
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1380732183
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3178283320
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.787596266
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1041062220
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1394563945
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1493776478
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3698389694
/workspace/coverage/default/6.sysrst_ctrl_smoke.1474304906
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1392921449
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2699930701
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4027581147
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2319623087
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2300582509
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1905086103
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.737908538
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1344531282
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1494329444
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1779059517
/workspace/coverage/default/7.sysrst_ctrl_alert_test.543618965
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.250169132
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.2648932196
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1339989978
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.148075963
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2083965941
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.406674544
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.816352973
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2925395305
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2972823516
/workspace/coverage/default/7.sysrst_ctrl_smoke.2078573174
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3350615128
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4145034052
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2686413420
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2827896587
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2994897804
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2451678340
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1764850908
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1901583507
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3487497343
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1765026418
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2479405647
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1448201737
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2099768329
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.2172865741
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2970932389
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1933808691
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3357758187
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.746413620
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.991807884
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.940056666
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2164494124
/workspace/coverage/default/8.sysrst_ctrl_smoke.3178752625
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3603602723
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4176374063
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2129422796
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.751491142
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1892063649
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1531710210
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1138748585
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2772830318
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.564227984
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.228572272
/workspace/coverage/default/9.sysrst_ctrl_alert_test.500813548
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1198520248
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1554278569
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.4017192656
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.3228825739
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.53910208
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2988533018
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.798689719
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3625182519
/workspace/coverage/default/9.sysrst_ctrl_smoke.122709080
/workspace/coverage/default/9.sysrst_ctrl_stress_all.886144170
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2555172691
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2253178689
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2945610293
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3821095454
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3018420730
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3044587550
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.280446617
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1369313966



Total test records in report: 909
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.4028686438 Jul 02 07:50:57 AM PDT 24 Jul 02 07:51:10 AM PDT 24 2471253269 ps
T1 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2144058145 Jul 02 07:51:40 AM PDT 24 Jul 02 07:51:47 AM PDT 24 5607068326 ps
T5 /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.497879334 Jul 02 07:50:57 AM PDT 24 Jul 02 07:51:07 AM PDT 24 2458898995 ps
T2 /workspace/coverage/default/19.sysrst_ctrl_combo_detect.115038380 Jul 02 07:50:51 AM PDT 24 Jul 02 07:58:22 AM PDT 24 165898041538 ps
T13 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1197444248 Jul 02 07:51:16 AM PDT 24 Jul 02 07:52:33 AM PDT 24 28833836084 ps
T3 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1366093996 Jul 02 07:50:42 AM PDT 24 Jul 02 07:50:49 AM PDT 24 5295947909 ps
T6 /workspace/coverage/default/13.sysrst_ctrl_stress_all.621876597 Jul 02 07:50:44 AM PDT 24 Jul 02 07:51:08 AM PDT 24 15335338677 ps
T14 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1302038881 Jul 02 07:49:49 AM PDT 24 Jul 02 07:50:06 AM PDT 24 2450212971 ps
T7 /workspace/coverage/default/7.sysrst_ctrl_stress_all.1147973452 Jul 02 07:50:20 AM PDT 24 Jul 02 07:51:02 AM PDT 24 18126859647 ps
T15 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3916062383 Jul 02 07:51:33 AM PDT 24 Jul 02 07:51:43 AM PDT 24 2044705923 ps
T16 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3050441297 Jul 02 07:50:35 AM PDT 24 Jul 02 07:51:42 AM PDT 24 99538590483 ps
T8 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4060933595 Jul 02 07:51:34 AM PDT 24 Jul 02 07:56:20 AM PDT 24 113829720683 ps
T9 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2767798235 Jul 02 07:51:51 AM PDT 24 Jul 02 07:52:03 AM PDT 24 3041057704 ps
T49 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.549611583 Jul 02 07:50:59 AM PDT 24 Jul 02 07:51:05 AM PDT 24 3289719306 ps
T24 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.644256551 Jul 02 07:50:46 AM PDT 24 Jul 02 07:50:58 AM PDT 24 3801605524 ps
T25 /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3720554734 Jul 02 07:51:33 AM PDT 24 Jul 02 07:51:40 AM PDT 24 3166538241 ps
T22 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1228554042 Jul 02 07:51:49 AM PDT 24 Jul 02 07:51:57 AM PDT 24 2520465534 ps
T23 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.4124927705 Jul 02 07:50:41 AM PDT 24 Jul 02 07:50:46 AM PDT 24 2528804503 ps
T93 /workspace/coverage/default/19.sysrst_ctrl_smoke.2797249347 Jul 02 07:50:50 AM PDT 24 Jul 02 07:51:00 AM PDT 24 2109226276 ps
T64 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.33647427 Jul 02 07:51:16 AM PDT 24 Jul 02 07:51:24 AM PDT 24 2511166227 ps
T94 /workspace/coverage/default/42.sysrst_ctrl_smoke.4146611782 Jul 02 07:51:40 AM PDT 24 Jul 02 07:51:47 AM PDT 24 2116151837 ps
T27 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1542219493 Jul 02 07:51:49 AM PDT 24 Jul 02 07:51:59 AM PDT 24 2861227419 ps
T10 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1441904368 Jul 02 07:50:10 AM PDT 24 Jul 02 07:51:12 AM PDT 24 73565498117 ps
T11 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.755601013 Jul 02 07:50:53 AM PDT 24 Jul 02 07:51:05 AM PDT 24 3972612539 ps
T38 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3205581156 Jul 02 07:51:50 AM PDT 24 Jul 02 07:52:25 AM PDT 24 41151920084 ps
T12 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2277053134 Jul 02 07:51:08 AM PDT 24 Jul 02 07:51:19 AM PDT 24 3677170395 ps
T255 /workspace/coverage/default/38.sysrst_ctrl_alert_test.60411683 Jul 02 07:51:29 AM PDT 24 Jul 02 07:51:32 AM PDT 24 2074467736 ps
T65 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3625182519 Jul 02 07:50:23 AM PDT 24 Jul 02 07:50:32 AM PDT 24 2513562770 ps
T66 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.566983425 Jul 02 07:51:12 AM PDT 24 Jul 02 07:51:16 AM PDT 24 2577904968 ps
T34 /workspace/coverage/default/17.sysrst_ctrl_stress_all.3694544058 Jul 02 07:50:46 AM PDT 24 Jul 02 07:51:16 AM PDT 24 10354734465 ps
T256 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2456623354 Jul 02 07:49:49 AM PDT 24 Jul 02 07:50:52 AM PDT 24 22028643123 ps
T52 /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1105626113 Jul 02 07:51:35 AM PDT 24 Jul 02 07:51:44 AM PDT 24 3209509567 ps
T17 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2553882721 Jul 02 07:50:40 AM PDT 24 Jul 02 07:50:44 AM PDT 24 6787663955 ps
T53 /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.148075963 Jul 02 07:50:18 AM PDT 24 Jul 02 07:50:21 AM PDT 24 2910967874 ps
T39 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3655277463 Jul 02 07:49:48 AM PDT 24 Jul 02 07:50:00 AM PDT 24 2319004900 ps
T28 /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2772830318 Jul 02 07:52:01 AM PDT 24 Jul 02 07:52:17 AM PDT 24 61417122579 ps
T129 /workspace/coverage/default/28.sysrst_ctrl_alert_test.947035127 Jul 02 07:51:17 AM PDT 24 Jul 02 07:51:22 AM PDT 24 2123305345 ps
T130 /workspace/coverage/default/23.sysrst_ctrl_alert_test.2306885422 Jul 02 07:50:54 AM PDT 24 Jul 02 07:51:01 AM PDT 24 2029701814 ps
T40 /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.36889612 Jul 02 07:50:43 AM PDT 24 Jul 02 07:50:57 AM PDT 24 3537840557 ps
T286 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1409442874 Jul 02 07:50:57 AM PDT 24 Jul 02 07:51:08 AM PDT 24 2046364188 ps
T67 /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.261920191 Jul 02 07:50:32 AM PDT 24 Jul 02 07:50:40 AM PDT 24 2513574222 ps
T68 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3109026771 Jul 02 07:50:29 AM PDT 24 Jul 02 07:50:38 AM PDT 24 2513584516 ps
T287 /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1043894062 Jul 02 07:51:06 AM PDT 24 Jul 02 07:51:19 AM PDT 24 3739048441 ps
T30 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.848920190 Jul 02 07:51:06 AM PDT 24 Jul 02 07:55:03 AM PDT 24 96788638467 ps
T41 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2201092220 Jul 02 07:50:47 AM PDT 24 Jul 02 07:51:24 AM PDT 24 24088429853 ps
T42 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3018420730 Jul 02 07:51:58 AM PDT 24 Jul 02 07:53:29 AM PDT 24 35245698676 ps
T29 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1083653214 Jul 02 07:51:44 AM PDT 24 Jul 02 07:56:35 AM PDT 24 115695321730 ps
T69 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1987393550 Jul 02 07:51:27 AM PDT 24 Jul 02 07:51:30 AM PDT 24 2646768873 ps
T322 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.2270297586 Jul 02 07:50:57 AM PDT 24 Jul 02 07:51:09 AM PDT 24 2256954036 ps
T300 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1116464085 Jul 02 07:49:59 AM PDT 24 Jul 02 07:51:01 AM PDT 24 22014959911 ps
T43 /workspace/coverage/default/6.sysrst_ctrl_stress_all.1392921449 Jul 02 07:50:21 AM PDT 24 Jul 02 07:50:50 AM PDT 24 9981893504 ps
T70 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1281030920 Jul 02 07:50:51 AM PDT 24 Jul 02 07:50:58 AM PDT 24 2535696223 ps
T313 /workspace/coverage/default/12.sysrst_ctrl_alert_test.1399534083 Jul 02 07:50:39 AM PDT 24 Jul 02 07:50:44 AM PDT 24 2019988538 ps
T51 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.121080288 Jul 02 07:51:33 AM PDT 24 Jul 02 07:53:37 AM PDT 24 87898296603 ps
T398 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3269896291 Jul 02 07:50:46 AM PDT 24 Jul 02 07:50:53 AM PDT 24 2531632394 ps
T60 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3461520883 Jul 02 07:51:53 AM PDT 24 Jul 02 07:52:05 AM PDT 24 2470545224 ps
T21 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1019997973 Jul 02 07:51:22 AM PDT 24 Jul 02 07:52:36 AM PDT 24 1201425484373 ps
T44 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2561225453 Jul 02 07:51:57 AM PDT 24 Jul 02 07:52:02 AM PDT 24 3330997664 ps
T182 /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1578362382 Jul 02 07:51:20 AM PDT 24 Jul 02 07:51:26 AM PDT 24 3636065569 ps
T183 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1767685284 Jul 02 07:51:49 AM PDT 24 Jul 02 07:57:50 AM PDT 24 548535889857 ps
T45 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2666655697 Jul 02 07:51:08 AM PDT 24 Jul 02 07:51:12 AM PDT 24 3680140994 ps
T184 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.307024885 Jul 02 07:51:04 AM PDT 24 Jul 02 07:51:12 AM PDT 24 2065246948 ps
T185 /workspace/coverage/default/40.sysrst_ctrl_smoke.1739275082 Jul 02 07:51:30 AM PDT 24 Jul 02 07:51:36 AM PDT 24 2120931383 ps
T61 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.758271543 Jul 02 07:50:27 AM PDT 24 Jul 02 07:50:30 AM PDT 24 2549540273 ps
T76 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3080622006 Jul 02 07:50:44 AM PDT 24 Jul 02 07:51:10 AM PDT 24 89291648930 ps
T186 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2132183702 Jul 02 07:50:56 AM PDT 24 Jul 02 07:51:09 AM PDT 24 2510530485 ps
T62 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3708111265 Jul 02 07:51:26 AM PDT 24 Jul 02 07:51:34 AM PDT 24 2460134662 ps
T280 /workspace/coverage/default/3.sysrst_ctrl_smoke.1252904566 Jul 02 07:50:06 AM PDT 24 Jul 02 07:50:15 AM PDT 24 2114940563 ps
T281 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.616511308 Jul 02 07:50:52 AM PDT 24 Jul 02 07:51:02 AM PDT 24 2096217251 ps
T282 /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.1880085251 Jul 02 07:51:24 AM PDT 24 Jul 02 07:51:27 AM PDT 24 2066922592 ps
T46 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.277339160 Jul 02 07:50:43 AM PDT 24 Jul 02 07:50:50 AM PDT 24 3497856248 ps
T283 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2478260605 Jul 02 07:50:51 AM PDT 24 Jul 02 07:50:59 AM PDT 24 4238229275 ps
T284 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1407899349 Jul 02 07:51:28 AM PDT 24 Jul 02 07:51:36 AM PDT 24 2511131467 ps
T285 /workspace/coverage/default/21.sysrst_ctrl_smoke.3406779216 Jul 02 07:50:47 AM PDT 24 Jul 02 07:50:53 AM PDT 24 2133620516 ps
T399 /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.916881043 Jul 02 07:50:05 AM PDT 24 Jul 02 07:50:09 AM PDT 24 2095618757 ps
T400 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1376607266 Jul 02 07:50:06 AM PDT 24 Jul 02 07:50:17 AM PDT 24 3085078004 ps
T54 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2020885669 Jul 02 07:51:00 AM PDT 24 Jul 02 07:51:16 AM PDT 24 14164389269 ps
T32 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1696698165 Jul 02 07:50:44 AM PDT 24 Jul 02 07:52:05 AM PDT 24 121695234663 ps
T150 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3282634224 Jul 02 07:51:50 AM PDT 24 Jul 02 07:51:57 AM PDT 24 2140668131 ps
T33 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3479234944 Jul 02 07:51:22 AM PDT 24 Jul 02 07:51:31 AM PDT 24 3750459636 ps
T91 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.40096440 Jul 02 07:50:16 AM PDT 24 Jul 02 07:52:33 AM PDT 24 51524408953 ps
T47 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.681687168 Jul 02 07:50:59 AM PDT 24 Jul 02 07:51:06 AM PDT 24 3313312743 ps
T151 /workspace/coverage/default/46.sysrst_ctrl_smoke.3664103212 Jul 02 07:51:36 AM PDT 24 Jul 02 07:51:41 AM PDT 24 2174965566 ps
T48 /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2791987797 Jul 02 07:50:45 AM PDT 24 Jul 02 07:50:55 AM PDT 24 3842523628 ps
T35 /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1203779451 Jul 02 07:51:55 AM PDT 24 Jul 02 07:52:06 AM PDT 24 2714624284 ps
T95 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1765026418 Jul 02 07:51:51 AM PDT 24 Jul 02 07:53:41 AM PDT 24 42667901429 ps
T236 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3178283320 Jul 02 07:50:18 AM PDT 24 Jul 02 07:50:21 AM PDT 24 2741261106 ps
T127 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.2092263784 Jul 02 07:51:12 AM PDT 24 Jul 02 07:51:34 AM PDT 24 86438099185 ps
T237 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2790921464 Jul 02 07:51:30 AM PDT 24 Jul 02 07:51:35 AM PDT 24 2523695288 ps
T238 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.279444767 Jul 02 07:50:05 AM PDT 24 Jul 02 07:50:24 AM PDT 24 22073078600 ps
T55 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2138443673 Jul 02 07:50:18 AM PDT 24 Jul 02 07:50:58 AM PDT 24 69069638650 ps
T56 /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3859273858 Jul 02 07:51:34 AM PDT 24 Jul 02 07:52:13 AM PDT 24 713930951025 ps
T239 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3856749171 Jul 02 07:51:20 AM PDT 24 Jul 02 07:51:30 AM PDT 24 2512512393 ps
T57 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.4209922283 Jul 02 07:50:37 AM PDT 24 Jul 02 07:50:43 AM PDT 24 10977108529 ps
T82 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2319623087 Jul 02 07:51:50 AM PDT 24 Jul 02 07:54:21 AM PDT 24 60212836569 ps
T187 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2581792985 Jul 02 07:50:42 AM PDT 24 Jul 02 07:50:50 AM PDT 24 2784293305 ps
T401 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2646145607 Jul 02 07:51:46 AM PDT 24 Jul 02 07:51:50 AM PDT 24 3194048286 ps
T402 /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.2962374836 Jul 02 07:49:46 AM PDT 24 Jul 02 07:50:01 AM PDT 24 2209232496 ps
T403 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.56725139 Jul 02 07:51:41 AM PDT 24 Jul 02 07:51:46 AM PDT 24 2241214326 ps
T63 /workspace/coverage/default/34.sysrst_ctrl_stress_all.2574914114 Jul 02 07:51:27 AM PDT 24 Jul 02 07:51:49 AM PDT 24 7063448051 ps
T404 /workspace/coverage/default/23.sysrst_ctrl_smoke.1191824411 Jul 02 07:50:57 AM PDT 24 Jul 02 07:51:08 AM PDT 24 2110240758 ps
T128 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2288658210 Jul 02 07:51:47 AM PDT 24 Jul 02 07:53:18 AM PDT 24 69814435986 ps
T36 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3759391279 Jul 02 07:51:46 AM PDT 24 Jul 02 07:51:52 AM PDT 24 4331903136 ps
T92 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3330193614 Jul 02 07:51:35 AM PDT 24 Jul 02 08:15:19 AM PDT 24 520528633196 ps
T405 /workspace/coverage/default/33.sysrst_ctrl_smoke.2382183867 Jul 02 07:51:11 AM PDT 24 Jul 02 07:51:16 AM PDT 24 2118275637 ps
T37 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1402498325 Jul 02 07:50:42 AM PDT 24 Jul 02 07:52:58 AM PDT 24 49839394430 ps
T58 /workspace/coverage/default/39.sysrst_ctrl_stress_all.925173282 Jul 02 07:51:28 AM PDT 24 Jul 02 07:56:00 AM PDT 24 857816611416 ps
T406 /workspace/coverage/default/48.sysrst_ctrl_alert_test.3424420095 Jul 02 07:51:51 AM PDT 24 Jul 02 07:51:59 AM PDT 24 2019263918 ps
T83 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.280446617 Jul 02 07:51:51 AM PDT 24 Jul 02 07:53:10 AM PDT 24 30131063528 ps
T407 /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.650359900 Jul 02 07:51:27 AM PDT 24 Jul 02 07:51:30 AM PDT 24 2549995301 ps
T321 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1023903881 Jul 02 07:51:31 AM PDT 24 Jul 02 07:51:37 AM PDT 24 2538736432 ps
T408 /workspace/coverage/default/36.sysrst_ctrl_alert_test.1546809619 Jul 02 07:51:39 AM PDT 24 Jul 02 07:51:44 AM PDT 24 2089937786 ps
T59 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4144771070 Jul 02 07:50:10 AM PDT 24 Jul 02 07:50:14 AM PDT 24 2622019627 ps
T409 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.746413620 Jul 02 07:50:25 AM PDT 24 Jul 02 07:50:31 AM PDT 24 2616493455 ps
T410 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3345509841 Jul 02 07:51:49 AM PDT 24 Jul 02 07:51:56 AM PDT 24 2520959763 ps
T319 /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.3872945733 Jul 02 07:50:45 AM PDT 24 Jul 02 07:50:56 AM PDT 24 2484540630 ps
T71 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.4281140297 Jul 02 07:51:16 AM PDT 24 Jul 02 07:53:38 AM PDT 24 55083883115 ps
T110 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1531710210 Jul 02 07:51:50 AM PDT 24 Jul 02 07:52:55 AM PDT 24 106740679936 ps
T111 /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2916400613 Jul 02 07:51:35 AM PDT 24 Jul 02 07:51:42 AM PDT 24 4227068442 ps
T112 /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3291437391 Jul 02 07:50:59 AM PDT 24 Jul 02 07:51:12 AM PDT 24 2610189389 ps
T113 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2555172691 Jul 02 07:52:00 AM PDT 24 Jul 02 07:54:57 AM PDT 24 66872803342 ps
T114 /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2083965941 Jul 02 07:50:23 AM PDT 24 Jul 02 07:50:33 AM PDT 24 2456236000 ps
T96 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.492380999 Jul 02 07:51:30 AM PDT 24 Jul 02 07:52:12 AM PDT 24 29343612123 ps
T115 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2678805551 Jul 02 07:51:05 AM PDT 24 Jul 02 07:52:23 AM PDT 24 186559744743 ps
T116 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.1401410979 Jul 02 07:51:32 AM PDT 24 Jul 02 07:51:41 AM PDT 24 2023889349 ps
T117 /workspace/coverage/default/0.sysrst_ctrl_smoke.2688464106 Jul 02 07:49:53 AM PDT 24 Jul 02 07:50:04 AM PDT 24 2126416687 ps
T411 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1041062220 Jul 02 07:50:12 AM PDT 24 Jul 02 07:50:21 AM PDT 24 2609055726 ps
T412 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2654070300 Jul 02 07:51:09 AM PDT 24 Jul 02 07:51:18 AM PDT 24 2512399864 ps
T188 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2905022173 Jul 02 07:51:35 AM PDT 24 Jul 02 07:51:49 AM PDT 24 3164987310 ps
T31 /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2471382189 Jul 02 07:51:48 AM PDT 24 Jul 02 07:53:48 AM PDT 24 83540832939 ps
T196 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.2154135933 Jul 02 07:51:33 AM PDT 24 Jul 02 07:51:38 AM PDT 24 3460289112 ps
T77 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.509017726 Jul 02 07:51:16 AM PDT 24 Jul 02 07:53:14 AM PDT 24 85488215323 ps
T272 /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2909048118 Jul 02 07:51:55 AM PDT 24 Jul 02 07:54:54 AM PDT 24 70623965805 ps
T273 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.506767767 Jul 02 07:51:00 AM PDT 24 Jul 02 07:51:11 AM PDT 24 4175591598 ps
T274 /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4145034052 Jul 02 07:50:19 AM PDT 24 Jul 02 07:50:22 AM PDT 24 3340916924 ps
T275 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2752414436 Jul 02 07:49:46 AM PDT 24 Jul 02 07:49:59 AM PDT 24 2182877104 ps
T97 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.475251179 Jul 02 07:50:09 AM PDT 24 Jul 02 07:50:20 AM PDT 24 47410670151 ps
T118 /workspace/coverage/default/15.sysrst_ctrl_smoke.3290540521 Jul 02 07:50:43 AM PDT 24 Jul 02 07:50:52 AM PDT 24 2111439511 ps
T119 /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1481973404 Jul 02 07:51:40 AM PDT 24 Jul 02 07:51:51 AM PDT 24 2466548352 ps
T120 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3587962472 Jul 02 07:51:48 AM PDT 24 Jul 02 07:51:59 AM PDT 24 2613771745 ps
T121 /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.406674544 Jul 02 07:50:24 AM PDT 24 Jul 02 07:50:28 AM PDT 24 2636826897 ps
T122 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1845593409 Jul 02 07:50:49 AM PDT 24 Jul 02 07:50:55 AM PDT 24 2220146654 ps
T123 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.706674848 Jul 02 07:51:35 AM PDT 24 Jul 02 07:51:43 AM PDT 24 2076663489 ps
T124 /workspace/coverage/default/27.sysrst_ctrl_stress_all.1221706025 Jul 02 07:51:17 AM PDT 24 Jul 02 07:51:46 AM PDT 24 921246108566 ps
T125 /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.2685743684 Jul 02 07:51:24 AM PDT 24 Jul 02 07:51:34 AM PDT 24 2484091099 ps
T126 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3638617383 Jul 02 07:50:40 AM PDT 24 Jul 02 07:50:44 AM PDT 24 2658189196 ps
T317 /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1464441845 Jul 02 07:52:02 AM PDT 24 Jul 02 07:52:06 AM PDT 24 3037071115 ps
T288 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1369313966 Jul 02 07:52:01 AM PDT 24 Jul 02 07:54:08 AM PDT 24 47569300154 ps
T359 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2734816290 Jul 02 07:51:51 AM PDT 24 Jul 02 07:57:08 AM PDT 24 183758662122 ps
T268 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.163059385 Jul 02 07:51:51 AM PDT 24 Jul 02 07:52:18 AM PDT 24 31377496604 ps
T360 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2499799349 Jul 02 07:51:40 AM PDT 24 Jul 02 07:53:16 AM PDT 24 76123281302 ps
T269 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3655304910 Jul 02 07:50:14 AM PDT 24 Jul 02 07:53:22 AM PDT 24 71355585492 ps
T316 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1752205683 Jul 02 07:51:00 AM PDT 24 Jul 02 07:52:18 AM PDT 24 27369025988 ps
T80 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.787596266 Jul 02 07:50:17 AM PDT 24 Jul 02 07:53:00 AM PDT 24 193507507905 ps
T210 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.415804459 Jul 02 07:49:51 AM PDT 24 Jul 02 07:53:07 AM PDT 24 178069157873 ps
T245 /workspace/coverage/default/16.sysrst_ctrl_alert_test.1278598397 Jul 02 07:50:42 AM PDT 24 Jul 02 07:50:51 AM PDT 24 2009768842 ps
T246 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.2886813159 Jul 02 07:49:56 AM PDT 24 Jul 02 07:50:07 AM PDT 24 2535259214 ps
T247 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2479405647 Jul 02 07:51:50 AM PDT 24 Jul 02 07:52:12 AM PDT 24 25857326398 ps
T248 /workspace/coverage/default/44.sysrst_ctrl_stress_all.2198528203 Jul 02 07:51:48 AM PDT 24 Jul 02 08:02:28 AM PDT 24 242810074890 ps
T249 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.836671324 Jul 02 07:51:48 AM PDT 24 Jul 02 07:54:00 AM PDT 24 54673843716 ps
T250 /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1558234020 Jul 02 07:50:59 AM PDT 24 Jul 02 07:51:11 AM PDT 24 2512647334 ps
T251 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3312839629 Jul 02 07:51:41 AM PDT 24 Jul 02 07:51:51 AM PDT 24 2612997135 ps
T98 /workspace/coverage/default/40.sysrst_ctrl_stress_all.3940323729 Jul 02 07:51:36 AM PDT 24 Jul 02 07:56:58 AM PDT 24 523343840260 ps
T292 /workspace/coverage/default/9.sysrst_ctrl_stress_all.886144170 Jul 02 07:50:28 AM PDT 24 Jul 02 07:50:40 AM PDT 24 14316806490 ps
T72 /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2472603893 Jul 02 07:49:47 AM PDT 24 Jul 02 07:50:07 AM PDT 24 35899341579 ps
T293 /workspace/coverage/default/37.sysrst_ctrl_alert_test.3761889106 Jul 02 07:51:35 AM PDT 24 Jul 02 07:51:41 AM PDT 24 2063000083 ps
T294 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1933808691 Jul 02 07:50:24 AM PDT 24 Jul 02 07:50:27 AM PDT 24 3350934951 ps
T295 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3858566521 Jul 02 07:50:02 AM PDT 24 Jul 02 07:50:11 AM PDT 24 3238582347 ps
T99 /workspace/coverage/default/43.sysrst_ctrl_stress_all.3350516556 Jul 02 07:51:43 AM PDT 24 Jul 02 07:59:22 AM PDT 24 171777394158 ps
T296 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2701433623 Jul 02 07:51:16 AM PDT 24 Jul 02 07:51:27 AM PDT 24 2608983139 ps
T266 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1847814478 Jul 02 07:50:47 AM PDT 24 Jul 02 07:51:07 AM PDT 24 25604533493 ps
T297 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.250169132 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:29 AM PDT 24 3515835956 ps
T361 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3673298034 Jul 02 07:51:02 AM PDT 24 Jul 02 07:52:40 AM PDT 24 145814015555 ps
T366 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1483176937 Jul 02 07:50:01 AM PDT 24 Jul 02 07:51:31 AM PDT 24 148087787582 ps
T413 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.933275619 Jul 02 07:50:52 AM PDT 24 Jul 02 07:50:59 AM PDT 24 2620997290 ps
T414 /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2059608611 Jul 02 07:51:57 AM PDT 24 Jul 02 07:52:04 AM PDT 24 2516998522 ps
T357 /workspace/coverage/default/17.sysrst_ctrl_combo_detect.893059267 Jul 02 07:50:42 AM PDT 24 Jul 02 07:52:08 AM PDT 24 112251269292 ps
T415 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2588599602 Jul 02 07:51:49 AM PDT 24 Jul 02 07:51:55 AM PDT 24 2132486140 ps
T416 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2477050821 Jul 02 07:51:32 AM PDT 24 Jul 02 07:51:38 AM PDT 24 3544830135 ps
T417 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2830409618 Jul 02 07:50:56 AM PDT 24 Jul 02 07:51:04 AM PDT 24 4145438248 ps
T418 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1739621301 Jul 02 07:50:53 AM PDT 24 Jul 02 07:51:07 AM PDT 24 3610422066 ps
T73 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1064291811 Jul 02 07:50:23 AM PDT 24 Jul 02 07:50:27 AM PDT 24 8694837821 ps
T379 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3525250949 Jul 02 07:50:44 AM PDT 24 Jul 02 07:56:16 AM PDT 24 128480738165 ps
T419 /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1653431228 Jul 02 07:51:39 AM PDT 24 Jul 02 07:51:44 AM PDT 24 2088299300 ps
T74 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3350615128 Jul 02 07:50:27 AM PDT 24 Jul 02 07:51:35 AM PDT 24 29052692338 ps
T136 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3373438643 Jul 02 07:50:47 AM PDT 24 Jul 02 07:52:30 AM PDT 24 159946539276 ps
T137 /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2745314602 Jul 02 07:51:50 AM PDT 24 Jul 02 07:51:56 AM PDT 24 2082204381 ps
T138 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3406419273 Jul 02 07:49:54 AM PDT 24 Jul 02 07:50:07 AM PDT 24 2276718126 ps
T139 /workspace/coverage/default/41.sysrst_ctrl_smoke.1606886012 Jul 02 07:51:28 AM PDT 24 Jul 02 07:51:32 AM PDT 24 2137259369 ps
T140 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2994897804 Jul 02 07:52:01 AM PDT 24 Jul 02 07:52:42 AM PDT 24 82687099537 ps
T141 /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1767871101 Jul 02 07:50:43 AM PDT 24 Jul 02 07:50:49 AM PDT 24 2620829209 ps
T142 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2778196954 Jul 02 07:51:10 AM PDT 24 Jul 02 07:52:00 AM PDT 24 208525783900 ps
T143 /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1557194883 Jul 02 07:50:13 AM PDT 24 Jul 02 07:52:26 AM PDT 24 103792211288 ps
T144 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.604120308 Jul 02 07:50:04 AM PDT 24 Jul 02 07:50:11 AM PDT 24 2456887812 ps
T75 /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1503045738 Jul 02 07:51:52 AM PDT 24 Jul 02 07:51:59 AM PDT 24 4614538222 ps
T365 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1578219083 Jul 02 07:52:06 AM PDT 24 Jul 02 07:52:41 AM PDT 24 89529276232 ps
T420 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1866643804 Jul 02 07:49:54 AM PDT 24 Jul 02 07:50:07 AM PDT 24 2466454225 ps
T267 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2253178689 Jul 02 07:52:10 AM PDT 24 Jul 02 07:53:12 AM PDT 24 23081012932 ps
T421 /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1339989978 Jul 02 07:50:19 AM PDT 24 Jul 02 07:51:12 AM PDT 24 87030573856 ps
T87 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.554893899 Jul 02 07:51:28 AM PDT 24 Jul 02 07:51:33 AM PDT 24 3001526955 ps
T131 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2699930701 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:27 AM PDT 24 6506826431 ps
T211 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2300582509 Jul 02 07:51:54 AM PDT 24 Jul 02 07:52:28 AM PDT 24 71054805110 ps
T212 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1022415879 Jul 02 07:52:04 AM PDT 24 Jul 02 07:54:58 AM PDT 24 144179584057 ps
T213 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3744405380 Jul 02 07:50:40 AM PDT 24 Jul 02 07:51:11 AM PDT 24 44897994055 ps
T214 /workspace/coverage/default/35.sysrst_ctrl_alert_test.663843110 Jul 02 07:51:28 AM PDT 24 Jul 02 07:51:30 AM PDT 24 2036227846 ps
T215 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.311947724 Jul 02 07:51:08 AM PDT 24 Jul 02 07:51:57 AM PDT 24 35335857348 ps
T216 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4190377414 Jul 02 07:51:35 AM PDT 24 Jul 02 07:52:52 AM PDT 24 28559629013 ps
T217 /workspace/coverage/default/26.sysrst_ctrl_stress_all.1968815384 Jul 02 07:51:03 AM PDT 24 Jul 02 07:51:26 AM PDT 24 98301751290 ps
T218 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.588344008 Jul 02 07:51:16 AM PDT 24 Jul 02 07:51:22 AM PDT 24 3064083818 ps
T422 /workspace/coverage/default/44.sysrst_ctrl_alert_test.1988442772 Jul 02 07:51:48 AM PDT 24 Jul 02 07:51:56 AM PDT 24 2012836062 ps
T423 /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3387050335 Jul 02 07:51:15 AM PDT 24 Jul 02 07:51:20 AM PDT 24 3403885822 ps
T424 /workspace/coverage/default/49.sysrst_ctrl_stress_all.784927972 Jul 02 07:51:51 AM PDT 24 Jul 02 07:51:59 AM PDT 24 9552209904 ps
T425 /workspace/coverage/default/49.sysrst_ctrl_smoke.1942711231 Jul 02 07:51:58 AM PDT 24 Jul 02 07:52:03 AM PDT 24 2129718465 ps
T426 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.1012863080 Jul 02 07:51:31 AM PDT 24 Jul 02 07:51:36 AM PDT 24 2469638184 ps
T320 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1306851216 Jul 02 07:50:34 AM PDT 24 Jul 02 07:50:38 AM PDT 24 2487293762 ps
T427 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.539497257 Jul 02 07:51:32 AM PDT 24 Jul 02 07:51:37 AM PDT 24 2235849630 ps
T393 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1905086103 Jul 02 07:51:51 AM PDT 24 Jul 02 07:53:12 AM PDT 24 112477022858 ps
T428 /workspace/coverage/default/11.sysrst_ctrl_stress_all.2383257483 Jul 02 07:50:33 AM PDT 24 Jul 02 07:50:53 AM PDT 24 7688644801 ps
T429 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3627262785 Jul 02 07:50:56 AM PDT 24 Jul 02 07:51:08 AM PDT 24 2612196818 ps
T100 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3153380481 Jul 02 07:51:17 AM PDT 24 Jul 02 07:52:21 AM PDT 24 22332681610 ps
T430 /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3529787244 Jul 02 07:51:04 AM PDT 24 Jul 02 07:51:11 AM PDT 24 2615792135 ps
T358 /workspace/coverage/default/33.sysrst_ctrl_combo_detect.2610360387 Jul 02 07:51:28 AM PDT 24 Jul 02 07:51:59 AM PDT 24 113442909367 ps
T254 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3357758187 Jul 02 07:50:25 AM PDT 24 Jul 02 07:50:31 AM PDT 24 2690184372 ps
T431 /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1883364598 Jul 02 07:50:40 AM PDT 24 Jul 02 07:50:49 AM PDT 24 2467118607 ps
T432 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3268225801 Jul 02 07:51:35 AM PDT 24 Jul 02 07:51:51 AM PDT 24 4345702759 ps
T433 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3756969543 Jul 02 07:49:51 AM PDT 24 Jul 02 07:50:08 AM PDT 24 2469630460 ps
T78 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3444601827 Jul 02 07:49:55 AM PDT 24 Jul 02 07:51:29 AM PDT 24 33383948059 ps
T434 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.575098861 Jul 02 07:50:50 AM PDT 24 Jul 02 07:51:58 AM PDT 24 24582007978 ps
T435 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3112069664 Jul 02 07:51:44 AM PDT 24 Jul 02 07:51:50 AM PDT 24 3348042134 ps
T436 /workspace/coverage/default/48.sysrst_ctrl_smoke.2981783825 Jul 02 07:51:50 AM PDT 24 Jul 02 07:52:00 AM PDT 24 2109303547 ps
T367 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2732545924 Jul 02 07:50:53 AM PDT 24 Jul 02 07:52:17 AM PDT 24 64430576501 ps
T163 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3112029537 Jul 02 07:50:32 AM PDT 24 Jul 02 07:51:17 AM PDT 24 39056709424 ps
T169 /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3017677836 Jul 02 07:51:04 AM PDT 24 Jul 02 07:51:10 AM PDT 24 2524145326 ps
T170 /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3192005407 Jul 02 07:50:50 AM PDT 24 Jul 02 07:50:59 AM PDT 24 2617655726 ps
T171 /workspace/coverage/default/31.sysrst_ctrl_alert_test.802348569 Jul 02 07:51:09 AM PDT 24 Jul 02 07:51:18 AM PDT 24 2014188883 ps
T172 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3128879864 Jul 02 07:51:29 AM PDT 24 Jul 02 07:51:34 AM PDT 24 2627478231 ps
T173 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3653147985 Jul 02 07:51:05 AM PDT 24 Jul 02 07:51:20 AM PDT 24 4287107981 ps
T174 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3259938452 Jul 02 07:51:42 AM PDT 24 Jul 02 07:52:27 AM PDT 24 69468520903 ps
T165 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.109742879 Jul 02 07:50:58 AM PDT 24 Jul 02 07:51:07 AM PDT 24 3386316426 ps
T175 /workspace/coverage/default/37.sysrst_ctrl_combo_detect.1666781771 Jul 02 07:51:23 AM PDT 24 Jul 02 07:51:51 AM PDT 24 77066250776 ps
T176 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1636516813 Jul 02 07:51:49 AM PDT 24 Jul 02 07:51:55 AM PDT 24 2492652538 ps
T101 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.3944267784 Jul 02 07:51:16 AM PDT 24 Jul 02 07:52:28 AM PDT 24 95807643478 ps
T437 /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2235650868 Jul 02 07:49:51 AM PDT 24 Jul 02 07:50:07 AM PDT 24 2625234785 ps
T289 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.1247648933 Jul 02 07:51:14 AM PDT 24 Jul 02 07:54:49 AM PDT 24 90074530723 ps
T438 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.392964020 Jul 02 07:51:33 AM PDT 24 Jul 02 07:51:41 AM PDT 24 2516428149 ps
T439 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1610244969 Jul 02 07:51:08 AM PDT 24 Jul 02 07:51:13 AM PDT 24 2253570963 ps
T440 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2444668131 Jul 02 07:51:28 AM PDT 24 Jul 02 07:51:34 AM PDT 24 2665728592 ps
T441 /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.991377361 Jul 02 07:51:05 AM PDT 24 Jul 02 07:51:10 AM PDT 24 2530139721 ps
T380 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1684569704 Jul 02 07:51:48 AM PDT 24 Jul 02 07:52:23 AM PDT 24 47416281513 ps
T442 /workspace/coverage/default/20.sysrst_ctrl_smoke.3010811410 Jul 02 07:50:56 AM PDT 24 Jul 02 07:51:03 AM PDT 24 2129261138 ps
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