Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.80	87.80	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	87.80	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.80	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	10	52	83.87

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	9	22	70.97	100	1	1	0
cross_key_combinations_combo_detection_sel	31	1	30	96.77	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1983

1

T16

22

T8

17

T10

14

auto[1]

585

1

T2

27

T16

2

T8

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1872

1

T2

27

T16

20

T8

19

auto[1]

696

1

T16

4

T8

1

T28

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2020

1

T2

13

T16

24

T8

20

auto[1]

548

1

T2

14

T10

2

T28

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1943

1

T2

27

T16

24

T8

18

auto[1]

625

1

T8

2

T29

4

T51

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2328

1

T2

27

T16

20

T8

20

auto[1]

240

1

T16

4

T10

2

T28

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T2

27

T16

24

T8

18

auto[1]

166

1

T8

2

T28

1

T30

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2376

1

T2

27

T16

24

T8

18

auto[1]

192

1

T8

2

T10

2

T51

8

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2418

1

T2

27

T16

22

T8

16

auto[1]

150

1

T16

2

T8

4

T10

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2342

1

T2

27

T16

24

T8

17

auto[1]

226

1

T8

3

T28

2

T30

9

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2013

1

T2

21

T16

24

T8

20

auto[1]

555

1

T2

6

T10

4

T28

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	9	22	70.97	9
Automatically Generated Cross Bins	31	9	22	70.97	9
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	924	1			T2	19		T76	8		T32	16
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	98	1			T16	4		T10	2		T30	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	75	1			T28	2		T113	2		T115	9
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	32	1			T30	4		T110	2		T369	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	49	1			T16	2		T8	3		T28	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	14	1			T370	2		T371	12		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	28	1			T8	1		T30	2		T369	20
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	7	1			T272	1		T212	4		T372	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	52	1			T82	3		T110	6		T113	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	31	1			T359	5		T140	8		T369	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	23	1			T128	3		T212	12		T332	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T51	3		T110	2		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	13	1			T10	2		T115	4		T373	6
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T359	5		T374	1		T371	2
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T375	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	54	1			T29	4		T272	1		T288	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	26	1			T28	1		T30	3		T82	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	1	1			T370	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T91	2		T376	4		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	8	1			T377	2		T378	6		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	33	1			T51	5		T110	5		T211	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T8	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	1	30	96.77	1
Automatically Generated Cross Bins	31	1	30	96.77	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Uncovered bins

cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

123

1

T2

13

T16

2

T8

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

142

1

T28

1

T110

5

T359

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

50

1

T10

2

T32

7

T98

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

93

1

T8

2

T110

2

T113

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

51

1

T379

4

T136

5

T143

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T29

4

T51

5

T77

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T76

2

T272

1

T269

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

103

1

T30

6

T32

6

T82

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

69

1

T28

2

T98

8

T366

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T10

2

T30

3

T82

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T2

6

T360

1

T380

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55

1

T76

6

T91

2

T31

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T288

2

T269

3

T98

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T213

2

T358

3

T174

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T357

4

T217

1

T278

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

150

1

T16

4

T8

1

T30

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

48

1

T30

2

T248

4

T361

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T29

6

T113

2

T97

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T127

3

T82

3

T115

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

111

1

T51

3

T55

1

T128

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T32

2

T97

2

T248

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T55

1

T128

3

T360

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T127

1

T97

1

T217

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T29

4

T212

4

T381

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T32

1

T127

1

T115

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T28

1

T128

3

T83

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T269

2

T98

1

T217

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27

1

T127

1

T77

4

T248

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T379

2

T142

1

T155

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T99

2

T379

2

T136

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded