Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T22

11

T23

12

T64

6

auto[1]

1081

1

T22

9

T23

8

T64

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T22

4

T23

4

T64

4

from_0to1

532

1

T22

4

T23

4

T64

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T22

16

T23

11

T64

11

auto[1]

1129

1

T22

4

T23

9

T64

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103

1

T22

8

T23

12

T64

13

auto[1]

1157

1

T22

12

T23

8

T64

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T22

1

T23

2

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T22

1

T70

1

T186

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T22

1

T65

1

T66

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T23

1

T65

1

T66

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T23

1

T64

1

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T22

1

T23

1

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T23

1

T65

2

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T22

1

T70

1

T398

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T64

3

T70

1

T186

2

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T22

1

T64

1

T68

2

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T65

2

T67

1

T70

2

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T23

1

T66

2

T398

3

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T22

2

T23

1

T64

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T64

1

T65

1

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T66

1

T67

1

T398

3

auto[1]

from_0to1

auto[1]

auto[1]

83

1

T64

1

T66

2

T70

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T22

5

T23

10

T64

9

auto[1]

1160

1

T22

15

T23

10

T64

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T22

6

T23

5

T64

5

from_0to1

546

1

T22

5

T23

4

T64

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T22

11

T23

11

T64

14

auto[1]

1114

1

T22

9

T23

9

T64

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T22

14

T23

9

T64

13

auto[1]

1117

1

T22

6

T23

11

T64

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T22

1

T23

1

T64

2

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T23

2

T64

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T22

2

T65

1

T66

2

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T23

1

T64

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T64

1

T65

2

T21

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T23

1

T65

1

T66

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T66

1

T67

1

T70

2

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T64

1

T65

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T22

2

T64

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T22

1

T66

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T65

2

T66

1

T186

3

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T23

1

T67

1

T68

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T22

1

T23

1

T64

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T22

1

T64

1

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T22

2

T23

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T22

1

T23

1

T64

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T22

10

T23

14

T64

9

auto[1]

1118

1

T22

10

T23

6

T64

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

554

1

T22

6

T23

5

T64

7

from_0to1

548

1

T22

6

T23

5

T64

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T22

14

T23

12

T64

8

auto[1]

1121

1

T22

6

T23

8

T64

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T22

5

T23

11

T64

13

auto[1]

1102

1

T22

15

T23

9

T64

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T23

1

T65

1

T66

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T22

3

T64

1

T66

1

auto[0]

from_1to0

auto[1]

auto[0]

90

1

T23

1

T66

1

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T23

2

T64

3

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T22

2

T23

1

T65

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T22

1

T66

1

T398

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T22

1

T23

1

T64

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T22

1

T64

1

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T64

2

T65

2

T66

1

auto[1]

from_1to0

auto[0]

auto[1]

80

1

T22

3

T65

1

T70

2

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T23

1

T64

1

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T66

1

T67

2

T68

2

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T23

1

T64

2

T65

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T23

1

T70

1

T186

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T22

1

T23

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T64

1

T66

1

T67

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T22

10

T23

7

T64

9

auto[1]

1121

1

T22

10

T23

13

T64

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

527

1

T22

4

T23

6

T64

3

from_0to1

532

1

T22

4

T23

5

T64

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T22

9

T23

9

T64

9

auto[1]

1129

1

T22

11

T23

11

T64

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T22

9

T23

10

T64

10

auto[1]

1127

1

T22

11

T23

10

T64

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T23

1

T68

2

T186

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T64

1

T65

1

T21

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T65

1

T66

1

T70

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T22

1

T64

1

T67

3

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T22

1

T23

1

T66

2

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T22

1

T67

1

T68

2

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T22

1

T23

1

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

85

1

T64

1

T65

1

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T22

1

T23

2

T66

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T65

2

T66

1

T398

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T68

2

T70

1

T398

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T22

2

T23

3

T64

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T21

1

T186

1

T284

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T22

1

T68

1

T398

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T23

2

T64

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

81

1

T23

1

T64

1

T65

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T22

11

T23

11

T64

8

auto[1]

1108

1

T22

9

T23

9

T64

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T22

7

T23

4

T64

6

from_0to1

533

1

T22

6

T23

5

T64

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T22

9

T23

12

T64

11

auto[1]

1139

1

T22

11

T23

8

T64

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T22

9

T23

8

T64

10

auto[1]

1108

1

T22

11

T23

12

T64

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T22

2

T23

1

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T22

2

T64

1

T65

2

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T22

1

T68

1

T186

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T22

1

T23

1

T64

2

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T22

1

T23

1

T64

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T22

1

T23

3

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T22

1

T65

3

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T65

2

T67

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T64

1

T67

2

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T65

1

T67

1

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T65

1

T66

1

T21

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T22

1

T23

2

T64

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T22

1

T64

1

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T22

1

T64

2

T66

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T23

1

T64

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T22

1

T64

2

T65

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T22

11

T23

9

T64

7

auto[1]

1129

1

T22

9

T23

11

T64

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

557

1

T22

3

T23

4

T64

5

from_0to1

554

1

T22

2

T23

4

T64

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T22

13

T23

10

T64

10

auto[1]

1144

1

T22

7

T23

10

T64

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1169

1

T22

10

T23

14

T64

9

auto[1]

1091

1

T22

10

T23

6

T64

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T66

1

T70

1

T237

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T67

1

T398

1

T21

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T22

1

T23

1

T65

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T23

1

T64

1

T65

2

auto[0]

from_0to1

auto[0]

auto[0]

83

1

T22

1

T23

2

T65

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T64

1

T66

1

T67

2

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T65

2

T67

1

T68

2

auto[0]

from_0to1

auto[1]

auto[1]

82

1

T64

2

T65

1

T66

3

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T22

1

T23

1

T64

2

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T67

1

T398

1

T284

1

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T23

1

T64

2

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

82

1

T22

1

T65

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T23

1

T65

1

T398

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T23

1

T64

2

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T22

1

T68

2

T398

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T398

1

T21

1

T186

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T22

12

T23

8

T64

8

auto[1]

1147

1

T22

8

T23

12

T64

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T22

4

T23

4

T64

4

from_0to1

560

1

T22

3

T23

3

T64

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T22

9

T23

11

T64

13

auto[1]

1131

1

T22

11

T23

9

T64

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T22

12

T23

8

T64

15

auto[1]

1189

1

T22

8

T23

12

T64

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T22

1

T23

1

T64

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T64

1

T398

2

T21

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T22

1

T64

1

T65

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T22

1

T23

2

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T64

1

T66

1

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T22

1

T67

1

T398

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T66

3

T68

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T22

1

T65

1

T186

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T23

1

T66

1

T21

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T66

1

T68

1

T70

2

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T64

1

T65

3

T398

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T22

1

T66

2

T67

3

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T22

1

T23

1

T64

1

auto[1]

from_0to1

auto[0]

auto[1]

80

1

T23

1

T64

2

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T23

1

T65

2

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T67

2

T70

1

T398

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T22

10

T23

10

T64

11

auto[1]

1121

1

T22

10

T23

10

T64

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

536

1

T22

4

T23

4

T64

5

from_0to1

536

1

T22

5

T23

5

T64

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1160

1

T22

12

T23

7

T64

8

auto[1]

1100

1

T22

8

T23

13

T64

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T22

13

T23

7

T64

10

auto[1]

1132

1

T22

7

T23

13

T64

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T22

1

T23

1

T66

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T64

1

T66

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T22

1

T64

1

T65

2

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T22

1

T23

1

T65

2

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T64

1

T66

2

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T22

2

T65

1

T67

2

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T22

1

T65

2

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T23

2

T64

2

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T22

1

T23

1

T64

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T67

1

T70

2

T398

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T64

1

T65

1

T67

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T23

1

T70

1

T186

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T21

1

T239

1

T37

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T22

1

T23

1

T66

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T22

1

T64

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T23

2

T64

1

T65

2