Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151506	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

114269

1

T4

17

T1

13

T5

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136418	1			T4	22		T1	11		T5	22
values[0x0]	64091	1			T4	12		T1	7		T5	12
values[0x1]	65266	1			T4	10		T1	1		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122738	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143037

1

T4

23

T1

13

T5

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	803	1			T13	4		T7	1		T8	4
valid_sources[0x01]	783	1			T5	1		T8	6		T64	1
valid_sources[0x02]	913	1			T2	7		T14	6		T7	4
valid_sources[0x03]	957	1			T14	8		T8	1		T10	7
valid_sources[0x04]	852	1			T2	5		T13	3		T16	61
valid_sources[0x05]	948	1			T2	1		T13	2		T7	8
valid_sources[0x06]	885	1			T2	1		T13	3		T8	6
valid_sources[0x07]	803	1			T2	3		T13	11		T8	7
valid_sources[0x08]	808	1			T5	1		T2	1		T13	1
valid_sources[0x09]	926	1			T2	3		T8	4		T64	1
valid_sources[0x0a]	833	1			T2	6		T8	5		T64	2
valid_sources[0x0b]	780	1			T5	1		T2	3		T13	2
valid_sources[0x0c]	871	1			T2	3		T13	5		T6	2
valid_sources[0x0d]	1246	1			T2	1		T8	2		T10	3
valid_sources[0x0e]	1007	1			T5	1		T13	2		T8	5
valid_sources[0x0f]	1174	1			T13	1		T8	3		T10	1
valid_sources[0x10]	844	1			T7	5		T8	2		T49	5
valid_sources[0x11]	1150	1			T2	1		T8	2		T64	1
valid_sources[0x12]	869	1			T1	1		T16	9		T8	2
valid_sources[0x13]	1253	1			T2	1		T16	24		T8	4
valid_sources[0x14]	777	1			T1	2		T13	4		T8	3
valid_sources[0x15]	818	1			T1	1		T8	1		T10	7
valid_sources[0x16]	1047	1			T13	2		T8	5		T10	4
valid_sources[0x17]	949	1			T2	2		T13	2		T8	2
valid_sources[0x18]	759	1			T2	1		T8	5		T10	4
valid_sources[0x19]	1240	1			T5	1		T2	4		T8	7
valid_sources[0x1a]	953	1			T8	2		T24	1		T64	1
valid_sources[0x1b]	910	1			T2	1		T8	5		T10	5
valid_sources[0x1c]	789	1			T2	1		T8	3		T10	11
valid_sources[0x1d]	2432	1			T2	1		T13	2		T7	14
valid_sources[0x1e]	831	1			T2	1		T8	5		T38	1
valid_sources[0x1f]	821	1			T5	1		T2	1		T7	17
valid_sources[0x20]	1891	1			T2	18		T6	1		T8	6
valid_sources[0x21]	1057	1			T2	5		T13	2		T6	3
valid_sources[0x22]	937	1			T2	8		T13	11		T8	3
valid_sources[0x23]	1780	1			T2	1		T8	6		T10	2
valid_sources[0x24]	790	1			T5	1		T2	3		T8	1
valid_sources[0x25]	928	1			T6	5		T8	4		T10	3
valid_sources[0x26]	973	1			T2	1		T13	5		T8	4
valid_sources[0x27]	1250	1			T2	1		T13	8		T6	8
valid_sources[0x28]	789	1			T2	8		T8	5		T38	2
valid_sources[0x29]	1065	1			T6	1		T8	5		T10	11
valid_sources[0x2a]	815	1			T2	1		T13	1		T8	1
valid_sources[0x2b]	829	1			T2	12		T7	7		T8	3
valid_sources[0x2c]	1075	1			T2	7		T8	4		T64	1
valid_sources[0x2d]	936	1			T5	1		T2	5		T8	5
valid_sources[0x2e]	783	1			T1	3		T5	1		T2	3
valid_sources[0x2f]	1088	1			T8	6		T64	1		T10	2
valid_sources[0x30]	1138	1			T13	7		T6	4		T8	3
valid_sources[0x31]	778	1			T2	4		T13	1		T8	8
valid_sources[0x32]	954	1			T2	7		T8	3		T10	3
valid_sources[0x33]	919	1			T2	1		T13	5		T8	3
valid_sources[0x34]	843	1			T13	1		T16	48		T8	3
valid_sources[0x35]	909	1			T5	1		T2	2		T13	1
valid_sources[0x36]	818	1			T2	2		T13	3		T8	8
valid_sources[0x37]	851	1			T2	2		T8	2		T64	3
valid_sources[0x38]	1502	1			T2	7		T7	3		T8	3
valid_sources[0x39]	1035	1			T5	1		T2	7		T13	10
valid_sources[0x3a]	908	1			T2	5		T13	3		T8	2
valid_sources[0x3b]	844	1			T6	5		T8	7		T10	4
valid_sources[0x3c]	1002	1			T5	1		T8	5		T10	3
valid_sources[0x3d]	791	1			T2	2		T8	4		T64	2
valid_sources[0x3e]	730	1			T2	2		T13	7		T8	2
valid_sources[0x3f]	981	1			T2	3		T8	4		T64	2
valid_sources[0x40]	2357	1			T7	2		T8	2		T10	2
valid_sources[0x41]	873	1			T8	3		T10	4		T38	5
valid_sources[0x42]	1048	1			T5	1		T2	4		T13	1
valid_sources[0x43]	752	1			T2	4		T13	1		T7	3
valid_sources[0x44]	939	1			T2	6		T8	5		T10	5
valid_sources[0x45]	859	1			T2	1		T14	4		T8	4
valid_sources[0x46]	800	1			T2	2		T8	7		T10	4
valid_sources[0x47]	1410	1			T2	3		T14	20		T7	1
valid_sources[0x48]	904	1			T2	4		T13	2		T7	3
valid_sources[0x49]	1014	1			T2	1		T7	5		T8	5
valid_sources[0x4a]	911	1			T5	1		T2	1		T13	2
valid_sources[0x4b]	792	1			T8	5		T10	6		T28	2
valid_sources[0x4c]	942	1			T2	5		T13	1		T8	7
valid_sources[0x4d]	756	1			T2	1		T8	3		T25	1
valid_sources[0x4e]	785	1			T2	5		T8	3		T10	2
valid_sources[0x4f]	888	1			T2	1		T8	6		T38	4
valid_sources[0x50]	1466	1			T2	1		T13	2		T8	4
valid_sources[0x51]	986	1			T13	1		T8	2		T64	1
valid_sources[0x52]	922	1			T2	5		T8	7		T10	1
valid_sources[0x53]	1073	1			T2	3		T8	3		T10	1
valid_sources[0x54]	1349	1			T2	1		T13	7		T7	1
valid_sources[0x55]	922	1			T2	2		T6	3		T7	3
valid_sources[0x56]	948	1			T2	10		T13	4		T8	8
valid_sources[0x57]	767	1			T7	3		T8	5		T10	4
valid_sources[0x58]	890	1			T7	4		T10	7		T38	1
valid_sources[0x59]	1270	1			T2	4		T13	4		T8	9
valid_sources[0x5a]	1085	1			T5	1		T13	2		T8	5
valid_sources[0x5b]	1321	1			T6	1		T16	32		T8	1
valid_sources[0x5c]	1381	1			T5	1		T8	2		T64	1
valid_sources[0x5d]	959	1			T5	2		T2	5		T16	20
valid_sources[0x5e]	878	1			T7	1		T8	2		T10	3
valid_sources[0x5f]	985	1			T13	6		T7	8		T8	6
valid_sources[0x60]	756	1			T2	7		T13	1		T8	5
valid_sources[0x61]	1099	1			T13	1		T16	8		T8	4
valid_sources[0x62]	1079	1			T2	1		T13	9		T8	8
valid_sources[0x63]	869	1			T13	2		T8	7		T10	4
valid_sources[0x64]	1224	1			T8	4		T25	1		T10	1
valid_sources[0x65]	1084	1			T2	4		T13	2		T7	2
valid_sources[0x66]	1474	1			T5	1		T2	6		T13	10
valid_sources[0x67]	975	1			T13	4		T7	7		T8	2
valid_sources[0x68]	908	1			T13	8		T8	3		T10	1
valid_sources[0x69]	876	1			T2	9		T7	6		T8	2
valid_sources[0x6a]	879	1			T13	1		T8	2		T64	1
valid_sources[0x6b]	1659	1			T2	7		T13	2		T8	7
valid_sources[0x6c]	1757	1			T13	2		T7	1		T8	5
valid_sources[0x6d]	977	1			T2	7		T7	1		T8	4
valid_sources[0x6e]	848	1			T2	4		T6	1		T8	2
valid_sources[0x6f]	773	1			T1	2		T2	4		T7	3
valid_sources[0x70]	790	1			T2	9		T13	1		T6	13
valid_sources[0x71]	1575	1			T2	4		T13	4		T8	4
valid_sources[0x72]	1043	1			T13	5		T8	3		T64	2
valid_sources[0x73]	1182	1			T2	4		T13	1		T6	14
valid_sources[0x74]	983	1			T2	9		T13	2		T8	3
valid_sources[0x75]	1830	1			T7	2		T16	26		T8	2
valid_sources[0x76]	941	1			T13	1		T16	41		T8	4
valid_sources[0x77]	998	1			T2	3		T13	2		T16	13
valid_sources[0x78]	1219	1			T8	4		T24	1		T38	1
valid_sources[0x79]	2616	1			T13	9		T8	4		T10	7
valid_sources[0x7a]	1117	1			T2	2		T8	3		T64	2
valid_sources[0x7b]	858	1			T5	1		T2	10		T16	22
valid_sources[0x7c]	918	1			T2	1		T13	1		T8	6
valid_sources[0x7d]	1231	1			T2	5		T16	25		T8	2
valid_sources[0x7e]	906	1			T5	2		T2	1		T13	4
valid_sources[0x7f]	1736	1			T2	2		T13	3		T6	9
valid_sources[0x80]	844	1			T2	3		T8	8		T10	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61313

1

T4

11

T1

8

T5

11

values[0x0]

all_enables

biggest_size

30956

1

T4

4

T1

5

T5

7

values[0x1]

all_enables

biggest_size

22000

1

T4

2

T5

6

T2

54