Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1194754601	11925	0	0
auto_block_debounce_ctl_rd_A	1194754601	1787	0	0
auto_block_out_ctl_rd_A	1194754601	2150	0	0
com_det_ctl_0_rd_A	1194754601	3703	0	0
com_det_ctl_1_rd_A	1194754601	3982	0	0
com_det_ctl_2_rd_A	1194754601	3941	0	0
com_det_ctl_3_rd_A	1194754601	3852	0	0
com_out_ctl_0_rd_A	1194754601	4090	0	0
com_out_ctl_1_rd_A	1194754601	4087	0	0
com_out_ctl_2_rd_A	1194754601	4130	0	0
com_out_ctl_3_rd_A	1194754601	4152	0	0
com_pre_det_ctl_0_rd_A	1194754601	1461	0	0
com_pre_det_ctl_1_rd_A	1194754601	1367	0	0
com_pre_det_ctl_2_rd_A	1194754601	1365	0	0
com_pre_det_ctl_3_rd_A	1194754601	1338	0	0
com_pre_sel_ctl_0_rd_A	1194754601	4169	0	0
com_pre_sel_ctl_1_rd_A	1194754601	4283	0	0
com_pre_sel_ctl_2_rd_A	1194754601	4162	0	0
com_pre_sel_ctl_3_rd_A	1194754601	4079	0	0
com_sel_ctl_0_rd_A	1194754601	4360	0	0
com_sel_ctl_1_rd_A	1194754601	4114	0	0
com_sel_ctl_2_rd_A	1194754601	4355	0	0
com_sel_ctl_3_rd_A	1194754601	4436	0	0
ec_rst_ctl_rd_A	1194754601	2318	0	0
intr_enable_rd_A	1194754601	1936	0	0
key_intr_ctl_rd_A	1194754601	2933	0	0
key_intr_debounce_ctl_rd_A	1194754601	1433	0	0
key_invert_ctl_rd_A	1194754601	5216	0	0
pin_allowed_ctl_rd_A	1194754601	5244	0	0
pin_out_ctl_rd_A	1194754601	4372	0	0
pin_out_value_rd_A	1194754601	4368	0	0
regwen_rd_A	1194754601	1401	0	0
ulp_ac_debounce_ctl_rd_A	1194754601	1461	0	0
ulp_ctl_rd_A	1194754601	1525	0	0
ulp_lid_debounce_ctl_rd_A	1194754601	1434	0	0
ulp_pwrb_debounce_ctl_rd_A	1194754601	1501	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	11925	0	0
T21	612049	2	0	0
T31	0	10	0	0
T37	0	13	0	0
T44	79942	0	0	0
T45	44161	0	0	0
T55	0	15	0	0
T61	20395	0	0	0
T71	0	23	0	0
T74	0	3	0	0
T76	714332	0	0	0
T142	0	17	0	0
T182	123624	0	0	0
T183	137133	0	0	0
T184	198254	0	0	0
T185	69989	0	0	0
T186	241000	0	0	0
T210	0	9	0	0
T249	0	10	0	0
T316	0	8	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1787	0	0
T10	235409	0	0	0
T11	298080	0	0	0
T21	0	8	0	0
T22	103339	0	0	0
T23	63218	0	0	0
T24	277507	10	0	0
T25	69661	0	0	0
T27	207632	0	0	0
T31	0	39	0	0
T37	0	23	0	0
T40	0	5	0	0
T46	0	17	0	0
T55	0	4	0	0
T64	125556	0	0	0
T93	204599	0	0	0
T94	105806	0	0	0
T297	0	7	0	0
T316	0	31	0	0
T317	0	13	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	2150	0	0
T10	235409	0	0	0
T11	298080	0	0	0
T21	0	15	0	0
T22	103339	0	0	0
T23	63218	0	0	0
T24	277507	4	0	0
T25	69661	0	0	0
T27	207632	0	0	0
T31	0	64	0	0
T37	0	23	0	0
T40	0	1	0	0
T46	0	18	0	0
T55	0	34	0	0
T64	125556	0	0	0
T93	204599	0	0	0
T94	105806	0	0	0
T297	0	8	0	0
T316	0	63	0	0
T317	0	4	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	3703	0	0
T2	164239	78	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	53	0	0
T9	256188	0	0	0
T10	0	56	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	10	0	0
T51	0	69	0	0
T55	0	11	0	0
T82	0	42	0	0
T91	0	68	0	0
T127	0	89	0	0
T128	0	36	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	3982	0	0
T2	164239	73	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	50	0	0
T9	256188	0	0	0
T10	0	79	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	19	0	0
T51	0	47	0	0
T55	0	12	0	0
T82	0	32	0	0
T91	0	31	0	0
T127	0	70	0	0
T128	0	40	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	3941	0	0
T2	164239	71	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	68	0	0
T9	256188	0	0	0
T10	0	67	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	10	0	0
T51	0	43	0	0
T55	0	16	0	0
T82	0	43	0	0
T91	0	37	0	0
T127	0	66	0	0
T128	0	49	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	3852	0	0
T2	164239	81	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	40	0	0
T9	256188	0	0	0
T10	0	56	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	10	0	0
T51	0	34	0	0
T55	0	9	0	0
T82	0	26	0	0
T91	0	54	0	0
T127	0	71	0	0
T128	0	51	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4090	0	0
T2	164239	52	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	41	0	0
T9	256188	0	0	0
T10	0	71	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	15	0	0
T51	0	16	0	0
T55	0	21	0	0
T82	0	39	0	0
T91	0	29	0	0
T127	0	88	0	0
T128	0	50	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4087	0	0
T2	164239	78	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	63	0	0
T9	256188	0	0	0
T10	0	70	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	8	0	0
T51	0	50	0	0
T55	0	10	0	0
T82	0	47	0	0
T91	0	50	0	0
T127	0	90	0	0
T128	0	56	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4130	0	0
T2	164239	77	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	59	0	0
T9	256188	0	0	0
T10	0	89	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	3	0	0
T51	0	28	0	0
T55	0	3	0	0
T82	0	40	0	0
T91	0	54	0	0
T127	0	82	0	0
T128	0	51	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4152	0	0
T2	164239	59	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	53	0	0
T9	256188	0	0	0
T10	0	85	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	13	0	0
T51	0	17	0	0
T55	0	23	0	0
T82	0	43	0	0
T91	0	68	0	0
T127	0	67	0	0
T128	0	39	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1461	0	0
T21	612049	17	0	0
T31	0	43	0	0
T37	0	14	0	0
T44	79942	0	0	0
T45	44161	0	0	0
T55	0	15	0	0
T61	20395	0	0	0
T74	0	22	0	0
T76	714332	0	0	0
T142	0	25	0	0
T163	0	28	0	0
T182	123624	0	0	0
T183	137133	0	0	0
T184	198254	0	0	0
T185	69989	0	0	0
T186	241000	0	0	0
T197	0	13	0	0
T216	0	14	0	0
T316	0	55	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1367	0	0
T21	612049	6	0	0
T31	0	23	0	0
T37	0	13	0	0
T44	79942	0	0	0
T45	44161	0	0	0
T55	0	15	0	0
T61	20395	0	0	0
T74	0	23	0	0
T76	714332	0	0	0
T142	0	20	0	0
T163	0	3	0	0
T182	123624	0	0	0
T183	137133	0	0	0
T184	198254	0	0	0
T185	69989	0	0	0
T186	241000	0	0	0
T197	0	32	0	0
T216	0	6	0	0
T316	0	40	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1365	0	0
T21	612049	21	0	0
T31	0	38	0	0
T37	0	25	0	0
T44	79942	0	0	0
T45	44161	0	0	0
T55	0	5	0	0
T61	20395	0	0	0
T74	0	22	0	0
T76	714332	0	0	0
T142	0	16	0	0
T163	0	6	0	0
T182	123624	0	0	0
T183	137133	0	0	0
T184	198254	0	0	0
T185	69989	0	0	0
T186	241000	0	0	0
T197	0	12	0	0
T216	0	8	0	0
T316	0	60	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1338	0	0
T21	612049	16	0	0
T31	0	27	0	0
T37	0	20	0	0
T44	79942	0	0	0
T45	44161	0	0	0
T55	0	9	0	0
T61	20395	0	0	0
T74	0	26	0	0
T76	714332	0	0	0
T142	0	28	0	0
T163	0	15	0	0
T182	123624	0	0	0
T183	137133	0	0	0
T184	198254	0	0	0
T185	69989	0	0	0
T186	241000	0	0	0
T197	0	12	0	0
T316	0	38	0	0
T318	0	9	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4169	0	0
T2	164239	70	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	60	0	0
T9	256188	0	0	0
T10	0	71	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	10	0	0
T51	0	77	0	0
T55	0	15	0	0
T82	0	44	0	0
T91	0	50	0	0
T127	0	84	0	0
T128	0	52	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4283	0	0
T2	164239	73	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	62	0	0
T9	256188	0	0	0
T10	0	61	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	4	0	0
T51	0	41	0	0
T55	0	21	0	0
T82	0	44	0	0
T91	0	74	0	0
T127	0	58	0	0
T128	0	42	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4162	0	0
T2	164239	48	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	60	0	0
T9	256188	0	0	0
T10	0	54	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	17	0	0
T51	0	54	0	0
T55	0	15	0	0
T82	0	39	0	0
T91	0	53	0	0
T127	0	95	0	0
T128	0	49	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4079	0	0
T2	164239	86	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	58	0	0
T9	256188	0	0	0
T10	0	65	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	11	0	0
T51	0	32	0	0
T55	0	10	0	0
T82	0	17	0	0
T91	0	57	0	0
T127	0	72	0	0
T128	0	49	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4360	0	0
T2	164239	67	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	67	0	0
T9	256188	0	0	0
T10	0	70	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	22	0	0
T51	0	47	0	0
T55	0	16	0	0
T82	0	37	0	0
T91	0	56	0	0
T127	0	71	0	0
T128	0	40	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4114	0	0
T2	164239	61	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	66	0	0
T9	256188	0	0	0
T10	0	66	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	6	0	0
T51	0	44	0	0
T55	0	28	0	0
T82	0	46	0	0
T91	0	45	0	0
T127	0	68	0	0
T128	0	38	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4355	0	0
T2	164239	102	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	62	0	0
T9	256188	0	0	0
T10	0	55	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	5	0	0
T51	0	32	0	0
T55	0	18	0	0
T82	0	37	0	0
T91	0	59	0	0
T127	0	50	0	0
T128	0	43	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4436	0	0
T2	164239	65	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	61	0	0
T9	256188	0	0	0
T10	0	62	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T37	0	18	0	0
T51	0	31	0	0
T55	0	9	0	0
T82	0	55	0	0
T91	0	41	0	0
T127	0	62	0	0
T128	0	56	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	2318	0	0
T2	164239	54	0	0
T3	97596	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T8	113829	22	0	0
T9	256188	0	0	0
T10	0	24	0	0
T13	279695	4	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T21	0	1	0	0
T34	0	2	0	0
T49	0	1	0	0
T51	0	10	0	0
T91	0	4	0	0
T127	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1936	0	0
T17	58766	0	0	0
T21	0	28	0	0
T28	491335	0	0	0
T31	0	31	0	0
T34	994020	9	0	0
T37	0	59	0	0
T39	46378	0	0	0
T40	339619	0	0	0
T52	160473	0	0	0
T53	66951	0	0	0
T55	0	25	0	0
T74	0	11	0	0
T129	12738	0	0	0
T130	48710	0	0	0
T142	0	48	0	0
T163	0	49	0	0
T216	0	39	0	0
T256	215882	0	0	0
T316	0	46	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	2933	0	0
T9	256188	5	0	0
T21	0	15	0	0
T22	103339	0	0	0
T23	63218	0	0	0
T24	277507	0	0	0
T25	69661	0	0	0
T27	207632	0	0	0
T31	0	42	0	0
T34	0	3	0	0
T37	0	27	0	0
T49	23027	0	0	0
T55	0	25	0	0
T64	125556	0	0	0
T74	0	24	0	0
T93	204599	0	0	0
T94	105806	0	0	0
T188	0	3	0	0
T196	0	2	0	0
T316	0	49	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1433	0	0
T21	612049	14	0	0
T31	0	25	0	0
T37	0	14	0	0
T44	79942	0	0	0
T45	44161	0	0	0
T55	0	18	0	0
T61	20395	0	0	0
T74	0	31	0	0
T76	714332	0	0	0
T142	0	26	0	0
T163	0	17	0	0
T182	123624	0	0	0
T183	137133	0	0	0
T184	198254	0	0	0
T185	69989	0	0	0
T186	241000	0	0	0
T197	0	5	0	0
T216	0	9	0	0
T316	0	21	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	5216	0	0
T21	612049	76	0	0
T31	0	36	0	0
T37	0	41	0	0
T44	79942	0	0	0
T45	44161	0	0	0
T55	0	226	0	0
T61	20395	0	0	0
T74	0	79	0	0
T76	714332	0	0	0
T142	0	110	0	0
T182	123624	0	0	0
T183	137133	0	0	0
T184	198254	0	0	0
T185	69989	0	0	0
T186	241000	0	0	0
T216	0	90	0	0
T316	0	28	0	0
T319	0	72	0	0
T320	0	78	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	5244	0	0
T21	0	108	0	0
T29	115695	0	0	0
T30	948536	0	0	0
T31	0	109	0	0
T37	0	65	0	0
T41	118034	0	0	0
T42	334844	0	0	0
T55	0	7	0	0
T67	238795	74	0	0
T68	241293	0	0	0
T69	44992	0	0	0
T186	0	79	0	0
T250	0	16	0	0
T284	0	69	0	0
T287	351479	0	0	0
T300	213550	0	0	0
T316	0	117	0	0
T321	0	79	0	0
T322	216658	0	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4372	0	0
T21	0	81	0	0
T29	115695	0	0	0
T30	948536	0	0	0
T31	0	59	0	0
T37	0	114	0	0
T41	118034	0	0	0
T42	334844	0	0	0
T55	0	11	0	0
T67	238795	47	0	0
T68	241293	0	0	0
T69	44992	0	0	0
T186	0	65	0	0
T250	0	51	0	0
T284	0	46	0	0
T287	351479	0	0	0
T300	213550	0	0	0
T316	0	111	0	0
T321	0	59	0	0
T322	216658	0	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	4368	0	0
T21	0	79	0	0
T29	115695	0	0	0
T30	948536	0	0	0
T31	0	104	0	0
T37	0	67	0	0
T41	118034	0	0	0
T42	334844	0	0	0
T55	0	23	0	0
T67	238795	94	0	0
T68	241293	0	0	0
T69	44992	0	0	0
T186	0	49	0	0
T250	0	32	0	0
T284	0	57	0	0
T287	351479	0	0	0
T300	213550	0	0	0
T316	0	91	0	0
T321	0	58	0	0
T322	216658	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1401	0	0
T21	612049	15	0	0
T31	0	37	0	0
T37	0	18	0	0
T44	79942	0	0	0
T45	44161	0	0	0
T55	0	7	0	0
T61	20395	0	0	0
T74	0	6	0	0
T76	714332	0	0	0
T142	0	30	0	0
T163	0	18	0	0
T182	123624	0	0	0
T183	137133	0	0	0
T184	198254	0	0	0
T185	69989	0	0	0
T186	241000	0	0	0
T197	0	16	0	0
T216	0	20	0	0
T316	0	29	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1461	0	0
T17	58766	15	0	0
T21	0	5	0	0
T28	491335	0	0	0
T31	0	27	0	0
T37	0	8	0	0
T39	46378	0	0	0
T40	339619	0	0	0
T53	66951	0	0	0
T55	0	7	0	0
T56	0	12	0	0
T67	238795	0	0	0
T68	241293	0	0	0
T74	0	22	0	0
T129	12738	0	0	0
T130	48710	0	0	0
T142	0	17	0	0
T216	0	15	0	0
T286	204633	0	0	0
T316	0	39	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1525	0	0
T1	110380	2	0	0
T2	164239	0	0	0
T3	97596	0	0	0
T5	118028	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T17	0	5	0	0
T21	0	13	0	0
T31	0	30	0	0
T37	0	13	0	0
T55	0	28	0	0
T56	0	16	0	0
T74	0	9	0	0
T142	0	18	0	0
T316	0	45	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1434	0	0
T17	58766	6	0	0
T21	0	14	0	0
T28	491335	0	0	0
T31	0	29	0	0
T37	0	24	0	0
T39	46378	0	0	0
T40	339619	0	0	0
T53	66951	0	0	0
T55	0	36	0	0
T56	0	19	0	0
T67	238795	0	0	0
T68	241293	0	0	0
T74	0	23	0	0
T129	12738	0	0	0
T130	48710	0	0	0
T142	0	30	0	0
T216	0	9	0	0
T286	204633	0	0	0
T316	0	35	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194754601	1501	0	0
T1	110380	7	0	0
T2	164239	0	0	0
T3	97596	0	0	0
T5	118028	0	0	0
T6	753487	0	0	0
T7	147216	0	0	0
T13	279695	0	0	0
T14	242569	0	0	0
T15	198340	0	0	0
T16	238890	0	0	0
T17	0	1	0	0
T21	0	21	0	0
T31	0	26	0	0
T37	0	4	0	0
T55	0	17	0	0
T56	0	9	0	0
T74	0	23	0	0
T142	0	20	0	0
T316	0	45	0	0