Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T17,T54

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T17,T54
1	1	Covered	T1,T2,T13

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	221505	0	0
SrcPulseCheck_M	2147483647	224152	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	221505
T1	781628	0
T2	4178957	42
T3	2960709	0
T4	705804	0
T5	830132	0
T6	22699687	0
T7	4981378	16
T8	3551470	18
T9	6676696	0
T10	0	15
T13	8284135	3
T14	7292260	0
T15	6559092	0
T16	7783817	21
T22	311526	0
T23	191169	0
T24	1113064	14
T25	210882	14
T28	0	9
T30	0	18
T38	0	3
T39	0	2
T40	0	12
T41	0	3
T42	0	1
T43	0	16
T44	0	16
T45	0	18
T46	0	14
T47	0	16
T48	0	16
T49	284220	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	224152
T1	890887	0
T2	4310017	42
T3	3057246	0
T4	705804	0
T5	947668	0
T6	23450107	0
T7	5124969	16
T8	3551470	18
T9	6676696	0
T10	0	15
T13	8558064	3
T14	7534339	0
T15	6757024	0
T16	8002800	21
T22	311526	0
T23	191169	0
T24	1113064	14
T25	210882	14
T28	0	9
T30	0	18
T38	0	3
T39	0	2
T40	0	12
T41	0	3
T42	0	1
T43	0	16
T44	0	16
T45	0	18
T46	0	14
T47	0	16
T48	0	16
T49	284220	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T18,T306,T339

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T18,T306,T339
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1847	0	0
SrcPulseCheck_M	1194754601	1927	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1847
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T34	0	1
T38	0	1
T49	0	1
T52	0	1
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1927
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T34	0	1
T38	0	1
T49	0	1
T52	0	1
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T18,T306,T339

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T18,T306,T339
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1920	0	0
SrcPulseCheck_M	8477978	1920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1920
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T34	0	1
T38	0	1
T49	0	1
T52	0	1
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1920
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T34	0	1
T38	0	1
T49	0	1
T52	0	1
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T1,T27,T17
1	1	Covered	T17,T54,T56

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T17,T54,T56
1	1	Covered	T1,T27,T17

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	816	0	0
SrcPulseCheck_M	1194754601	893	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	816
T1	1121	1
T2	33179	0
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	893
T1	110380	1
T2	164239	0
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T1,T27,T17
1	1	Covered	T17,T54,T56

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T17,T54,T56
1	1	Covered	T1,T27,T17

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	886	0	0
SrcPulseCheck_M	8477978	886	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	886
T1	110380	1
T2	164239	0
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	886
T1	1121	1
T2	33179	0
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T1,T27,T17
1	1	Covered	T17,T54,T56

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T17,T54,T56
1	1	Covered	T1,T27,T17

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	851	0	0
SrcPulseCheck_M	1194754601	927	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	851
T1	1121	1
T2	33179	0
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	927
T1	110380	1
T2	164239	0
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T1,T27,T17
1	1	Covered	T17,T54,T56

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T17,T54,T56
1	1	Covered	T1,T27,T17

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	920	0	0
SrcPulseCheck_M	8477978	920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	920
T1	110380	1
T2	164239	0
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	920
T1	1121	1
T2	33179	0
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T1,T27,T17
1	1	Covered	T17,T54,T56

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T17,T54,T56
1	1	Covered	T1,T27,T17

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	852	0	0
SrcPulseCheck_M	1194754601	930	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	852
T1	1121	1
T2	33179	0
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	930
T1	110380	1
T2	164239	0
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T1,T27,T17
1	1	Covered	T17,T54,T56

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T27,T17
1	0	Covered	T17,T54,T56
1	1	Covered	T1,T27,T17

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	922	0	0
SrcPulseCheck_M	8477978	922	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	922
T1	110380	1
T2	164239	0
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	922
T1	1121	1
T2	33179	0
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	2
T21	0	1
T27	0	1
T54	0	3
T55	0	2
T56	0	3
T57	0	3
T58	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T17,T21
1	0	Covered	T1,T17,T21
1	1	Covered	T1,T17,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T17,T21
1	0	Covered	T1,T17,T21
1	1	Covered	T1,T17,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	820	0	0
SrcPulseCheck_M	1194754601	900	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	820
T1	1121	2
T2	33179	0
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	2
T21	0	2
T54	0	2
T57	0	2
T71	0	2
T72	0	2
T73	0	2
T74	0	1
T75	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	900
T1	110380	2
T2	164239	0
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	2
T21	0	2
T54	0	2
T57	0	2
T71	0	2
T72	0	2
T73	0	2
T74	0	1
T75	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T17,T21
1	0	Covered	T1,T17,T21
1	1	Covered	T1,T17,T21

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T17,T21
1	0	Covered	T1,T17,T21
1	1	Covered	T1,T17,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	892	0	0
SrcPulseCheck_M	8477978	892	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	892
T1	110380	2
T2	164239	0
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	2
T21	0	2
T54	0	2
T57	0	2
T71	0	2
T72	0	2
T73	0	2
T74	0	1
T75	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	892
T1	1121	2
T2	33179	0
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	2
T21	0	2
T54	0	2
T57	0	2
T71	0	2
T72	0	2
T73	0	2
T74	0	1
T75	0	2

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8
1	1	Covered	T32,T82,T97

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T8
1	0	Covered	T32,T82,T97
1	1	Covered	T1,T2,T8

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1130	0	0
SrcPulseCheck_M	1194754601	1209	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1130
T1	1121	1
T2	33179	13
T3	1059	0
T5	492	0
T6	3067	0
T7	3625	0
T8	0	2
T10	0	4
T13	5766	0
T14	490	0
T15	408	0
T16	19907	0
T17	0	1
T21	0	1
T28	0	3
T29	0	6
T30	0	5
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1209
T1	110380	1
T2	164239	13
T3	97596	0
T5	118028	0
T6	753487	0
T7	147216	0
T8	0	2
T10	0	4
T13	279695	0
T14	242569	0
T15	198340	0
T16	238890	0
T17	0	1
T21	0	1
T28	0	3
T29	0	6
T30	0	5
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T14
1	1	Covered	T4,T5,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T14
1	1	Covered	T4,T5,T14

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	2904	0	0
SrcPulseCheck_M	1194754601	2984	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	2904
T1	1121	0
T2	33179	0
T3	1059	0
T4	494	20
T5	492	20
T6	3067	0
T7	3625	20
T13	5766	0
T14	490	20
T15	408	0
T21	0	20
T55	0	100
T60	0	20
T61	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	2984
T1	110380	0
T2	164239	0
T3	97596	0
T4	234774	20
T5	118028	20
T6	753487	0
T7	147216	20
T13	279695	0
T14	242569	20
T15	198340	0
T21	0	20
T55	0	100
T60	0	20
T61	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T14
1	1	Covered	T4,T5,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T14
1	1	Covered	T4,T5,T14

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	2976	0	0
SrcPulseCheck_M	8477978	2976	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	2976
T1	110380	0
T2	164239	0
T3	97596	0
T4	234774	20
T5	118028	20
T6	753487	0
T7	147216	20
T13	279695	0
T14	242569	20
T15	198340	0
T21	0	20
T55	0	100
T60	0	20
T61	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	2976
T1	1121	0
T2	33179	0
T3	1059	0
T4	494	20
T5	492	20
T6	3067	0
T7	3625	20
T13	5766	0
T14	490	20
T15	408	0
T21	0	20
T55	0	100
T60	0	20
T61	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T14
1	1	Covered	T7,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T14
1	0	Covered	T7,T22,T23
1	1	Covered	T4,T5,T14

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	6036	0	0
SrcPulseCheck_M	1194754601	6112	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	6036
T1	1121	0
T2	33179	0
T3	1059	0
T4	494	1
T5	492	1
T6	3067	0
T7	3625	41
T13	5766	0
T14	490	1
T15	408	0
T22	0	20
T23	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	6112
T1	110380	0
T2	164239	0
T3	97596	0
T4	234774	1
T5	118028	1
T6	753487	0
T7	147216	41
T13	279695	0
T14	242569	1
T15	198340	0
T22	0	20
T23	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T14
1	1	Covered	T7,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T14
1	0	Covered	T7,T22,T23
1	1	Covered	T4,T5,T14

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	6103	0	0
SrcPulseCheck_M	8477978	6103	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	6103
T1	110380	0
T2	164239	0
T3	97596	0
T4	234774	1
T5	118028	1
T6	753487	0
T7	147216	41
T13	279695	0
T14	242569	1
T15	198340	0
T22	0	20
T23	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	6103
T1	1121	0
T2	33179	0
T3	1059	0
T4	494	1
T5	492	1
T6	3067	0
T7	3625	41
T13	5766	0
T14	490	1
T15	408	0
T22	0	20
T23	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T2
1	1	Covered	T7,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T2
1	0	Covered	T7,T22,T23
1	1	Covered	T4,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	7235	0	0
SrcPulseCheck_M	1194754601	7317	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	7235
T1	1121	0
T2	33179	14
T3	1059	0
T4	494	1
T5	492	1
T6	3067	0
T7	3625	41
T8	0	6
T13	5766	1
T14	490	1
T15	408	0
T16	0	7
T22	0	20
T49	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7317
T1	110380	0
T2	164239	14
T3	97596	0
T4	234774	1
T5	118028	1
T6	753487	0
T7	147216	41
T8	0	6
T13	279695	1
T14	242569	1
T15	198340	0
T16	0	7
T22	0	20
T49	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T2
1	0	Covered	T4,T5,T2
1	1	Covered	T7,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T4,T5,T2
1	0	Covered	T7,T22,T23
1	1	Covered	T4,T5,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7307	0	0
SrcPulseCheck_M	8477978	7307	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7307
T1	110380	0
T2	164239	14
T3	97596	0
T4	234774	1
T5	118028	1
T6	753487	0
T7	147216	41
T8	0	6
T13	279695	1
T14	242569	1
T15	198340	0
T16	0	7
T22	0	20
T49	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7307
T1	1121	0
T2	33179	14
T3	1059	0
T4	494	1
T5	492	1
T6	3067	0
T7	3625	41
T8	0	6
T13	5766	1
T14	490	1
T15	408	0
T16	0	7
T22	0	20
T49	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T22,T23
1	0	Covered	T7,T22,T23
1	1	Covered	T7,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T22,T23
1	0	Covered	T7,T22,T23
1	1	Covered	T7,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	5959	0	0
SrcPulseCheck_M	1194754601	6041	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	5959
T7	3625	40
T8	22766	0
T9	608	0
T15	408	0
T16	19907	0
T22	503	20
T23	505	20
T24	759	0
T25	633	0
T49	658	0
T64	0	20
T65	0	20
T66	0	20
T67	0	20
T68	0	20
T69	0	20
T70	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	6041
T7	147216	40
T8	113829	0
T9	256188	0
T15	198340	0
T16	238890	0
T22	103339	20
T23	63218	20
T24	277507	0
T25	69661	0
T49	23027	0
T64	0	20
T65	0	20
T66	0	20
T67	0	20
T68	0	20
T69	0	20
T70	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T22,T23
1	0	Covered	T7,T22,T23
1	1	Covered	T7,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T22,T23
1	0	Covered	T7,T22,T23
1	1	Covered	T7,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	6031	0	0
SrcPulseCheck_M	8477978	6031	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	6031
T7	147216	40
T8	113829	0
T9	256188	0
T15	198340	0
T16	238890	0
T22	103339	20
T23	63218	20
T24	277507	0
T25	69661	0
T49	23027	0
T64	0	20
T65	0	20
T66	0	20
T67	0	20
T68	0	20
T69	0	20
T70	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	6031
T7	3625	40
T8	22766	0
T9	608	0
T15	408	0
T16	19907	0
T22	503	20
T23	505	20
T24	759	0
T25	633	0
T49	658	0
T64	0	20
T65	0	20
T66	0	20
T67	0	20
T68	0	20
T69	0	20
T70	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T3,T6,T7
1	0	Covered	T78,T50,T18
1	1	Covered	T3,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	874	0	0
SrcPulseCheck_M	1194754601	952	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	874
T3	1059	1
T6	3067	2
T7	3625	1
T8	22766	0
T9	608	1
T11	0	1
T12	0	1
T14	490	0
T15	408	0
T16	19907	0
T21	0	1
T24	759	0
T33	0	1
T34	0	1
T35	0	1
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	952
T3	97596	1
T6	753487	2
T7	147216	1
T8	113829	0
T9	256188	1
T11	0	1
T12	0	1
T14	242569	0
T15	198340	0
T16	238890	0
T21	0	1
T24	277507	0
T33	0	1
T34	0	1
T35	0	1
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T3,T6,T7
1	0	Covered	T78,T50,T18
1	1	Covered	T3,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	945	0	0
SrcPulseCheck_M	8477978	945	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	945
T3	97596	1
T6	753487	2
T7	147216	1
T8	113829	0
T9	256188	1
T11	0	1
T12	0	1
T14	242569	0
T15	198340	0
T16	238890	0
T21	0	1
T24	277507	0
T33	0	1
T34	0	1
T35	0	1
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	945
T3	1059	1
T6	3067	2
T7	3625	1
T8	22766	0
T9	608	1
T11	0	1
T12	0	1
T14	490	0
T15	408	0
T16	19907	0
T21	0	1
T24	759	0
T33	0	1
T34	0	1
T35	0	1
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1842	0	0
SrcPulseCheck_M	1194754601	1921	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1842
T2	33179	14
T3	1059	1
T6	3067	2
T7	3625	1
T8	22766	6
T9	608	1
T10	0	5
T11	0	1
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1921
T2	164239	14
T3	97596	1
T6	753487	2
T7	147216	1
T8	113829	6
T9	256188	1
T10	0	5
T11	0	1
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1913	0	0
SrcPulseCheck_M	8477978	1913	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1913
T2	164239	14
T3	97596	1
T6	753487	2
T7	147216	1
T8	113829	6
T9	256188	1
T10	0	5
T11	0	1
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1913
T2	33179	14
T3	1059	1
T6	3067	2
T7	3625	1
T8	22766	6
T9	608	1
T10	0	5
T11	0	1
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T24,T25
1	0	Covered	T7,T24,T25
1	1	Covered	T7,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T24,T25
1	0	Covered	T7,T24,T25
1	1	Covered	T7,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1244	0	0
SrcPulseCheck_M	1194754601	1323	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1244
T7	3625	5
T8	22766	0
T9	608	0
T15	408	0
T16	19907	0
T22	503	0
T23	505	0
T24	759	4
T25	633	4
T40	0	3
T43	0	5
T44	0	5
T45	0	6
T46	0	4
T47	0	5
T48	0	5
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1323
T7	147216	5
T8	113829	0
T9	256188	0
T15	198340	0
T16	238890	0
T22	103339	0
T23	63218	0
T24	277507	4
T25	69661	4
T40	0	3
T43	0	5
T44	0	5
T45	0	6
T46	0	4
T47	0	5
T48	0	5
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T24,T25
1	0	Covered	T7,T24,T25
1	1	Covered	T7,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T24,T25
1	0	Covered	T7,T24,T25
1	1	Covered	T7,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1316	0	0
SrcPulseCheck_M	8477978	1316	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1316
T7	147216	5
T8	113829	0
T9	256188	0
T15	198340	0
T16	238890	0
T22	103339	0
T23	63218	0
T24	277507	4
T25	69661	4
T40	0	3
T43	0	5
T44	0	5
T45	0	6
T46	0	4
T47	0	5
T48	0	5
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1316
T7	3625	5
T8	22766	0
T9	608	0
T15	408	0
T16	19907	0
T22	503	0
T23	505	0
T24	759	4
T25	633	4
T40	0	3
T43	0	5
T44	0	5
T45	0	6
T46	0	4
T47	0	5
T48	0	5
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T24,T25
1	0	Covered	T7,T24,T25
1	1	Covered	T7,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T24,T25
1	0	Covered	T7,T24,T25
1	1	Covered	T7,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1046	0	0
SrcPulseCheck_M	1194754601	1118	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1046
T7	3625	3
T8	22766	0
T9	608	0
T15	408	0
T16	19907	0
T22	503	0
T23	505	0
T24	759	3
T25	633	3
T40	0	3
T43	0	3
T44	0	3
T45	0	3
T46	0	3
T47	0	3
T48	0	3
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1118
T7	147216	3
T8	113829	0
T9	256188	0
T15	198340	0
T16	238890	0
T22	103339	0
T23	63218	0
T24	277507	3
T25	69661	3
T40	0	3
T43	0	3
T44	0	3
T45	0	3
T46	0	3
T47	0	3
T48	0	3
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T24,T25
1	0	Covered	T7,T24,T25
1	1	Covered	T7,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T7,T24,T25
1	0	Covered	T7,T24,T25
1	1	Covered	T7,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1111	0	0
SrcPulseCheck_M	8477978	1111	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1111
T7	147216	3
T8	113829	0
T9	256188	0
T15	198340	0
T16	238890	0
T22	103339	0
T23	63218	0
T24	277507	3
T25	69661	3
T40	0	3
T43	0	3
T44	0	3
T45	0	3
T46	0	3
T47	0	3
T48	0	3
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1111
T7	3625	3
T8	22766	0
T9	608	0
T15	408	0
T16	19907	0
T22	503	0
T23	505	0
T24	759	3
T25	633	3
T40	0	3
T43	0	3
T44	0	3
T45	0	3
T46	0	3
T47	0	3
T48	0	3
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	7020	0	0
SrcPulseCheck_M	1194754601	7095	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	7020
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	86
T9	608	0
T10	0	85
T13	5766	51
T14	490	0
T15	408	0
T16	19907	72
T28	0	65
T30	0	72
T38	0	74
T39	0	1
T41	0	51
T42	0	82
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7095
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	86
T9	256188	0
T10	0	85
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	72
T28	0	65
T30	0	72
T38	0	74
T39	0	1
T41	0	51
T42	0	83
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7088	0	0
SrcPulseCheck_M	8477978	7088	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7088
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	86
T9	256188	0
T10	0	85
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	72
T28	0	65
T30	0	72
T38	0	74
T39	0	1
T41	0	51
T42	0	83
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7088
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	86
T9	608	0
T10	0	85
T13	5766	51
T14	490	0
T15	408	0
T16	19907	72
T28	0	65
T30	0	72
T38	0	74
T39	0	1
T41	0	51
T42	0	83
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	6941	0	0
SrcPulseCheck_M	1194754601	7018	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	6941
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	80
T9	608	0
T10	0	61
T13	5766	51
T14	490	0
T15	408	0
T16	19907	89
T28	0	87
T29	0	78
T30	0	76
T38	0	74
T41	0	51
T42	0	66
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7018
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	80
T9	256188	0
T10	0	61
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	89
T28	0	87
T29	0	78
T30	0	76
T38	0	74
T41	0	51
T42	0	66
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7010	0	0
SrcPulseCheck_M	8477978	7010	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7010
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	80
T9	256188	0
T10	0	61
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	89
T28	0	87
T29	0	78
T30	0	76
T38	0	74
T41	0	51
T42	0	66
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7010
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	80
T9	608	0
T10	0	61
T13	5766	51
T14	490	0
T15	408	0
T16	19907	89
T28	0	87
T29	0	78
T30	0	76
T38	0	74
T41	0	51
T42	0	66
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	7076	0	0
SrcPulseCheck_M	1194754601	7153	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	7076
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	74
T9	608	0
T10	0	85
T13	5766	51
T14	490	0
T15	408	0
T16	19907	71
T28	0	70
T29	0	77
T30	0	64
T38	0	51
T41	0	51
T42	0	71
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7153
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	74
T9	256188	0
T10	0	85
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	71
T28	0	70
T29	0	77
T30	0	64
T38	0	51
T41	0	51
T42	0	72
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7146	0	0
SrcPulseCheck_M	8477978	7146	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7146
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	74
T9	256188	0
T10	0	85
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	71
T28	0	70
T29	0	77
T30	0	64
T38	0	51
T41	0	51
T42	0	72
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7146
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	74
T9	608	0
T10	0	85
T13	5766	51
T14	490	0
T15	408	0
T16	19907	71
T28	0	70
T29	0	77
T30	0	64
T38	0	51
T41	0	51
T42	0	72
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	6972	0	0
SrcPulseCheck_M	1194754601	7049	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	6972
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	58
T9	608	0
T10	0	72
T13	5766	51
T14	490	0
T15	408	0
T16	19907	94
T28	0	78
T29	0	102
T30	0	78
T38	0	74
T41	0	51
T42	0	73
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7049
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	58
T9	256188	0
T10	0	72
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	94
T28	0	78
T29	0	102
T30	0	78
T38	0	74
T41	0	51
T42	0	73
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7042	0	0
SrcPulseCheck_M	8477978	7042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7042
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	58
T9	256188	0
T10	0	72
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	94
T28	0	78
T29	0	102
T30	0	78
T38	0	74
T41	0	51
T42	0	73
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7042
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	58
T9	608	0
T10	0	72
T13	5766	51
T14	490	0
T15	408	0
T16	19907	94
T28	0	78
T29	0	102
T30	0	78
T38	0	74
T41	0	51
T42	0	73
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T78,T50,T18
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1087	0	0
SrcPulseCheck_M	1194754601	1167	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1087
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1
T42	0	1
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1167
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1
T42	0	1
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T78,T50,T18
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1159	0	0
SrcPulseCheck_M	8477978	1159	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1159
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1
T42	0	1
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1159
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1
T42	0	1
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T78,T50,T18
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1087	0	0
SrcPulseCheck_M	1194754601	1164	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1087
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1164
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T78,T50,T18
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1156	0	0
SrcPulseCheck_M	8477978	1156	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1156
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1156
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T78,T50,T18
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1072	0	0
SrcPulseCheck_M	1194754601	1148	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1072
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1148
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T78,T50,T18
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1141	0	0
SrcPulseCheck_M	8477978	1141	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1141
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1141
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T78,T50,T18
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1083	0	0
SrcPulseCheck_M	1194754601	1161	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1083
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	658	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1161
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	23027	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T13,T16,T8
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T13,T16,T8
1	0	Covered	T78,T50,T18
1	1	Covered	T13,T16,T8

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1154	0	0
SrcPulseCheck_M	8477978	1154	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1154
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	23027	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1154
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T29	0	7
T30	0	6
T38	0	1
T41	0	1
T42	0	1
T49	658	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T13,T16,T8
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	7668	0	0
SrcPulseCheck_M	1194754601	7748	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	7668
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	86
T9	608	0
T10	0	85
T13	5766	51
T14	490	0
T15	408	0
T16	19907	72
T28	0	65
T30	0	72
T38	0	74
T39	0	1
T41	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7748
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	86
T9	256188	0
T10	0	85
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	72
T28	0	65
T30	0	72
T38	0	74
T39	0	1
T41	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T13,T16,T8
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7741	0	0
SrcPulseCheck_M	8477978	7741	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7741
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	86
T9	256188	0
T10	0	85
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	72
T28	0	65
T30	0	72
T38	0	74
T39	0	1
T41	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7741
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	86
T9	608	0
T10	0	85
T13	5766	51
T14	490	0
T15	408	0
T16	19907	72
T28	0	65
T30	0	72
T38	0	74
T39	0	1
T41	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T13,T16,T8
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	7542	0	0
SrcPulseCheck_M	1194754601	7622	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	7542
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	80
T9	608	0
T10	0	61
T13	5766	51
T14	490	0
T15	408	0
T16	19907	89
T28	0	87
T30	0	76
T38	0	74
T41	0	51
T42	0	66

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7622
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	80
T9	256188	0
T10	0	61
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	89
T28	0	87
T30	0	76
T38	0	74
T41	0	51
T42	0	66

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T13,T16,T8
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7616	0	0
SrcPulseCheck_M	8477978	7616	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7616
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	80
T9	256188	0
T10	0	61
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	89
T28	0	87
T30	0	76
T38	0	74
T41	0	51
T42	0	66

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7616
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	80
T9	608	0
T10	0	61
T13	5766	51
T14	490	0
T15	408	0
T16	19907	89
T28	0	87
T30	0	76
T38	0	74
T41	0	51
T42	0	66

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T13,T16,T8
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	7721	0	0
SrcPulseCheck_M	1194754601	7800	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	7721
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	74
T9	608	0
T10	0	85
T13	5766	51
T14	490	0
T15	408	0
T16	19907	71
T28	0	70
T30	0	64
T38	0	51
T41	0	51
T42	0	71

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7800
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	74
T9	256188	0
T10	0	85
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	71
T28	0	70
T30	0	64
T38	0	51
T41	0	51
T42	0	72

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T13,T16,T8
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7792	0	0
SrcPulseCheck_M	8477978	7792	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7792
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	74
T9	256188	0
T10	0	85
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	71
T28	0	70
T30	0	64
T38	0	51
T41	0	51
T42	0	72

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7792
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	74
T9	608	0
T10	0	85
T13	5766	51
T14	490	0
T15	408	0
T16	19907	71
T28	0	70
T30	0	64
T38	0	51
T41	0	51
T42	0	72

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T13,T16,T8
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	7588	0	0
SrcPulseCheck_M	1194754601	7664	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	7588
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	58
T9	608	0
T10	0	72
T13	5766	51
T14	490	0
T15	408	0
T16	19907	94
T28	0	78
T30	0	78
T38	0	74
T41	0	51
T42	0	73

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	7664
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	58
T9	256188	0
T10	0	72
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	94
T28	0	78
T30	0	78
T38	0	74
T41	0	51
T42	0	73

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T13,T16,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T13,T16,T8
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	7657	0	0
SrcPulseCheck_M	8477978	7657	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	7657
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	58
T9	256188	0
T10	0	72
T13	279695	51
T14	242569	0
T15	198340	0
T16	238890	94
T28	0	78
T30	0	78
T38	0	74
T41	0	51
T42	0	73

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	7657
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	58
T9	608	0
T10	0	72
T13	5766	51
T14	490	0
T15	408	0
T16	19907	94
T28	0	78
T30	0	78
T38	0	74
T41	0	51
T42	0	73

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1792	0	0
SrcPulseCheck_M	1194754601	1868	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1792
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1868
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1861	0	0
SrcPulseCheck_M	8477978	1861	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1861
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1861
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1739	0	0
SrcPulseCheck_M	1194754601	1815	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1739
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1815
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1808	0	0
SrcPulseCheck_M	8477978	1808	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1808
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1808
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1712	0	0
SrcPulseCheck_M	1194754601	1789	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1712
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1789
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1782	0	0
SrcPulseCheck_M	8477978	1782	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1782
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1782
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1694	0	0
SrcPulseCheck_M	1194754601	1768	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1694
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1768
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1761	0	0
SrcPulseCheck_M	8477978	1761	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1761
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1761
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1768	0	0
SrcPulseCheck_M	1194754601	1846	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1768
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1846
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1839	0	0
SrcPulseCheck_M	8477978	1839	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1839
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1839
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T39	0	1
T41	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1703	0	0
SrcPulseCheck_M	1194754601	1784	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1703
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1784
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1776	0	0
SrcPulseCheck_M	8477978	1776	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1776
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1776
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1744	0	0
SrcPulseCheck_M	1194754601	1822	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1744
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1822
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1815	0	0
SrcPulseCheck_M	8477978	1815	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1815
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1815
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8477978	1693	0	0
SrcPulseCheck_M	1194754601	1770	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8477978	1693
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1194754601	1770
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T2,T13,T16
1	1	Covered	T78,T50,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T13,T16
1	0	Covered	T78,T50,T18
1	1	Covered	T2,T13,T16

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1194754601	1761	0	0
SrcPulseCheck_M	8477978	1761	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1194754601	1761
T2	164239	14
T3	97596	0
T6	753487	0
T7	147216	0
T8	113829	6
T9	256188	0
T10	0	5
T13	279695	1
T14	242569	0
T15	198340	0
T16	238890	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8477978	1761
T2	33179	14
T3	1059	0
T6	3067	0
T7	3625	0
T8	22766	6
T9	608	0
T10	0	5
T13	5766	1
T14	490	0
T15	408	0
T16	19907	7
T28	0	3
T30	0	6
T38	0	1
T41	0	1
T42	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc