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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 99.33 96.81 100.00 97.44 98.74 99.61 94.30


Total test records in report: 909
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T786 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3581309683 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:09 AM PDT 24 2021517927 ps
T304 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2951391378 Jul 02 07:48:50 AM PDT 24 Jul 02 07:48:59 AM PDT 24 2095057496 ps
T305 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1491017467 Jul 02 07:48:52 AM PDT 24 Jul 02 07:48:56 AM PDT 24 2031381887 ps
T787 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1183026306 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:13 AM PDT 24 2015250012 ps
T20 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3145311447 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:27 AM PDT 24 4782344132 ps
T306 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2511656234 Jul 02 07:48:56 AM PDT 24 Jul 02 07:50:38 AM PDT 24 39002610858 ps
T351 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.629667738 Jul 02 07:49:01 AM PDT 24 Jul 02 07:49:07 AM PDT 24 2045770700 ps
T327 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1509567361 Jul 02 07:49:02 AM PDT 24 Jul 02 07:49:08 AM PDT 24 2087947100 ps
T307 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.4245601819 Jul 02 07:50:15 AM PDT 24 Jul 02 07:50:20 AM PDT 24 2223363426 ps
T301 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2811339876 Jul 02 07:48:52 AM PDT 24 Jul 02 07:49:00 AM PDT 24 22449504886 ps
T788 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1058423773 Jul 02 07:50:11 AM PDT 24 Jul 02 07:50:16 AM PDT 24 2074748186 ps
T309 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.507769121 Jul 02 07:49:13 AM PDT 24 Jul 02 07:49:17 AM PDT 24 2118798866 ps
T356 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1116563258 Jul 02 07:48:47 AM PDT 24 Jul 02 07:49:04 AM PDT 24 6034508561 ps
T352 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2336775182 Jul 02 07:48:53 AM PDT 24 Jul 02 07:49:01 AM PDT 24 2033100317 ps
T789 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.373123459 Jul 02 07:49:02 AM PDT 24 Jul 02 07:49:06 AM PDT 24 2054884515 ps
T337 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.302906670 Jul 02 07:48:53 AM PDT 24 Jul 02 07:49:11 AM PDT 24 6048900278 ps
T338 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3855943004 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:02 AM PDT 24 2080461478 ps
T790 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3594652100 Jul 02 07:48:52 AM PDT 24 Jul 02 07:48:55 AM PDT 24 2020490826 ps
T339 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2522241408 Jul 02 07:48:47 AM PDT 24 Jul 02 07:50:32 AM PDT 24 39733835248 ps
T353 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3150846154 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:26 AM PDT 24 7224652842 ps
T340 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4215981044 Jul 02 07:48:52 AM PDT 24 Jul 02 07:48:55 AM PDT 24 4040767782 ps
T354 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3510724708 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:04 AM PDT 24 5461145727 ps
T308 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.916910138 Jul 02 07:50:02 AM PDT 24 Jul 02 07:50:11 AM PDT 24 2497230042 ps
T302 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3399677454 Jul 02 07:48:56 AM PDT 24 Jul 02 07:49:57 AM PDT 24 42394038728 ps
T791 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3387576072 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:06 AM PDT 24 2063698775 ps
T341 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3982127679 Jul 02 07:48:50 AM PDT 24 Jul 02 07:49:02 AM PDT 24 3011924052 ps
T355 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1421505932 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:05 AM PDT 24 2065732812 ps
T792 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.736296017 Jul 02 07:49:03 AM PDT 24 Jul 02 07:49:16 AM PDT 24 4562504937 ps
T793 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2102937375 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:25 AM PDT 24 2140188015 ps
T794 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1688588572 Jul 02 07:48:55 AM PDT 24 Jul 02 07:48:58 AM PDT 24 2072532772 ps
T310 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.976842672 Jul 02 07:48:47 AM PDT 24 Jul 02 07:48:54 AM PDT 24 2054929922 ps
T795 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2826467120 Jul 02 07:49:02 AM PDT 24 Jul 02 07:49:09 AM PDT 24 2014206124 ps
T796 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4044500739 Jul 02 07:50:23 AM PDT 24 Jul 02 07:50:28 AM PDT 24 2025521216 ps
T797 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.179489934 Jul 02 07:49:13 AM PDT 24 Jul 02 07:49:15 AM PDT 24 2043693994 ps
T798 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4245584922 Jul 02 07:49:01 AM PDT 24 Jul 02 07:49:05 AM PDT 24 2028468542 ps
T799 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.861522164 Jul 02 07:49:15 AM PDT 24 Jul 02 07:49:29 AM PDT 24 4872567804 ps
T800 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.684450333 Jul 02 07:48:54 AM PDT 24 Jul 02 07:48:57 AM PDT 24 2067293955 ps
T801 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2617638586 Jul 02 07:48:54 AM PDT 24 Jul 02 07:49:07 AM PDT 24 4015612561 ps
T802 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2091342177 Jul 02 07:48:54 AM PDT 24 Jul 02 07:49:00 AM PDT 24 2312379693 ps
T803 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1094070977 Jul 02 07:49:08 AM PDT 24 Jul 02 07:49:12 AM PDT 24 2020258593 ps
T804 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.396797936 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:08 AM PDT 24 2085687530 ps
T805 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1774614675 Jul 02 07:48:54 AM PDT 24 Jul 02 07:48:57 AM PDT 24 2034224455 ps
T806 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3476133931 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:04 AM PDT 24 2159135742 ps
T807 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.258654694 Jul 02 07:48:56 AM PDT 24 Jul 02 07:48:59 AM PDT 24 2038405929 ps
T808 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.641686534 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:07 AM PDT 24 2052717850 ps
T809 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3253244252 Jul 02 07:48:50 AM PDT 24 Jul 02 07:48:56 AM PDT 24 5157699939 ps
T810 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.627751058 Jul 02 07:48:49 AM PDT 24 Jul 02 07:48:54 AM PDT 24 2130049565 ps
T811 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2041763585 Jul 02 07:49:09 AM PDT 24 Jul 02 07:49:11 AM PDT 24 2096476012 ps
T812 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1170416258 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:25 AM PDT 24 2040512442 ps
T813 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1864032435 Jul 02 07:49:28 AM PDT 24 Jul 02 07:49:32 AM PDT 24 2034242373 ps
T814 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3188497642 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:07 AM PDT 24 2413594765 ps
T815 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2843327690 Jul 02 07:49:20 AM PDT 24 Jul 02 07:49:25 AM PDT 24 2019136966 ps
T342 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2960603799 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:23 AM PDT 24 16095210440 ps
T816 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.4097619283 Jul 02 07:50:23 AM PDT 24 Jul 02 07:50:30 AM PDT 24 2015291518 ps
T343 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.152401729 Jul 02 07:48:53 AM PDT 24 Jul 02 07:49:08 AM PDT 24 3088814986 ps
T382 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1517277609 Jul 02 07:48:56 AM PDT 24 Jul 02 07:49:13 AM PDT 24 22267312164 ps
T817 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1486413793 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:10 AM PDT 24 9306791749 ps
T818 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.316855805 Jul 02 07:49:24 AM PDT 24 Jul 02 07:49:27 AM PDT 24 2037304482 ps
T384 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3726160644 Jul 02 07:49:07 AM PDT 24 Jul 02 07:49:17 AM PDT 24 22357029651 ps
T819 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.719399537 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:53 AM PDT 24 22233821644 ps
T344 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1568454756 Jul 02 07:48:54 AM PDT 24 Jul 02 07:49:02 AM PDT 24 2048765293 ps
T820 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.767289970 Jul 02 07:49:01 AM PDT 24 Jul 02 07:49:06 AM PDT 24 2111724627 ps
T821 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1319678910 Jul 02 07:48:53 AM PDT 24 Jul 02 07:48:58 AM PDT 24 4466067502 ps
T822 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3798886959 Jul 02 07:49:01 AM PDT 24 Jul 02 07:49:07 AM PDT 24 2021317248 ps
T823 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1965251511 Jul 02 07:48:53 AM PDT 24 Jul 02 07:49:00 AM PDT 24 2079612159 ps
T345 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3099966025 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:27 AM PDT 24 2406721873 ps
T824 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1290851217 Jul 02 07:49:02 AM PDT 24 Jul 02 07:49:06 AM PDT 24 2029474475 ps
T825 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1922412837 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:07 AM PDT 24 2075516086 ps
T346 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3347915640 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:08 AM PDT 24 2054331865 ps
T826 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3548800365 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:03 AM PDT 24 2058546833 ps
T827 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.4113502295 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:03 AM PDT 24 2448290247 ps
T828 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1345340030 Jul 02 07:48:49 AM PDT 24 Jul 02 07:48:55 AM PDT 24 2683963745 ps
T829 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1387475205 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:08 AM PDT 24 4933154666 ps
T830 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2440611659 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:08 AM PDT 24 2029987036 ps
T831 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.28936351 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:52 AM PDT 24 42448552895 ps
T832 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4130246087 Jul 02 07:48:53 AM PDT 24 Jul 02 07:49:00 AM PDT 24 5168821812 ps
T347 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.153864091 Jul 02 07:49:07 AM PDT 24 Jul 02 07:49:14 AM PDT 24 2057914326 ps
T833 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3271721560 Jul 02 07:48:58 AM PDT 24 Jul 02 07:50:53 AM PDT 24 42384918395 ps
T834 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.660006364 Jul 02 07:48:53 AM PDT 24 Jul 02 07:49:01 AM PDT 24 2012133912 ps
T835 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.354398316 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:26 AM PDT 24 2016464133 ps
T348 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.4179170968 Jul 02 07:48:54 AM PDT 24 Jul 02 07:48:59 AM PDT 24 2082828343 ps
T836 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.271287408 Jul 02 07:48:50 AM PDT 24 Jul 02 07:49:04 AM PDT 24 3171905921 ps
T837 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2328401900 Jul 02 07:48:51 AM PDT 24 Jul 02 07:48:57 AM PDT 24 2069375504 ps
T838 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1627621483 Jul 02 07:50:09 AM PDT 24 Jul 02 07:50:17 AM PDT 24 2013079991 ps
T839 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3507390312 Jul 02 07:48:50 AM PDT 24 Jul 02 07:48:52 AM PDT 24 2233969612 ps
T840 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1421345853 Jul 02 07:48:56 AM PDT 24 Jul 02 07:49:03 AM PDT 24 2032387563 ps
T841 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1093068613 Jul 02 07:48:50 AM PDT 24 Jul 02 07:48:57 AM PDT 24 2046813224 ps
T842 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1773017889 Jul 02 07:48:48 AM PDT 24 Jul 02 07:48:51 AM PDT 24 2209737018 ps
T383 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2923551176 Jul 02 07:48:57 AM PDT 24 Jul 02 07:50:56 AM PDT 24 42472642444 ps
T843 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1954193670 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:07 AM PDT 24 7447354995 ps
T844 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2123445698 Jul 02 07:48:56 AM PDT 24 Jul 02 07:48:59 AM PDT 24 2035165134 ps
T845 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3388887020 Jul 02 07:48:50 AM PDT 24 Jul 02 07:49:02 AM PDT 24 9388558365 ps
T846 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2595264062 Jul 02 07:50:12 AM PDT 24 Jul 02 07:50:18 AM PDT 24 2018053990 ps
T847 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3036773534 Jul 02 07:48:50 AM PDT 24 Jul 02 07:49:08 AM PDT 24 22395055846 ps
T848 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1519538976 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:05 AM PDT 24 2013771777 ps
T849 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1361182542 Jul 02 07:48:54 AM PDT 24 Jul 02 07:49:09 AM PDT 24 2133237161 ps
T850 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.844092377 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:05 AM PDT 24 2142263699 ps
T851 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2640272509 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:30 AM PDT 24 42496082817 ps
T852 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4011883297 Jul 02 07:50:23 AM PDT 24 Jul 02 07:50:27 AM PDT 24 2033340976 ps
T853 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1302758133 Jul 02 07:48:53 AM PDT 24 Jul 02 07:48:59 AM PDT 24 6048548081 ps
T854 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.489724840 Jul 02 07:48:53 AM PDT 24 Jul 02 07:49:01 AM PDT 24 2055164056 ps
T855 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2099815348 Jul 02 07:49:00 AM PDT 24 Jul 02 07:49:04 AM PDT 24 2071532965 ps
T856 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2929329704 Jul 02 07:48:55 AM PDT 24 Jul 02 07:48:59 AM PDT 24 2023567326 ps
T857 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2145902119 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:07 AM PDT 24 2059846099 ps
T858 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.586653347 Jul 02 07:48:52 AM PDT 24 Jul 02 07:48:58 AM PDT 24 2079488188 ps
T859 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3461361023 Jul 02 07:48:51 AM PDT 24 Jul 02 07:48:53 AM PDT 24 2081178291 ps
T860 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3251768830 Jul 02 07:48:56 AM PDT 24 Jul 02 07:49:00 AM PDT 24 2027037244 ps
T861 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3790872406 Jul 02 07:49:06 AM PDT 24 Jul 02 07:49:13 AM PDT 24 2014442081 ps
T862 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1690481388 Jul 02 07:48:51 AM PDT 24 Jul 02 07:48:54 AM PDT 24 2074728803 ps
T863 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1319388143 Jul 02 07:48:51 AM PDT 24 Jul 02 07:50:44 AM PDT 24 42402276262 ps
T864 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3017443738 Jul 02 07:48:48 AM PDT 24 Jul 02 07:48:54 AM PDT 24 2009332405 ps
T385 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3627702842 Jul 02 07:49:12 AM PDT 24 Jul 02 07:49:42 AM PDT 24 42820892822 ps
T865 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1936447234 Jul 02 07:48:47 AM PDT 24 Jul 02 07:49:45 AM PDT 24 22239468538 ps
T866 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.331190648 Jul 02 07:49:01 AM PDT 24 Jul 02 07:49:07 AM PDT 24 2098614192 ps
T867 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.134432635 Jul 02 07:49:03 AM PDT 24 Jul 02 07:49:11 AM PDT 24 2044275215 ps
T868 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2129507439 Jul 02 07:49:08 AM PDT 24 Jul 02 07:49:15 AM PDT 24 2012988347 ps
T869 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3221435180 Jul 02 07:48:51 AM PDT 24 Jul 02 07:48:54 AM PDT 24 2116617012 ps
T870 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.364233173 Jul 02 07:48:59 AM PDT 24 Jul 02 07:49:58 AM PDT 24 22235192122 ps
T871 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4211114254 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:02 AM PDT 24 2056360318 ps
T872 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2272515638 Jul 02 07:50:10 AM PDT 24 Jul 02 07:50:15 AM PDT 24 2013852969 ps
T873 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3445009298 Jul 02 07:49:18 AM PDT 24 Jul 02 07:49:23 AM PDT 24 4535863745 ps
T874 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1778261907 Jul 02 07:48:51 AM PDT 24 Jul 02 07:48:53 AM PDT 24 2086851505 ps
T875 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2422282568 Jul 02 07:49:00 AM PDT 24 Jul 02 07:50:01 AM PDT 24 22252040609 ps
T876 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.4215934703 Jul 02 07:48:52 AM PDT 24 Jul 02 07:48:58 AM PDT 24 4860660344 ps
T877 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3006362340 Jul 02 07:49:15 AM PDT 24 Jul 02 07:49:18 AM PDT 24 2038773864 ps
T349 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.916787595 Jul 02 07:48:48 AM PDT 24 Jul 02 07:54:02 AM PDT 24 73635334047 ps
T878 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3737265953 Jul 02 07:48:48 AM PDT 24 Jul 02 07:49:03 AM PDT 24 22273406163 ps
T879 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2240098836 Jul 02 07:49:06 AM PDT 24 Jul 02 07:49:09 AM PDT 24 2042747180 ps
T880 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1899323815 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:26 AM PDT 24 2037781336 ps
T881 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4174670295 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:03 AM PDT 24 2110773126 ps
T882 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3843869065 Jul 02 07:49:20 AM PDT 24 Jul 02 07:49:26 AM PDT 24 2011072116 ps
T883 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.873788103 Jul 02 07:49:26 AM PDT 24 Jul 02 07:49:34 AM PDT 24 9780995952 ps
T350 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3292361008 Jul 02 07:48:48 AM PDT 24 Jul 02 07:48:58 AM PDT 24 3160178374 ps
T884 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.596131725 Jul 02 07:48:54 AM PDT 24 Jul 02 07:49:02 AM PDT 24 2066602103 ps
T885 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3151292244 Jul 02 07:49:21 AM PDT 24 Jul 02 07:49:29 AM PDT 24 2128744632 ps
T886 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2483809210 Jul 02 07:49:11 AM PDT 24 Jul 02 07:49:14 AM PDT 24 2096101351 ps
T887 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1431368101 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:09 AM PDT 24 2032265937 ps
T888 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3636809115 Jul 02 07:49:02 AM PDT 24 Jul 02 07:49:06 AM PDT 24 2061111467 ps
T889 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.960528687 Jul 02 07:49:14 AM PDT 24 Jul 02 07:49:18 AM PDT 24 2282415013 ps
T890 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2128876046 Jul 02 07:49:04 AM PDT 24 Jul 02 07:49:21 AM PDT 24 22638207080 ps
T891 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.940992223 Jul 02 07:48:51 AM PDT 24 Jul 02 07:49:08 AM PDT 24 4834588850 ps
T892 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2745844417 Jul 02 07:49:01 AM PDT 24 Jul 02 07:49:11 AM PDT 24 2107973152 ps
T893 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1264828024 Jul 02 07:48:59 AM PDT 24 Jul 02 07:49:06 AM PDT 24 2020318612 ps
T894 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2986721977 Jul 02 07:50:23 AM PDT 24 Jul 02 07:50:31 AM PDT 24 2012591208 ps
T895 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.672146625 Jul 02 07:49:02 AM PDT 24 Jul 02 07:49:12 AM PDT 24 2037489097 ps
T896 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2068916372 Jul 02 07:48:52 AM PDT 24 Jul 02 07:48:54 AM PDT 24 2063100124 ps
T897 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3264817209 Jul 02 07:49:15 AM PDT 24 Jul 02 07:49:21 AM PDT 24 2011947101 ps
T898 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1280709868 Jul 02 07:50:22 AM PDT 24 Jul 02 07:50:29 AM PDT 24 2009074344 ps
T899 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2622781265 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:37 AM PDT 24 8755972349 ps
T900 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.463611750 Jul 02 07:48:57 AM PDT 24 Jul 02 07:50:48 AM PDT 24 42434034158 ps
T901 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153628386 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:01 AM PDT 24 2098831606 ps
T902 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3667594903 Jul 02 07:50:09 AM PDT 24 Jul 02 07:50:14 AM PDT 24 2044139700 ps
T903 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.148751729 Jul 02 07:49:17 AM PDT 24 Jul 02 07:49:18 AM PDT 24 2101906348 ps
T904 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2991975822 Jul 02 07:48:58 AM PDT 24 Jul 02 07:49:08 AM PDT 24 2026685957 ps
T905 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.116636024 Jul 02 07:49:19 AM PDT 24 Jul 02 07:49:25 AM PDT 24 2008355457 ps
T906 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2706461904 Jul 02 07:48:57 AM PDT 24 Jul 02 07:49:12 AM PDT 24 5027663127 ps
T907 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3172801858 Jul 02 07:49:01 AM PDT 24 Jul 02 07:49:09 AM PDT 24 2011655349 ps
T908 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2116414879 Jul 02 07:48:51 AM PDT 24 Jul 02 07:50:33 AM PDT 24 42423780785 ps
T909 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2784633796 Jul 02 07:48:53 AM PDT 24 Jul 02 07:49:01 AM PDT 24 2046618980 ps

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.621876597
Short name T6
Test name
Test status
Simulation time 15335338677 ps
CPU time 20.02 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201408 kb
Host smart-fb8b96df-5370-4368-88b3-f2c2fd8f55c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621876597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_st
ress_all.621876597
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4060933595
Short name T8
Test name
Test status
Simulation time 113829720683 ps
CPU time 281.14 seconds
Started Jul 02 07:51:34 AM PDT 24
Finished Jul 02 07:56:20 AM PDT 24
Peak memory 201788 kb
Host smart-5e0d7373-8dc8-4b96-8489-57eabeebbdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060933595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.4060933595
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1019997973
Short name T21
Test name
Test status
Simulation time 1201425484373 ps
CPU time 72.12 seconds
Started Jul 02 07:51:22 AM PDT 24
Finished Jul 02 07:52:36 AM PDT 24
Peak memory 210136 kb
Host smart-cde67ae0-6d8d-4d40-9e22-67b2bc4a0eee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019997973 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1019997973
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2138443673
Short name T55
Test name
Test status
Simulation time 69069638650 ps
CPU time 38.68 seconds
Started Jul 02 07:50:18 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 214176 kb
Host smart-577076a0-e98a-4bb2-be5d-3b2e42ea839f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138443673 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.2138443673
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.1147973452
Short name T7
Test name
Test status
Simulation time 18126859647 ps
CPU time 41.03 seconds
Started Jul 02 07:50:20 AM PDT 24
Finished Jul 02 07:51:02 AM PDT 24
Peak memory 201588 kb
Host smart-692ae752-66eb-4e98-b7d9-9e6b12cffc24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147973452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.1147973452
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3444601827
Short name T78
Test name
Test status
Simulation time 33383948059 ps
CPU time 85.16 seconds
Started Jul 02 07:49:55 AM PDT 24
Finished Jul 02 07:51:29 AM PDT 24
Peak memory 201520 kb
Host smart-9db8606b-7bb6-49ed-aeac-11988062dae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444601827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3444601827
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.4281140297
Short name T71
Test name
Test status
Simulation time 55083883115 ps
CPU time 138.59 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:53:38 AM PDT 24
Peak memory 210200 kb
Host smart-143cb76f-54e0-4d46-a03a-7c81ed6d915c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281140297 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.4281140297
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.3940323729
Short name T98
Test name
Test status
Simulation time 523343840260 ps
CPU time 316.95 seconds
Started Jul 02 07:51:36 AM PDT 24
Finished Jul 02 07:56:58 AM PDT 24
Peak memory 201784 kb
Host smart-8d2f50af-b5a0-4faf-b4ad-9d72393cebc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940323729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.3940323729
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1645973837
Short name T26
Test name
Test status
Simulation time 42686207785 ps
CPU time 16.53 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:15 AM PDT 24
Peak memory 202068 kb
Host smart-2bf8e0de-f33d-4394-b6b7-dc468c8e2064
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645973837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.1645973837
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.848920190
Short name T30
Test name
Test status
Simulation time 96788638467 ps
CPU time 234.04 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:55:03 AM PDT 24
Peak memory 201840 kb
Host smart-31dfe922-b4af-44d0-b77a-bb3b61c3e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848920190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_wi
th_pre_cond.848920190
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2818751239
Short name T81
Test name
Test status
Simulation time 149200750702 ps
CPU time 60.76 seconds
Started Jul 02 07:51:32 AM PDT 24
Finished Jul 02 07:52:36 AM PDT 24
Peak memory 218416 kb
Host smart-8c7f38a7-3e4e-4f09-b967-6a3ab81b38fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818751239 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2818751239
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.40096440
Short name T91
Test name
Test status
Simulation time 51524408953 ps
CPU time 135.87 seconds
Started Jul 02 07:50:16 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 201768 kb
Host smart-d2686e2c-3950-469a-8dd3-469bb13976be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40096440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with
_pre_cond.40096440
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3831674797
Short name T135
Test name
Test status
Simulation time 69614930162 ps
CPU time 44.54 seconds
Started Jul 02 07:50:46 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 213608 kb
Host smart-f0c4a99c-2268-4730-b486-88e6efd65251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831674797 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3831674797
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1402498325
Short name T37
Test name
Test status
Simulation time 49839394430 ps
CPU time 132.3 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:52:58 AM PDT 24
Peak memory 210080 kb
Host smart-54748349-eb15-485d-9daa-cac038903475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402498325 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.1402498325
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2198528203
Short name T248
Test name
Test status
Simulation time 242810074890 ps
CPU time 636.55 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 08:02:28 AM PDT 24
Peak memory 201756 kb
Host smart-aee55220-e8f4-4c6f-95af-598c51ff2613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198528203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2198528203
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2456623354
Short name T256
Test name
Test status
Simulation time 22028643123 ps
CPU time 53.08 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:52 AM PDT 24
Peak memory 221036 kb
Host smart-7def719a-949b-46b7-aa01-6d842f03b5e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456623354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2456623354
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2683320673
Short name T145
Test name
Test status
Simulation time 1177198387318 ps
CPU time 32.47 seconds
Started Jul 02 07:50:33 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201604 kb
Host smart-8203baaf-6af0-4fe1-98ff-a6c0f0b49e19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683320673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.2683320673
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.2619727383
Short name T205
Test name
Test status
Simulation time 15348891311 ps
CPU time 37.08 seconds
Started Jul 02 07:50:58 AM PDT 24
Finished Jul 02 07:51:40 AM PDT 24
Peak memory 201488 kb
Host smart-3f07cec1-aec4-49f4-9a09-a337e8365a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619727383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.2619727383
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2678805551
Short name T115
Test name
Test status
Simulation time 186559744743 ps
CPU time 74.92 seconds
Started Jul 02 07:51:05 AM PDT 24
Finished Jul 02 07:52:23 AM PDT 24
Peak memory 201844 kb
Host smart-36b34274-e1ff-4b56-ba29-ccdacf52da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678805551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.2678805551
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.321372395
Short name T298
Test name
Test status
Simulation time 2309745671 ps
CPU time 4.95 seconds
Started Jul 02 07:50:24 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 202052 kb
Host smart-396d8af2-cc70-4269-bcdf-156b409d7129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321372395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors
.321372395
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.1229263042
Short name T181
Test name
Test status
Simulation time 4952206057 ps
CPU time 3.33 seconds
Started Jul 02 07:50:48 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 201576 kb
Host smart-d435750e-32f2-4e4a-a318-f9ddefc2a2b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229263042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.1229263042
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2471382189
Short name T31
Test name
Test status
Simulation time 83540832939 ps
CPU time 116.13 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:53:48 AM PDT 24
Peak memory 214404 kb
Host smart-6b13ef1d-5775-433d-9935-7caf6f5dcfbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471382189 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.2471382189
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3112029537
Short name T163
Test name
Test status
Simulation time 39056709424 ps
CPU time 43.2 seconds
Started Jul 02 07:50:32 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 210168 kb
Host smart-5223f1ce-dd84-43ff-9d78-705986231787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112029537 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3112029537
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1398392985
Short name T166
Test name
Test status
Simulation time 2774967693 ps
CPU time 6.59 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201560 kb
Host smart-103356c4-7163-4664-9e73-f1c56479c3df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398392985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.1398392985
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1794388948
Short name T257
Test name
Test status
Simulation time 3942843732 ps
CPU time 7.87 seconds
Started Jul 02 07:51:23 AM PDT 24
Finished Jul 02 07:51:33 AM PDT 24
Peak memory 201876 kb
Host smart-6b1124ef-6773-4b4c-844c-8a2c580dd1d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794388948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.1794388948
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2522241408
Short name T339
Test name
Test status
Simulation time 39733835248 ps
CPU time 104.56 seconds
Started Jul 02 07:48:47 AM PDT 24
Finished Jul 02 07:50:32 AM PDT 24
Peak memory 202176 kb
Host smart-4a7418d9-3298-49af-a27f-47b9c2adc1e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522241408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.2522241408
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3373438643
Short name T136
Test name
Test status
Simulation time 159946539276 ps
CPU time 98.17 seconds
Started Jul 02 07:50:47 AM PDT 24
Finished Jul 02 07:52:30 AM PDT 24
Peak memory 201748 kb
Host smart-738c7af3-9f7d-4f62-9f19-b881b5fb5431
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373438643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3373438643
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3269896291
Short name T398
Test name
Test status
Simulation time 2531632394 ps
CPU time 2.48 seconds
Started Jul 02 07:50:46 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 201596 kb
Host smart-fbf3f1ab-4454-4155-a012-6abf8b51efb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269896291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.3269896291
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2981994324
Short name T197
Test name
Test status
Simulation time 117953087189 ps
CPU time 68.1 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:52:11 AM PDT 24
Peak memory 210124 kb
Host smart-24d21964-564d-4b93-8ad5-9260578cd5a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981994324 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2981994324
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1631816748
Short name T19
Test name
Test status
Simulation time 5106089091 ps
CPU time 17.73 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:18 AM PDT 24
Peak memory 202112 kb
Host smart-b860264a-7a03-45dd-9ac3-c965abc02c34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631816748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.1631816748
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1210392682
Short name T50
Test name
Test status
Simulation time 39655366911 ps
CPU time 49.75 seconds
Started Jul 02 07:50:04 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 201532 kb
Host smart-3293e7fd-2bef-4d3a-a83b-55c4e24f0878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210392682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1210392682
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2734816290
Short name T359
Test name
Test status
Simulation time 183758662122 ps
CPU time 312.44 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:57:08 AM PDT 24
Peak memory 201864 kb
Host smart-5e417c0f-2fd3-43a3-a016-2f598a56e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734816290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.2734816290
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1399534083
Short name T313
Test name
Test status
Simulation time 2019988538 ps
CPU time 3.06 seconds
Started Jul 02 07:50:39 AM PDT 24
Finished Jul 02 07:50:44 AM PDT 24
Peak memory 201612 kb
Host smart-579695eb-34b6-421f-98df-ac3c2f14a5a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399534083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1399534083
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1064291811
Short name T73
Test name
Test status
Simulation time 8694837821 ps
CPU time 2.04 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 201576 kb
Host smart-93e2c2b3-711c-48e3-a873-7baaa7fbee40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064291811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.1064291811
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1013386611
Short name T397
Test name
Test status
Simulation time 193361085196 ps
CPU time 122.76 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:52:57 AM PDT 24
Peak memory 212100 kb
Host smart-1c9a9006-5be7-45c5-ab72-42b417ab313c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013386611 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.1013386611
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.949688532
Short name T386
Test name
Test status
Simulation time 83264600689 ps
CPU time 55.93 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:52:50 AM PDT 24
Peak memory 201736 kb
Host smart-6546e422-8f17-47ab-b41f-ae6b7ac36dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949688532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_wi
th_pre_cond.949688532
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3399677454
Short name T302
Test name
Test status
Simulation time 42394038728 ps
CPU time 60.51 seconds
Started Jul 02 07:48:56 AM PDT 24
Finished Jul 02 07:49:57 AM PDT 24
Peak memory 202468 kb
Host smart-035266f6-d75d-4a9f-95d3-76a66ed4cea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399677454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.3399677454
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.36889612
Short name T40
Test name
Test status
Simulation time 3537840557 ps
CPU time 9.84 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:57 AM PDT 24
Peak memory 201584 kb
Host smart-7c50c2af-8f56-431e-9090-983ab87b72c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36889612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.36889612
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2778196954
Short name T142
Test name
Test status
Simulation time 208525783900 ps
CPU time 47.89 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:52:00 AM PDT 24
Peak memory 210136 kb
Host smart-4249cbb0-5abd-42f0-942c-8346cb3fc248
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778196954 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2778196954
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.566983425
Short name T66
Test name
Test status
Simulation time 2577904968 ps
CPU time 1.47 seconds
Started Jul 02 07:51:12 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201500 kb
Host smart-ebde13bc-f658-4301-bf66-cdc9d06a74bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566983425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.566983425
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.121080288
Short name T51
Test name
Test status
Simulation time 87898296603 ps
CPU time 119.4 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:53:37 AM PDT 24
Peak memory 201940 kb
Host smart-68906485-fe5c-4932-93e1-87a8c2d208c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121080288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_wi
th_pre_cond.121080288
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1578219083
Short name T365
Test name
Test status
Simulation time 89529276232 ps
CPU time 33.8 seconds
Started Jul 02 07:52:06 AM PDT 24
Finished Jul 02 07:52:41 AM PDT 24
Peak memory 201912 kb
Host smart-65a1b57a-882c-442d-bc38-9c404994be0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578219083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.1578219083
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1083653214
Short name T29
Test name
Test status
Simulation time 115695321730 ps
CPU time 288.92 seconds
Started Jul 02 07:51:44 AM PDT 24
Finished Jul 02 07:56:35 AM PDT 24
Peak memory 201884 kb
Host smart-52e6bf70-9f00-48f7-be62-140ea5660bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083653214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1083653214
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.754255207
Short name T164
Test name
Test status
Simulation time 4569175096 ps
CPU time 2.13 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:03 AM PDT 24
Peak memory 201504 kb
Host smart-9d34633b-cd52-4689-aea4-457a450619fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754255207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctr
l_edge_detect.754255207
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1104751829
Short name T271
Test name
Test status
Simulation time 76194762076 ps
CPU time 22.49 seconds
Started Jul 02 07:50:37 AM PDT 24
Finished Jul 02 07:51:02 AM PDT 24
Peak memory 201812 kb
Host smart-234588a3-6754-4cc9-bd37-f900f6c5cb41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104751829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1104751829
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.670988212
Short name T370
Test name
Test status
Simulation time 80184543328 ps
CPU time 197.31 seconds
Started Jul 02 07:51:55 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 201760 kb
Host smart-88516eb3-ddfb-46c0-af3e-ba8953109140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670988212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_wi
th_pre_cond.670988212
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1022415879
Short name T212
Test name
Test status
Simulation time 144179584057 ps
CPU time 173.1 seconds
Started Jul 02 07:52:04 AM PDT 24
Finished Jul 02 07:54:58 AM PDT 24
Peak memory 201784 kb
Host smart-d7a01cea-fe95-43b7-a6e9-f8d41a270eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022415879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1022415879
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.627751058
Short name T810
Test name
Test status
Simulation time 2130049565 ps
CPU time 4.14 seconds
Started Jul 02 07:48:49 AM PDT 24
Finished Jul 02 07:48:54 AM PDT 24
Peak memory 201964 kb
Host smart-7b653731-0653-4006-9861-34afb3effe53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627751058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors
.627751058
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.302906670
Short name T337
Test name
Test status
Simulation time 6048900278 ps
CPU time 16.26 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:49:11 AM PDT 24
Peak memory 201904 kb
Host smart-047da151-c541-4161-8523-55a33209a850
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302906670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.302906670
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1955675752
Short name T134
Test name
Test status
Simulation time 112170159684 ps
CPU time 150.34 seconds
Started Jul 02 07:50:29 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 210488 kb
Host smart-094821ff-a70c-4f14-8d84-39dce63c1ae0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955675752 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1955675752
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.853416830
Short name T390
Test name
Test status
Simulation time 110442688544 ps
CPU time 278.14 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:55:25 AM PDT 24
Peak memory 201672 kb
Host smart-1ce75a95-3934-4490-bd41-d71221ce71c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853416830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_wi
th_pre_cond.853416830
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.893059267
Short name T357
Test name
Test status
Simulation time 112251269292 ps
CPU time 81.72 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:52:08 AM PDT 24
Peak memory 201796 kb
Host smart-b8f53a24-0a89-498e-8565-a38e0df9fefa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893059267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.893059267
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.3694544058
Short name T34
Test name
Test status
Simulation time 10354734465 ps
CPU time 25.81 seconds
Started Jul 02 07:50:46 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201580 kb
Host smart-5998aa47-c6f9-45de-a33c-fd2d93ba0cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694544058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.3694544058
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2732545924
Short name T367
Test name
Test status
Simulation time 64430576501 ps
CPU time 78.84 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:52:17 AM PDT 24
Peak memory 201892 kb
Host smart-08359bae-c9c1-4aa3-9467-21cc4f11cc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732545924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.2732545924
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.525095070
Short name T90
Test name
Test status
Simulation time 867378833072 ps
CPU time 100.58 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 210180 kb
Host smart-b008a4b5-334f-44d0-af19-841952036d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525095070 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.525095070
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1483176937
Short name T366
Test name
Test status
Simulation time 148087787582 ps
CPU time 85.39 seconds
Started Jul 02 07:50:01 AM PDT 24
Finished Jul 02 07:51:31 AM PDT 24
Peak memory 201724 kb
Host smart-03eb1e1b-e076-47cb-9546-f13683dd8e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483176937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1483176937
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.492380999
Short name T96
Test name
Test status
Simulation time 29343612123 ps
CPU time 38.24 seconds
Started Jul 02 07:51:30 AM PDT 24
Finished Jul 02 07:52:12 AM PDT 24
Peak memory 201896 kb
Host smart-50dcf27a-3541-4bb7-a857-c82aa6af32a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492380999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.492380999
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3350516556
Short name T99
Test name
Test status
Simulation time 171777394158 ps
CPU time 455.93 seconds
Started Jul 02 07:51:43 AM PDT 24
Finished Jul 02 07:59:22 AM PDT 24
Peak memory 201792 kb
Host smart-14cac1da-812b-4bd7-94a9-f81f983fa034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350516556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3350516556
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.375997430
Short name T368
Test name
Test status
Simulation time 88515137107 ps
CPU time 220.8 seconds
Started Jul 02 07:51:58 AM PDT 24
Finished Jul 02 07:55:41 AM PDT 24
Peak memory 201704 kb
Host smart-18874450-353a-4310-a510-dfb0aadb8689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375997430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_wi
th_pre_cond.375997430
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.745902205
Short name T378
Test name
Test status
Simulation time 93129437503 ps
CPU time 59.59 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:55 AM PDT 24
Peak memory 201760 kb
Host smart-949914bd-1757-4044-8412-ac8b9ef990ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745902205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_wi
th_pre_cond.745902205
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3970119023
Short name T375
Test name
Test status
Simulation time 55493569701 ps
CPU time 13.59 seconds
Started Jul 02 07:51:55 AM PDT 24
Finished Jul 02 07:52:12 AM PDT 24
Peak memory 201864 kb
Host smart-ac1d9142-d269-4d9e-a776-166b3d8d7648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970119023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.3970119023
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.152401729
Short name T343
Test name
Test status
Simulation time 3088814986 ps
CPU time 14.53 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 202120 kb
Host smart-0cd0048a-e5b6-4140-98f5-7629ee039411
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152401729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_aliasing.152401729
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1116563258
Short name T356
Test name
Test status
Simulation time 6034508561 ps
CPU time 16.21 seconds
Started Jul 02 07:48:47 AM PDT 24
Finished Jul 02 07:49:04 AM PDT 24
Peak memory 201912 kb
Host smart-13e0d916-9830-430d-b239-e9eea5d48df1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116563258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.1116563258
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1773017889
Short name T842
Test name
Test status
Simulation time 2209737018 ps
CPU time 2.48 seconds
Started Jul 02 07:48:48 AM PDT 24
Finished Jul 02 07:48:51 AM PDT 24
Peak memory 201900 kb
Host smart-9c0ecbd4-6ca9-40cf-9e9f-dcf374eb99a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773017889 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1773017889
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1491017467
Short name T305
Test name
Test status
Simulation time 2031381887 ps
CPU time 3.11 seconds
Started Jul 02 07:48:52 AM PDT 24
Finished Jul 02 07:48:56 AM PDT 24
Peak memory 201640 kb
Host smart-2fab4303-9031-42d9-b9ed-a2f6e9698f8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491017467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1491017467
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2929329704
Short name T856
Test name
Test status
Simulation time 2023567326 ps
CPU time 2.86 seconds
Started Jul 02 07:48:55 AM PDT 24
Finished Jul 02 07:48:59 AM PDT 24
Peak memory 201680 kb
Host smart-4ba445e1-4e7a-4b1a-8f2b-7081fd43d3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929329704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.2929329704
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1319678910
Short name T821
Test name
Test status
Simulation time 4466067502 ps
CPU time 3.6 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:48:58 AM PDT 24
Peak memory 201872 kb
Host smart-24504a3d-22c9-458f-aa8d-76c07f44b3a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319678910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.1319678910
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.976842672
Short name T310
Test name
Test status
Simulation time 2054929922 ps
CPU time 6.41 seconds
Started Jul 02 07:48:47 AM PDT 24
Finished Jul 02 07:48:54 AM PDT 24
Peak memory 201932 kb
Host smart-ad8ff08f-2a6a-452d-8f3a-11e8bfa4be27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976842672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors
.976842672
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1936447234
Short name T865
Test name
Test status
Simulation time 22239468538 ps
CPU time 57.54 seconds
Started Jul 02 07:48:47 AM PDT 24
Finished Jul 02 07:49:45 AM PDT 24
Peak memory 202120 kb
Host smart-26171733-25a3-4dd4-83d8-e0b132d02287
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936447234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.1936447234
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1345340030
Short name T828
Test name
Test status
Simulation time 2683963745 ps
CPU time 5.67 seconds
Started Jul 02 07:48:49 AM PDT 24
Finished Jul 02 07:48:55 AM PDT 24
Peak memory 202096 kb
Host smart-76d2a252-a1fc-41bc-9536-12f521426184
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345340030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.1345340030
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.916787595
Short name T349
Test name
Test status
Simulation time 73635334047 ps
CPU time 312.8 seconds
Started Jul 02 07:48:48 AM PDT 24
Finished Jul 02 07:54:02 AM PDT 24
Peak memory 201992 kb
Host smart-928c7132-69de-43a2-9ae8-dcd7a5561275
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916787595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.916787595
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1302758133
Short name T853
Test name
Test status
Simulation time 6048548081 ps
CPU time 3.83 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:48:59 AM PDT 24
Peak memory 201904 kb
Host smart-0ce8548b-e958-4513-b083-f5bac03dfeae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302758133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.1302758133
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3221435180
Short name T869
Test name
Test status
Simulation time 2116617012 ps
CPU time 2.28 seconds
Started Jul 02 07:48:51 AM PDT 24
Finished Jul 02 07:48:54 AM PDT 24
Peak memory 201788 kb
Host smart-116f75df-8a11-46ab-97b3-6a0743a16995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221435180 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3221435180
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2784633796
Short name T909
Test name
Test status
Simulation time 2046618980 ps
CPU time 5.99 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:49:01 AM PDT 24
Peak memory 201692 kb
Host smart-846f7853-56a3-4016-b075-7d2763b60917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784633796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2784633796
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3017443738
Short name T864
Test name
Test status
Simulation time 2009332405 ps
CPU time 5.81 seconds
Started Jul 02 07:48:48 AM PDT 24
Finished Jul 02 07:48:54 AM PDT 24
Peak memory 201644 kb
Host smart-93a7bdf1-5414-463a-bee3-01e037e482b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017443738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.3017443738
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3253244252
Short name T809
Test name
Test status
Simulation time 5157699939 ps
CPU time 5.03 seconds
Started Jul 02 07:48:50 AM PDT 24
Finished Jul 02 07:48:56 AM PDT 24
Peak memory 202036 kb
Host smart-991e5b15-250d-4e8a-9f87-217538d81d7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253244252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.3253244252
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2116414879
Short name T908
Test name
Test status
Simulation time 42423780785 ps
CPU time 101.05 seconds
Started Jul 02 07:48:51 AM PDT 24
Finished Jul 02 07:50:33 AM PDT 24
Peak memory 202120 kb
Host smart-8f7e4ba4-9521-4ee3-ad3c-fd16a9adad71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116414879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.2116414879
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153628386
Short name T901
Test name
Test status
Simulation time 2098831606 ps
CPU time 2.15 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:01 AM PDT 24
Peak memory 201720 kb
Host smart-62170e34-4d90-4b25-9351-139641a493de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153628386 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3153628386
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.153864091
Short name T347
Test name
Test status
Simulation time 2057914326 ps
CPU time 6.44 seconds
Started Jul 02 07:49:07 AM PDT 24
Finished Jul 02 07:49:14 AM PDT 24
Peak memory 200968 kb
Host smart-0a512f7b-33c7-4981-90f8-493f7cc551c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153864091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_r
w.153864091
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2123445698
Short name T844
Test name
Test status
Simulation time 2035165134 ps
CPU time 1.65 seconds
Started Jul 02 07:48:56 AM PDT 24
Finished Jul 02 07:48:59 AM PDT 24
Peak memory 201972 kb
Host smart-822230b3-7cbb-4d1d-bd08-86b0b2967dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123445698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.2123445698
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1387475205
Short name T829
Test name
Test status
Simulation time 4933154666 ps
CPU time 7.23 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 202080 kb
Host smart-5f1b6529-697e-4ebe-8c3a-7fd7a40ab2fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387475205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.1387475205
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.672146625
Short name T895
Test name
Test status
Simulation time 2037489097 ps
CPU time 7.18 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:49:12 AM PDT 24
Peak memory 201960 kb
Host smart-12181d39-ca64-47e5-a83c-be4a5a2e2641
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672146625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.672146625
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2483809210
Short name T886
Test name
Test status
Simulation time 2096101351 ps
CPU time 2.65 seconds
Started Jul 02 07:49:11 AM PDT 24
Finished Jul 02 07:49:14 AM PDT 24
Peak memory 201836 kb
Host smart-17a7d8db-186f-4112-99da-bb8425bd0130
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483809210 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2483809210
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1688588572
Short name T794
Test name
Test status
Simulation time 2072532772 ps
CPU time 1.83 seconds
Started Jul 02 07:48:55 AM PDT 24
Finished Jul 02 07:48:58 AM PDT 24
Peak memory 201736 kb
Host smart-40b7b2cc-3603-4e33-80c2-8eafda21582a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688588572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.1688588572
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1183026306
Short name T787
Test name
Test status
Simulation time 2015250012 ps
CPU time 5.54 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:13 AM PDT 24
Peak memory 201516 kb
Host smart-e2f48e26-080c-49e1-977d-30481bc62f4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183026306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.1183026306
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1954193670
Short name T843
Test name
Test status
Simulation time 7447354995 ps
CPU time 6.06 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 202120 kb
Host smart-8d5a02f6-5581-444a-add9-172d5e4dfd36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954193670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.1954193670
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2745844417
Short name T892
Test name
Test status
Simulation time 2107973152 ps
CPU time 7.05 seconds
Started Jul 02 07:49:01 AM PDT 24
Finished Jul 02 07:49:11 AM PDT 24
Peak memory 201960 kb
Host smart-1cd34874-b675-4515-89b3-8bc3d86288fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745844417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2745844417
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2422282568
Short name T875
Test name
Test status
Simulation time 22252040609 ps
CPU time 55.14 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:50:01 AM PDT 24
Peak memory 202064 kb
Host smart-300a1aa4-4c7b-44d0-8bfb-06a1a6d57c02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422282568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.2422282568
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.396797936
Short name T804
Test name
Test status
Simulation time 2085687530 ps
CPU time 6.62 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 202016 kb
Host smart-810a5f38-035b-401e-a99c-e93b52af0545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396797936 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.396797936
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.629667738
Short name T351
Test name
Test status
Simulation time 2045770700 ps
CPU time 3.33 seconds
Started Jul 02 07:49:01 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 201760 kb
Host smart-c8ec49f2-b89b-4b45-be42-9f1180d38459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629667738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r
w.629667738
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3790872406
Short name T861
Test name
Test status
Simulation time 2014442081 ps
CPU time 6.01 seconds
Started Jul 02 07:49:06 AM PDT 24
Finished Jul 02 07:49:13 AM PDT 24
Peak memory 201604 kb
Host smart-c905d7d8-9c80-4af5-92a0-7ec73a4bad05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790872406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.3790872406
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3151292244
Short name T885
Test name
Test status
Simulation time 2128744632 ps
CPU time 7.28 seconds
Started Jul 02 07:49:21 AM PDT 24
Finished Jul 02 07:49:29 AM PDT 24
Peak memory 202144 kb
Host smart-a02b9539-f76a-4d22-81d3-63061f62ce89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151292244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.3151292244
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2640272509
Short name T851
Test name
Test status
Simulation time 42496082817 ps
CPU time 29.77 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:30 AM PDT 24
Peak memory 202140 kb
Host smart-9ea4ec0a-78e0-4d2a-bba4-6219c86343c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640272509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.2640272509
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.960528687
Short name T889
Test name
Test status
Simulation time 2282415013 ps
CPU time 2.43 seconds
Started Jul 02 07:49:14 AM PDT 24
Finished Jul 02 07:49:18 AM PDT 24
Peak memory 201944 kb
Host smart-d09bac17-ed43-476f-b492-8fbcc3186f33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960528687 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.960528687
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.134432635
Short name T867
Test name
Test status
Simulation time 2044275215 ps
CPU time 5.64 seconds
Started Jul 02 07:49:03 AM PDT 24
Finished Jul 02 07:49:11 AM PDT 24
Peak memory 201692 kb
Host smart-e958f2a2-3ce3-4d5f-a744-64f3cd01c218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134432635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_r
w.134432635
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3548800365
Short name T826
Test name
Test status
Simulation time 2058546833 ps
CPU time 1.34 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:03 AM PDT 24
Peak memory 201480 kb
Host smart-9cf07dbe-dff8-4277-b17e-ffd6c33e8299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548800365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.3548800365
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3445009298
Short name T873
Test name
Test status
Simulation time 4535863745 ps
CPU time 3.97 seconds
Started Jul 02 07:49:18 AM PDT 24
Finished Jul 02 07:49:23 AM PDT 24
Peak memory 202032 kb
Host smart-13e5dbc3-5346-40ef-86ba-64baef82eacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445009298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.3445009298
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.916910138
Short name T308
Test name
Test status
Simulation time 2497230042 ps
CPU time 4.2 seconds
Started Jul 02 07:50:02 AM PDT 24
Finished Jul 02 07:50:11 AM PDT 24
Peak memory 201220 kb
Host smart-10cd72cb-3396-465b-a46a-21cc6a75e4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916910138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.916910138
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2128876046
Short name T890
Test name
Test status
Simulation time 22638207080 ps
CPU time 15.07 seconds
Started Jul 02 07:49:04 AM PDT 24
Finished Jul 02 07:49:21 AM PDT 24
Peak memory 202068 kb
Host smart-87649715-e952-4b6a-8ce1-fad17ea80489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128876046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.2128876046
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.489724840
Short name T854
Test name
Test status
Simulation time 2055164056 ps
CPU time 6.24 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:49:01 AM PDT 24
Peak memory 201832 kb
Host smart-05dbc248-80e1-4270-b9a2-ddcd081ca5c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489724840 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.489724840
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1421345853
Short name T840
Test name
Test status
Simulation time 2032387563 ps
CPU time 6.01 seconds
Started Jul 02 07:48:56 AM PDT 24
Finished Jul 02 07:49:03 AM PDT 24
Peak memory 201832 kb
Host smart-86a1d54f-e7c4-46be-93cc-dc302601a8e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421345853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.1421345853
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1094070977
Short name T803
Test name
Test status
Simulation time 2020258593 ps
CPU time 3.44 seconds
Started Jul 02 07:49:08 AM PDT 24
Finished Jul 02 07:49:12 AM PDT 24
Peak memory 201600 kb
Host smart-c3a05695-afea-4969-801e-23eb174a4873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094070977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1094070977
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3510724708
Short name T354
Test name
Test status
Simulation time 5461145727 ps
CPU time 2.42 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:04 AM PDT 24
Peak memory 202032 kb
Host smart-e2adbbd6-d2a0-4536-a018-55ed6319e11d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510724708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.3510724708
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1431368101
Short name T887
Test name
Test status
Simulation time 2032265937 ps
CPU time 7.08 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:09 AM PDT 24
Peak memory 201996 kb
Host smart-cd004a2d-6f14-497d-8997-3a14b7c7dcb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431368101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.1431368101
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.719399537
Short name T819
Test name
Test status
Simulation time 22233821644 ps
CPU time 53.75 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:53 AM PDT 24
Peak memory 202024 kb
Host smart-10b73a84-a2c0-4008-a4b7-d4fbc798435f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719399537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_tl_intg_err.719399537
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4174670295
Short name T881
Test name
Test status
Simulation time 2110773126 ps
CPU time 2.29 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:03 AM PDT 24
Peak memory 201844 kb
Host smart-335574d0-a435-4e05-b646-9cbbdace8b15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174670295 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4174670295
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1421505932
Short name T355
Test name
Test status
Simulation time 2065732812 ps
CPU time 2.12 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:05 AM PDT 24
Peak memory 201776 kb
Host smart-35a2709e-4986-4d3b-bc5b-5afb9fc22c19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421505932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1421505932
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2843327690
Short name T815
Test name
Test status
Simulation time 2019136966 ps
CPU time 3.12 seconds
Started Jul 02 07:49:20 AM PDT 24
Finished Jul 02 07:49:25 AM PDT 24
Peak memory 201512 kb
Host smart-f5bc6325-468c-42ee-a4ce-12c436a7a610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843327690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.2843327690
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.736296017
Short name T792
Test name
Test status
Simulation time 4562504937 ps
CPU time 11.11 seconds
Started Jul 02 07:49:03 AM PDT 24
Finished Jul 02 07:49:16 AM PDT 24
Peak memory 202236 kb
Host smart-50c9814c-eacd-49d7-a72f-169197f55e4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736296017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.sysrst_ctrl_same_csr_outstanding.736296017
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3188497642
Short name T814
Test name
Test status
Simulation time 2413594765 ps
CPU time 3.96 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 218056 kb
Host smart-e3b38789-3e83-4ce2-a120-20ce6ee6b894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188497642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3188497642
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.463611750
Short name T900
Test name
Test status
Simulation time 42434034158 ps
CPU time 107.88 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:50:48 AM PDT 24
Peak memory 202144 kb
Host smart-1a75b9a3-0b2e-43d7-b71a-a2886adce895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463611750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_tl_intg_err.463611750
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.641686534
Short name T808
Test name
Test status
Simulation time 2052717850 ps
CPU time 6.15 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 201720 kb
Host smart-36406ce5-26ef-48ad-9e70-aff87462aa0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641686534 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.641686534
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3855943004
Short name T338
Test name
Test status
Simulation time 2080461478 ps
CPU time 2.01 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:02 AM PDT 24
Peak memory 201680 kb
Host smart-bafaa90f-4281-4f9b-accb-35aa25fdc682
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855943004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3855943004
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1519538976
Short name T848
Test name
Test status
Simulation time 2013771777 ps
CPU time 5.39 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:05 AM PDT 24
Peak memory 201548 kb
Host smart-37ef6198-5b52-4dbf-a988-2c45b1ea0e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519538976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.1519538976
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.258209785
Short name T18
Test name
Test status
Simulation time 7598631676 ps
CPU time 28.3 seconds
Started Jul 02 07:49:12 AM PDT 24
Finished Jul 02 07:49:41 AM PDT 24
Peak memory 202084 kb
Host smart-5c407d9b-575d-4ae0-88ad-29aa30918015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258209785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.sysrst_ctrl_same_csr_outstanding.258209785
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1922412837
Short name T825
Test name
Test status
Simulation time 2075516086 ps
CPU time 6.8 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 201892 kb
Host smart-26f7ae7e-64ea-4948-96ef-b3e25a7abce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922412837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1922412837
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.767289970
Short name T820
Test name
Test status
Simulation time 2111724627 ps
CPU time 2.1 seconds
Started Jul 02 07:49:01 AM PDT 24
Finished Jul 02 07:49:06 AM PDT 24
Peak memory 201832 kb
Host smart-05488f59-5a8e-45cc-8408-509ab069b9d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767289970 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.767289970
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4211114254
Short name T871
Test name
Test status
Simulation time 2056360318 ps
CPU time 2.21 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:02 AM PDT 24
Peak memory 201792 kb
Host smart-4681a986-7eb8-4825-9e3b-87cbaa8ad1a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211114254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.4211114254
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1864032435
Short name T813
Test name
Test status
Simulation time 2034242373 ps
CPU time 1.86 seconds
Started Jul 02 07:49:28 AM PDT 24
Finished Jul 02 07:49:32 AM PDT 24
Peak memory 201584 kb
Host smart-b6a7c5f6-1d8c-4386-b2bd-ca4f145b913f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864032435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.1864032435
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.861522164
Short name T799
Test name
Test status
Simulation time 4872567804 ps
CPU time 13.14 seconds
Started Jul 02 07:49:15 AM PDT 24
Finished Jul 02 07:49:29 AM PDT 24
Peak memory 202100 kb
Host smart-21d20b13-37e3-4838-904e-1ad751d6861b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861522164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.861522164
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.507769121
Short name T309
Test name
Test status
Simulation time 2118798866 ps
CPU time 3.05 seconds
Started Jul 02 07:49:13 AM PDT 24
Finished Jul 02 07:49:17 AM PDT 24
Peak memory 202000 kb
Host smart-6b52dfb7-8b23-405d-a616-aa05a3b4e480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507769121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_error
s.507769121
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.28936351
Short name T831
Test name
Test status
Simulation time 42448552895 ps
CPU time 48.97 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:52 AM PDT 24
Peak memory 202028 kb
Host smart-b90b078d-8baa-49ec-a10d-61c525e3b8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28936351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_tl_intg_err.28936351
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1509567361
Short name T327
Test name
Test status
Simulation time 2087947100 ps
CPU time 3.54 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 201712 kb
Host smart-f15aaab9-7611-4adf-ac90-c797ab7c2d97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509567361 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1509567361
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3636809115
Short name T888
Test name
Test status
Simulation time 2061111467 ps
CPU time 2.1 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:49:06 AM PDT 24
Peak memory 201792 kb
Host smart-86a4c0c0-37f2-49cb-9ace-a264832bbb85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636809115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.3636809115
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1264828024
Short name T893
Test name
Test status
Simulation time 2020318612 ps
CPU time 3.22 seconds
Started Jul 02 07:48:59 AM PDT 24
Finished Jul 02 07:49:06 AM PDT 24
Peak memory 201632 kb
Host smart-790890a9-9e77-4ca7-a0c7-20f5d8a6a831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264828024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.1264828024
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.873788103
Short name T883
Test name
Test status
Simulation time 9780995952 ps
CPU time 7.78 seconds
Started Jul 02 07:49:26 AM PDT 24
Finished Jul 02 07:49:34 AM PDT 24
Peak memory 202156 kb
Host smart-97fd2fb5-827a-4d12-b028-4ec87d7bf479
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873788103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.sysrst_ctrl_same_csr_outstanding.873788103
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.4245601819
Short name T307
Test name
Test status
Simulation time 2223363426 ps
CPU time 4.59 seconds
Started Jul 02 07:50:15 AM PDT 24
Finished Jul 02 07:50:20 AM PDT 24
Peak memory 202072 kb
Host smart-5197df19-2d4c-45b8-a5b8-bcaa2bb49681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245601819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.4245601819
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3627702842
Short name T385
Test name
Test status
Simulation time 42820892822 ps
CPU time 29.5 seconds
Started Jul 02 07:49:12 AM PDT 24
Finished Jul 02 07:49:42 AM PDT 24
Peak memory 202140 kb
Host smart-4abfc2e7-495b-4640-bec1-e3da607b0f09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627702842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.3627702842
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1058423773
Short name T788
Test name
Test status
Simulation time 2074748186 ps
CPU time 3.36 seconds
Started Jul 02 07:50:11 AM PDT 24
Finished Jul 02 07:50:16 AM PDT 24
Peak memory 201732 kb
Host smart-dbbce1af-4ab2-46b6-be3c-5acf3a9ebd92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058423773 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1058423773
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2440611659
Short name T830
Test name
Test status
Simulation time 2029987036 ps
CPU time 5.82 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 201664 kb
Host smart-4a890286-cb8f-4b0e-8beb-33a7b388c76b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440611659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2440611659
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3006362340
Short name T877
Test name
Test status
Simulation time 2038773864 ps
CPU time 1.95 seconds
Started Jul 02 07:49:15 AM PDT 24
Finished Jul 02 07:49:18 AM PDT 24
Peak memory 201580 kb
Host smart-dec6bfa8-dd34-4751-b878-7464f1ddf6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006362340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.3006362340
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3145311447
Short name T20
Test name
Test status
Simulation time 4782344132 ps
CPU time 3.33 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 201876 kb
Host smart-eac9c2f2-f1d0-4013-9322-07b0ee3ac552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145311447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.3145311447
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3799146921
Short name T299
Test name
Test status
Simulation time 2173719024 ps
CPU time 6.74 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 202104 kb
Host smart-31676451-3ae9-435e-bbc0-6219c17caa30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799146921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3799146921
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2923551176
Short name T383
Test name
Test status
Simulation time 42472642444 ps
CPU time 116.86 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:50:56 AM PDT 24
Peak memory 202020 kb
Host smart-767d827f-dce2-456f-a9cf-18147b32227b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923551176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2923551176
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3292361008
Short name T350
Test name
Test status
Simulation time 3160178374 ps
CPU time 9.11 seconds
Started Jul 02 07:48:48 AM PDT 24
Finished Jul 02 07:48:58 AM PDT 24
Peak memory 202092 kb
Host smart-0266b5fd-2faa-4f9c-984a-4690ee9de2e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292361008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3292361008
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3982127679
Short name T341
Test name
Test status
Simulation time 3011924052 ps
CPU time 11.56 seconds
Started Jul 02 07:48:50 AM PDT 24
Finished Jul 02 07:49:02 AM PDT 24
Peak memory 202124 kb
Host smart-979469df-3125-4a01-90b4-be08de8b1bda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982127679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.3982127679
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2617638586
Short name T801
Test name
Test status
Simulation time 4015612561 ps
CPU time 10.59 seconds
Started Jul 02 07:48:54 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 201896 kb
Host smart-e287a0da-2cf6-4380-a04c-12ef2f4f5452
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617638586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.2617638586
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1965251511
Short name T823
Test name
Test status
Simulation time 2079612159 ps
CPU time 5.88 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:49:00 AM PDT 24
Peak memory 201748 kb
Host smart-9cc655fa-51b7-49ac-8d1e-9bd3204ce91a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965251511 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1965251511
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1568454756
Short name T344
Test name
Test status
Simulation time 2048765293 ps
CPU time 5.88 seconds
Started Jul 02 07:48:54 AM PDT 24
Finished Jul 02 07:49:02 AM PDT 24
Peak memory 201788 kb
Host smart-9b02ad11-3223-47a3-b3b9-aacb949d7baa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568454756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.1568454756
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3251768830
Short name T860
Test name
Test status
Simulation time 2027037244 ps
CPU time 2 seconds
Started Jul 02 07:48:56 AM PDT 24
Finished Jul 02 07:49:00 AM PDT 24
Peak memory 201544 kb
Host smart-fff06e38-3df1-4cd1-92d9-746f3004315e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251768830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.3251768830
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4130246087
Short name T832
Test name
Test status
Simulation time 5168821812 ps
CPU time 5.11 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:49:00 AM PDT 24
Peak memory 202104 kb
Host smart-4be2410a-e699-4082-9a0d-3204ab3d9c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130246087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.4130246087
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2091342177
Short name T802
Test name
Test status
Simulation time 2312379693 ps
CPU time 5.11 seconds
Started Jul 02 07:48:54 AM PDT 24
Finished Jul 02 07:49:00 AM PDT 24
Peak memory 210856 kb
Host smart-6ce84e56-5819-4abc-ade8-e29a585bc7b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091342177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.2091342177
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1319388143
Short name T863
Test name
Test status
Simulation time 42402276262 ps
CPU time 111.53 seconds
Started Jul 02 07:48:51 AM PDT 24
Finished Jul 02 07:50:44 AM PDT 24
Peak memory 202080 kb
Host smart-9fed047b-5fd6-4469-b9cd-c95fbc35e8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319388143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1319388143
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.148751729
Short name T903
Test name
Test status
Simulation time 2101906348 ps
CPU time 1.09 seconds
Started Jul 02 07:49:17 AM PDT 24
Finished Jul 02 07:49:18 AM PDT 24
Peak memory 201484 kb
Host smart-cec8fecc-a384-4c7d-8f39-5e275c34b7ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148751729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_tes
t.148751729
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.4245584922
Short name T798
Test name
Test status
Simulation time 2028468542 ps
CPU time 1.95 seconds
Started Jul 02 07:49:01 AM PDT 24
Finished Jul 02 07:49:05 AM PDT 24
Peak memory 201572 kb
Host smart-7160a5dd-2451-4338-ab0f-84b6e6022012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245584922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.4245584922
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3172801858
Short name T907
Test name
Test status
Simulation time 2011655349 ps
CPU time 5.3 seconds
Started Jul 02 07:49:01 AM PDT 24
Finished Jul 02 07:49:09 AM PDT 24
Peak memory 201612 kb
Host smart-676ab3a5-0b9e-4105-b45d-350592890f8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172801858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.3172801858
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.316855805
Short name T818
Test name
Test status
Simulation time 2037304482 ps
CPU time 1.85 seconds
Started Jul 02 07:49:24 AM PDT 24
Finished Jul 02 07:49:27 AM PDT 24
Peak memory 201496 kb
Host smart-34971ec9-a340-4b17-a903-44af4b42f7fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316855805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_tes
t.316855805
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2041763585
Short name T811
Test name
Test status
Simulation time 2096476012 ps
CPU time 1.04 seconds
Started Jul 02 07:49:09 AM PDT 24
Finished Jul 02 07:49:11 AM PDT 24
Peak memory 201612 kb
Host smart-a70f50b6-c99c-42e0-b1e3-847a68b7b7f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041763585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.2041763585
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3581309683
Short name T786
Test name
Test status
Simulation time 2021517927 ps
CPU time 2.9 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:09 AM PDT 24
Peak memory 201708 kb
Host smart-f9cc689f-f836-4dfd-9b2e-46f7ae036692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581309683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.3581309683
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.4097619283
Short name T816
Test name
Test status
Simulation time 2015291518 ps
CPU time 5.69 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 201492 kb
Host smart-5011e1ac-31b4-4794-8081-2c7c44af2181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097619283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.4097619283
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2826467120
Short name T795
Test name
Test status
Simulation time 2014206124 ps
CPU time 4.56 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:49:09 AM PDT 24
Peak memory 201564 kb
Host smart-52571098-4e4b-4b13-9dc3-41265603e4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826467120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.2826467120
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3843869065
Short name T882
Test name
Test status
Simulation time 2011072116 ps
CPU time 5.18 seconds
Started Jul 02 07:49:20 AM PDT 24
Finished Jul 02 07:49:26 AM PDT 24
Peak memory 201584 kb
Host smart-276fd67f-3d07-43aa-b916-e262ee84eaa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843869065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.3843869065
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4044500739
Short name T796
Test name
Test status
Simulation time 2025521216 ps
CPU time 3.05 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 201384 kb
Host smart-50458d0c-3ffa-4655-97ea-939fc95b44cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044500739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.4044500739
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.271287408
Short name T836
Test name
Test status
Simulation time 3171905921 ps
CPU time 12.6 seconds
Started Jul 02 07:48:50 AM PDT 24
Finished Jul 02 07:49:04 AM PDT 24
Peak memory 201792 kb
Host smart-fe4df906-7b01-493f-9c6f-69be05d8e6b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271287408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.271287408
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2511656234
Short name T306
Test name
Test status
Simulation time 39002610858 ps
CPU time 100.42 seconds
Started Jul 02 07:48:56 AM PDT 24
Finished Jul 02 07:50:38 AM PDT 24
Peak memory 202052 kb
Host smart-80ddd948-653d-4238-9e83-d6fb1041c952
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511656234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.2511656234
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4215981044
Short name T340
Test name
Test status
Simulation time 4040767782 ps
CPU time 3 seconds
Started Jul 02 07:48:52 AM PDT 24
Finished Jul 02 07:48:55 AM PDT 24
Peak memory 201812 kb
Host smart-4fbe90b4-d991-4fbd-b3ae-a2bf2887cc58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215981044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.4215981044
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3507390312
Short name T839
Test name
Test status
Simulation time 2233969612 ps
CPU time 1.37 seconds
Started Jul 02 07:48:50 AM PDT 24
Finished Jul 02 07:48:52 AM PDT 24
Peak memory 201820 kb
Host smart-b067b44a-1288-4f79-97c8-818cd8d1d5a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507390312 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3507390312
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1690481388
Short name T862
Test name
Test status
Simulation time 2074728803 ps
CPU time 2.16 seconds
Started Jul 02 07:48:51 AM PDT 24
Finished Jul 02 07:48:54 AM PDT 24
Peak memory 201636 kb
Host smart-105e2693-0086-426f-8db5-9ac51b5cd9b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690481388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.1690481388
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.684450333
Short name T800
Test name
Test status
Simulation time 2067293955 ps
CPU time 1.11 seconds
Started Jul 02 07:48:54 AM PDT 24
Finished Jul 02 07:48:57 AM PDT 24
Peak memory 201656 kb
Host smart-3554c93e-07d8-4172-b47e-d06336c8d814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684450333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test
.684450333
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3388887020
Short name T845
Test name
Test status
Simulation time 9388558365 ps
CPU time 11.94 seconds
Started Jul 02 07:48:50 AM PDT 24
Finished Jul 02 07:49:02 AM PDT 24
Peak memory 202052 kb
Host smart-4be67e61-a244-4601-9e6a-0b4214f9cfcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388887020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.3388887020
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1361182542
Short name T849
Test name
Test status
Simulation time 2133237161 ps
CPU time 7.57 seconds
Started Jul 02 07:48:54 AM PDT 24
Finished Jul 02 07:49:09 AM PDT 24
Peak memory 217644 kb
Host smart-79f6eaec-eb6b-4e1c-971c-825275a3ebe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361182542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.1361182542
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3271721560
Short name T833
Test name
Test status
Simulation time 42384918395 ps
CPU time 111.8 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 201780 kb
Host smart-b2d76e14-f0cc-447a-a888-5456517ac604
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271721560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3271721560
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3798886959
Short name T822
Test name
Test status
Simulation time 2021317248 ps
CPU time 3.17 seconds
Started Jul 02 07:49:01 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 201572 kb
Host smart-443db479-1111-4729-80fb-d09af8292ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798886959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3798886959
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2595264062
Short name T846
Test name
Test status
Simulation time 2018053990 ps
CPU time 4.15 seconds
Started Jul 02 07:50:12 AM PDT 24
Finished Jul 02 07:50:18 AM PDT 24
Peak memory 201540 kb
Host smart-e71a83e8-4ac8-4a93-abbe-26e83983a6dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595264062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2595264062
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.354398316
Short name T835
Test name
Test status
Simulation time 2016464133 ps
CPU time 2.84 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 201536 kb
Host smart-d5d8f095-1677-4883-bbcf-25668a4e006f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354398316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_tes
t.354398316
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2099815348
Short name T855
Test name
Test status
Simulation time 2071532965 ps
CPU time 1.2 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:04 AM PDT 24
Peak memory 201668 kb
Host smart-b31b5d2f-9445-438b-ab00-70e7538319c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099815348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2099815348
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2272515638
Short name T872
Test name
Test status
Simulation time 2013852969 ps
CPU time 3 seconds
Started Jul 02 07:50:10 AM PDT 24
Finished Jul 02 07:50:15 AM PDT 24
Peak memory 201532 kb
Host smart-37cd778e-e884-4353-9335-54b32e3ea590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272515638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.2272515638
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1290851217
Short name T824
Test name
Test status
Simulation time 2029474475 ps
CPU time 1.97 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:49:06 AM PDT 24
Peak memory 201676 kb
Host smart-cf0141d3-4286-4f16-a510-8d18e36811bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290851217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.1290851217
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1170416258
Short name T812
Test name
Test status
Simulation time 2040512442 ps
CPU time 1.86 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:25 AM PDT 24
Peak memory 201528 kb
Host smart-add2cd2e-c417-4045-945b-7e5050e1e598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170416258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.1170416258
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.373123459
Short name T789
Test name
Test status
Simulation time 2054884515 ps
CPU time 1.21 seconds
Started Jul 02 07:49:02 AM PDT 24
Finished Jul 02 07:49:06 AM PDT 24
Peak memory 201672 kb
Host smart-5c9aa593-6210-4f55-9ee7-76a0f6a1671c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373123459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_tes
t.373123459
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2102937375
Short name T793
Test name
Test status
Simulation time 2140188015 ps
CPU time 1.16 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:25 AM PDT 24
Peak memory 201548 kb
Host smart-4fc27032-21a4-4a3b-bfb9-a45ef302340b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102937375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.2102937375
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2129507439
Short name T868
Test name
Test status
Simulation time 2012988347 ps
CPU time 5.84 seconds
Started Jul 02 07:49:08 AM PDT 24
Finished Jul 02 07:49:15 AM PDT 24
Peak memory 201624 kb
Host smart-9cb97fc4-bc30-4abd-b7bd-f73985075071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129507439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.2129507439
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3099966025
Short name T345
Test name
Test status
Simulation time 2406721873 ps
CPU time 2.66 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 202104 kb
Host smart-eaf463e5-04fe-42d1-b9ff-1a998d36141b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099966025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.3099966025
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2960603799
Short name T342
Test name
Test status
Simulation time 16095210440 ps
CPU time 20.54 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:23 AM PDT 24
Peak memory 201960 kb
Host smart-05ae4db7-bc33-45b1-a0b9-11e17463350f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960603799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2960603799
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3476133931
Short name T806
Test name
Test status
Simulation time 2159135742 ps
CPU time 3.78 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:04 AM PDT 24
Peak memory 201888 kb
Host smart-1fd92c2d-95a5-4fc8-a9a0-6cc7d40270f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476133931 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3476133931
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3461361023
Short name T859
Test name
Test status
Simulation time 2081178291 ps
CPU time 2.12 seconds
Started Jul 02 07:48:51 AM PDT 24
Finished Jul 02 07:48:53 AM PDT 24
Peak memory 201712 kb
Host smart-c568364b-acf4-496f-9c94-5cea37725a05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461361023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3461361023
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1778261907
Short name T874
Test name
Test status
Simulation time 2086851505 ps
CPU time 1.07 seconds
Started Jul 02 07:48:51 AM PDT 24
Finished Jul 02 07:48:53 AM PDT 24
Peak memory 201528 kb
Host smart-b467f64b-4443-430f-b148-ca9e87ee6807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778261907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.1778261907
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.4215934703
Short name T876
Test name
Test status
Simulation time 4860660344 ps
CPU time 4.86 seconds
Started Jul 02 07:48:52 AM PDT 24
Finished Jul 02 07:48:58 AM PDT 24
Peak memory 202120 kb
Host smart-78933dd0-c05c-43c4-ab24-fe9774a0ada1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215934703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.4215934703
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2951391378
Short name T304
Test name
Test status
Simulation time 2095057496 ps
CPU time 7.39 seconds
Started Jul 02 07:48:50 AM PDT 24
Finished Jul 02 07:48:59 AM PDT 24
Peak memory 201960 kb
Host smart-e7902289-5809-4bcf-bbbe-459d491ac76a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951391378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.2951391378
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1517277609
Short name T382
Test name
Test status
Simulation time 22267312164 ps
CPU time 16.29 seconds
Started Jul 02 07:48:56 AM PDT 24
Finished Jul 02 07:49:13 AM PDT 24
Peak memory 202120 kb
Host smart-43294102-9915-4d3e-a06a-d88b86ee9130
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517277609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.1517277609
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1627621483
Short name T838
Test name
Test status
Simulation time 2013079991 ps
CPU time 5.96 seconds
Started Jul 02 07:50:09 AM PDT 24
Finished Jul 02 07:50:17 AM PDT 24
Peak memory 200092 kb
Host smart-5803716d-435c-480e-827d-72e1ce0a83bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627621483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1627621483
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3264817209
Short name T897
Test name
Test status
Simulation time 2011947101 ps
CPU time 5.39 seconds
Started Jul 02 07:49:15 AM PDT 24
Finished Jul 02 07:49:21 AM PDT 24
Peak memory 201604 kb
Host smart-654a7790-672c-4eb8-917f-f4b34a005b83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264817209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3264817209
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1899323815
Short name T880
Test name
Test status
Simulation time 2037781336 ps
CPU time 1.95 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 201616 kb
Host smart-776a06ac-4f2e-4670-8f74-019fe8881b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899323815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1899323815
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.179489934
Short name T797
Test name
Test status
Simulation time 2043693994 ps
CPU time 1.83 seconds
Started Jul 02 07:49:13 AM PDT 24
Finished Jul 02 07:49:15 AM PDT 24
Peak memory 201568 kb
Host smart-71bc7f5c-87b0-4c9e-85c6-13e170fc0408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179489934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.179489934
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2986721977
Short name T894
Test name
Test status
Simulation time 2012591208 ps
CPU time 5.6 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:31 AM PDT 24
Peak memory 201296 kb
Host smart-5e237fbe-a2c2-4d88-a146-635a77a39840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986721977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2986721977
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3055184698
Short name T785
Test name
Test status
Simulation time 2024123920 ps
CPU time 2.75 seconds
Started Jul 02 07:49:18 AM PDT 24
Finished Jul 02 07:49:22 AM PDT 24
Peak memory 201584 kb
Host smart-c7f26773-3704-40e5-bb3f-fceae5d65c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055184698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.3055184698
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4011883297
Short name T852
Test name
Test status
Simulation time 2033340976 ps
CPU time 1.87 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 201412 kb
Host smart-d5a6ac04-d72a-4252-b1f2-751c6e6066e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011883297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.4011883297
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3667594903
Short name T902
Test name
Test status
Simulation time 2044139700 ps
CPU time 2 seconds
Started Jul 02 07:50:09 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 200208 kb
Host smart-b58cd58b-e47d-4d2d-a3c0-aa0c985cd0e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667594903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3667594903
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1280709868
Short name T898
Test name
Test status
Simulation time 2009074344 ps
CPU time 5.58 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:29 AM PDT 24
Peak memory 201616 kb
Host smart-404a9b34-b8bd-4b3d-b445-c09cdb7e26a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280709868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.1280709868
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2240098836
Short name T879
Test name
Test status
Simulation time 2042747180 ps
CPU time 1.91 seconds
Started Jul 02 07:49:06 AM PDT 24
Finished Jul 02 07:49:09 AM PDT 24
Peak memory 201568 kb
Host smart-e503ddb1-bc5f-4bf2-942c-de39ada1faf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240098836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.2240098836
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2328401900
Short name T837
Test name
Test status
Simulation time 2069375504 ps
CPU time 5.97 seconds
Started Jul 02 07:48:51 AM PDT 24
Finished Jul 02 07:48:57 AM PDT 24
Peak memory 201516 kb
Host smart-67f32ae5-7cc2-4363-a72b-11f9231a6983
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328401900 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2328401900
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2336775182
Short name T352
Test name
Test status
Simulation time 2033100317 ps
CPU time 5.88 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:49:01 AM PDT 24
Peak memory 201656 kb
Host smart-5acfc080-3bdb-4974-9896-dc45513eae24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336775182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.2336775182
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.258654694
Short name T807
Test name
Test status
Simulation time 2038405929 ps
CPU time 1.88 seconds
Started Jul 02 07:48:56 AM PDT 24
Finished Jul 02 07:48:59 AM PDT 24
Peak memory 201504 kb
Host smart-d40f762d-ab2a-42e9-a19b-44dc34ce9d55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258654694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.258654694
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2706461904
Short name T906
Test name
Test status
Simulation time 5027663127 ps
CPU time 12.17 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:12 AM PDT 24
Peak memory 202052 kb
Host smart-8fef45fa-e82e-4667-997e-84fd73381458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706461904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.2706461904
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1093068613
Short name T841
Test name
Test status
Simulation time 2046813224 ps
CPU time 6.08 seconds
Started Jul 02 07:48:50 AM PDT 24
Finished Jul 02 07:48:57 AM PDT 24
Peak memory 201912 kb
Host smart-fc13b5c8-d332-499d-938c-23fad4220000
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093068613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.1093068613
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2811339876
Short name T301
Test name
Test status
Simulation time 22449504886 ps
CPU time 7 seconds
Started Jul 02 07:48:52 AM PDT 24
Finished Jul 02 07:49:00 AM PDT 24
Peak memory 202128 kb
Host smart-cb96abd7-1ee3-47fd-b354-b8f35f41c35e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811339876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.2811339876
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3387576072
Short name T791
Test name
Test status
Simulation time 2063698775 ps
CPU time 5.77 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:06 AM PDT 24
Peak memory 201744 kb
Host smart-c6746d56-55cb-4f8c-b983-f6876234ba88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387576072 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3387576072
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2145902119
Short name T857
Test name
Test status
Simulation time 2059846099 ps
CPU time 6.53 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 201828 kb
Host smart-b9cba9be-fd04-44b3-9dc7-a5790a29c786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145902119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.2145902119
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1774614675
Short name T805
Test name
Test status
Simulation time 2034224455 ps
CPU time 1.67 seconds
Started Jul 02 07:48:54 AM PDT 24
Finished Jul 02 07:48:57 AM PDT 24
Peak memory 200148 kb
Host smart-6414358c-9f9e-4de4-b766-e7f6e2b7dec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774614675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.1774614675
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2622781265
Short name T899
Test name
Test status
Simulation time 8755972349 ps
CPU time 36.19 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:37 AM PDT 24
Peak memory 202056 kb
Host smart-1d7a996f-95ff-44dd-9cc5-f8d0d89c2095
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622781265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.2622781265
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.4113502295
Short name T827
Test name
Test status
Simulation time 2448290247 ps
CPU time 2.93 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:03 AM PDT 24
Peak memory 202140 kb
Host smart-88ed03a8-6b24-47e7-a61d-67a507d32fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113502295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.4113502295
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3726160644
Short name T384
Test name
Test status
Simulation time 22357029651 ps
CPU time 9.75 seconds
Started Jul 02 07:49:07 AM PDT 24
Finished Jul 02 07:49:17 AM PDT 24
Peak memory 202120 kb
Host smart-f1277239-70c7-4526-87e2-28bce4edc1e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726160644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3726160644
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.844092377
Short name T850
Test name
Test status
Simulation time 2142263699 ps
CPU time 2.62 seconds
Started Jul 02 07:49:00 AM PDT 24
Finished Jul 02 07:49:05 AM PDT 24
Peak memory 201780 kb
Host smart-b869e239-2118-4bcb-a35e-6b56168a974c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844092377 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.844092377
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.4179170968
Short name T348
Test name
Test status
Simulation time 2082828343 ps
CPU time 3.5 seconds
Started Jul 02 07:48:54 AM PDT 24
Finished Jul 02 07:48:59 AM PDT 24
Peak memory 201796 kb
Host smart-4c8cffa9-4c9d-4967-838e-c865835fd716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179170968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.4179170968
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.660006364
Short name T834
Test name
Test status
Simulation time 2012133912 ps
CPU time 5.63 seconds
Started Jul 02 07:48:53 AM PDT 24
Finished Jul 02 07:49:01 AM PDT 24
Peak memory 201680 kb
Host smart-acbdc7f1-8e01-4d31-bcda-221208feeb47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660006364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test
.660006364
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3150846154
Short name T353
Test name
Test status
Simulation time 7224652842 ps
CPU time 25.34 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:26 AM PDT 24
Peak memory 202136 kb
Host smart-01179892-41f0-43a3-91ae-a22b9f4eb34a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150846154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.3150846154
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3737265953
Short name T878
Test name
Test status
Simulation time 22273406163 ps
CPU time 14.3 seconds
Started Jul 02 07:48:48 AM PDT 24
Finished Jul 02 07:49:03 AM PDT 24
Peak memory 202052 kb
Host smart-ac6970f3-16d4-4f8d-9d52-93c49b787c52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737265953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.3737265953
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.586653347
Short name T858
Test name
Test status
Simulation time 2079488188 ps
CPU time 5.75 seconds
Started Jul 02 07:48:52 AM PDT 24
Finished Jul 02 07:48:58 AM PDT 24
Peak memory 201780 kb
Host smart-d2595eef-8b92-4bfa-9b84-fdfef796767f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586653347 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.586653347
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2068916372
Short name T896
Test name
Test status
Simulation time 2063100124 ps
CPU time 1.95 seconds
Started Jul 02 07:48:52 AM PDT 24
Finished Jul 02 07:48:54 AM PDT 24
Peak memory 201744 kb
Host smart-5a3287cd-7d67-4460-9922-ee5ee6e21ad7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068916372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.2068916372
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3594652100
Short name T790
Test name
Test status
Simulation time 2020490826 ps
CPU time 1.94 seconds
Started Jul 02 07:48:52 AM PDT 24
Finished Jul 02 07:48:55 AM PDT 24
Peak memory 201536 kb
Host smart-2fe5637e-b97d-4e2a-bded-d0a2b5caf40d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594652100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.3594652100
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.940992223
Short name T891
Test name
Test status
Simulation time 4834588850 ps
CPU time 16.36 seconds
Started Jul 02 07:48:51 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 202072 kb
Host smart-942b5e22-9e44-4e63-b22f-07581fcd0a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940992223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
sysrst_ctrl_same_csr_outstanding.940992223
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.596131725
Short name T884
Test name
Test status
Simulation time 2066602103 ps
CPU time 6.1 seconds
Started Jul 02 07:48:54 AM PDT 24
Finished Jul 02 07:49:02 AM PDT 24
Peak memory 200648 kb
Host smart-3e67960d-2c43-44bf-a1b8-5c1bcb8619c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596131725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors
.596131725
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3036773534
Short name T847
Test name
Test status
Simulation time 22395055846 ps
CPU time 16.38 seconds
Started Jul 02 07:48:50 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 202088 kb
Host smart-035f7509-5107-4cdd-80dc-c90f33c8b1cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036773534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.3036773534
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.331190648
Short name T866
Test name
Test status
Simulation time 2098614192 ps
CPU time 3.57 seconds
Started Jul 02 07:49:01 AM PDT 24
Finished Jul 02 07:49:07 AM PDT 24
Peak memory 201812 kb
Host smart-122f0f36-dd9c-4244-8303-805a54c10853
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331190648 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.331190648
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3347915640
Short name T346
Test name
Test status
Simulation time 2054331865 ps
CPU time 6.49 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 201780 kb
Host smart-39013f84-4170-40e8-bacb-9a0ea55f0976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347915640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.3347915640
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.116636024
Short name T905
Test name
Test status
Simulation time 2008355457 ps
CPU time 5.72 seconds
Started Jul 02 07:49:19 AM PDT 24
Finished Jul 02 07:49:25 AM PDT 24
Peak memory 201660 kb
Host smart-7e756756-e73a-49c0-82da-b898746bffa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116636024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test
.116636024
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1486413793
Short name T817
Test name
Test status
Simulation time 9306791749 ps
CPU time 12.09 seconds
Started Jul 02 07:48:57 AM PDT 24
Finished Jul 02 07:49:10 AM PDT 24
Peak memory 202116 kb
Host smart-750b9de9-1297-43d7-874e-bf18164281e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486413793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.1486413793
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2991975822
Short name T904
Test name
Test status
Simulation time 2026685957 ps
CPU time 6.81 seconds
Started Jul 02 07:48:58 AM PDT 24
Finished Jul 02 07:49:08 AM PDT 24
Peak memory 201980 kb
Host smart-b8069708-09a9-410f-811e-b904841c3235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991975822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.2991975822
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.364233173
Short name T870
Test name
Test status
Simulation time 22235192122 ps
CPU time 56.24 seconds
Started Jul 02 07:48:59 AM PDT 24
Finished Jul 02 07:49:58 AM PDT 24
Peak memory 202088 kb
Host smart-1235daef-47be-45c3-a3b3-c82251e44d21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364233173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_tl_intg_err.364233173
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.352611577
Short name T712
Test name
Test status
Simulation time 2010473905 ps
CPU time 5.76 seconds
Started Jul 02 07:49:52 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201876 kb
Host smart-11b4f82d-36a3-4be9-88ab-26ee8de4ea79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352611577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.352611577
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1944396609
Short name T516
Test name
Test status
Simulation time 3381101909 ps
CPU time 2.66 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:50:02 AM PDT 24
Peak memory 201624 kb
Host smart-425d9114-d576-4a9d-a779-d6da5762ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944396609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1944396609
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.1058423442
Short name T718
Test name
Test status
Simulation time 48752943648 ps
CPU time 129.75 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:52:13 AM PDT 24
Peak memory 201688 kb
Host smart-81e1de7f-2d67-4b17-be61-5c93af21f00a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058423442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.1058423442
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2752414436
Short name T275
Test name
Test status
Simulation time 2182877104 ps
CPU time 1.84 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:49:59 AM PDT 24
Peak memory 201560 kb
Host smart-6a8a1181-e698-4a7b-adf7-3753d64ba9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752414436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2752414436
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3655277463
Short name T39
Test name
Test status
Simulation time 2319004900 ps
CPU time 1.71 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:50:00 AM PDT 24
Peak memory 201508 kb
Host smart-8801d561-7d50-4749-a84c-9425036cd3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655277463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3655277463
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2910437352
Short name T767
Test name
Test status
Simulation time 66858887293 ps
CPU time 173.37 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 200816 kb
Host smart-3bc80ffd-8c0d-48e8-91ce-b06e61b5e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910437352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.2910437352
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.3865908714
Short name T610
Test name
Test status
Simulation time 3116534331 ps
CPU time 7.12 seconds
Started Jul 02 07:50:05 AM PDT 24
Finished Jul 02 07:50:15 AM PDT 24
Peak memory 201500 kb
Host smart-a6a6eeba-40d6-4c99-b73c-73e04e86cd79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865908714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.3865908714
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.116431042
Short name T223
Test name
Test status
Simulation time 2590107242 ps
CPU time 7.34 seconds
Started Jul 02 07:50:05 AM PDT 24
Finished Jul 02 07:50:16 AM PDT 24
Peak memory 201448 kb
Host smart-f69bcd94-6e5e-4023-92cb-27d833cfb4fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116431042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_edge_detect.116431042
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1635305036
Short name T509
Test name
Test status
Simulation time 2609895524 ps
CPU time 7 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:04 AM PDT 24
Peak memory 201508 kb
Host smart-58c0433a-e2db-41ad-9d21-7f6b10a816d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635305036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1635305036
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1302038881
Short name T14
Test name
Test status
Simulation time 2450212971 ps
CPU time 6.51 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:06 AM PDT 24
Peak memory 201532 kb
Host smart-ee05a209-fb4b-4706-b62b-7c1504b5e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302038881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1302038881
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.2582356804
Short name T469
Test name
Test status
Simulation time 2079528298 ps
CPU time 5.41 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:06 AM PDT 24
Peak memory 201388 kb
Host smart-32b629a7-cda2-4618-b56e-dd6c40a10050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582356804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.2582356804
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2823225633
Short name T583
Test name
Test status
Simulation time 2510916996 ps
CPU time 6.54 seconds
Started Jul 02 07:50:00 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201532 kb
Host smart-36d30ad5-ebbe-40f9-924b-4581bed6d013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823225633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2823225633
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3167000073
Short name T315
Test name
Test status
Simulation time 42026442137 ps
CPU time 51.97 seconds
Started Jul 02 07:49:48 AM PDT 24
Finished Jul 02 07:50:51 AM PDT 24
Peak memory 220608 kb
Host smart-e4299bd6-c5fd-47db-82c3-0c682a8e1339
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167000073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3167000073
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2688464106
Short name T117
Test name
Test status
Simulation time 2126416687 ps
CPU time 1.91 seconds
Started Jul 02 07:49:53 AM PDT 24
Finished Jul 02 07:50:04 AM PDT 24
Peak memory 201528 kb
Host smart-9d2a8c98-b333-4915-8950-b87acc85d9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688464106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2688464106
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.3563831097
Short name T526
Test name
Test status
Simulation time 15868733198 ps
CPU time 9.31 seconds
Started Jul 02 07:49:50 AM PDT 24
Finished Jul 02 07:50:10 AM PDT 24
Peak memory 201488 kb
Host smart-34225543-f09f-45e0-a249-d837ff27e623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563831097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.3563831097
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3752765535
Short name T160
Test name
Test status
Simulation time 19432480629 ps
CPU time 12.43 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:10 AM PDT 24
Peak memory 209872 kb
Host smart-0567d427-9cb3-4c9a-a441-162b29551b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752765535 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.3752765535
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2472603893
Short name T72
Test name
Test status
Simulation time 35899341579 ps
CPU time 7.79 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 200420 kb
Host smart-5b99cf8a-8fc7-46a6-965e-ed19f9b4d067
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472603893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.2472603893
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.2433812365
Short name T732
Test name
Test status
Simulation time 2013945029 ps
CPU time 5.47 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:50:09 AM PDT 24
Peak memory 201524 kb
Host smart-c871d2ae-26f7-4fe3-a558-7ac8b5b15506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433812365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.2433812365
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.184192662
Short name T569
Test name
Test status
Simulation time 3381635603 ps
CPU time 8.97 seconds
Started Jul 02 07:49:51 AM PDT 24
Finished Jul 02 07:50:10 AM PDT 24
Peak memory 201564 kb
Host smart-c856c1e7-9ece-4e46-986a-65b79c3662da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184192662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.184192662
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3995784351
Short name T291
Test name
Test status
Simulation time 74798047297 ps
CPU time 96.26 seconds
Started Jul 02 07:50:08 AM PDT 24
Finished Jul 02 07:51:46 AM PDT 24
Peak memory 201768 kb
Host smart-fe2bdfad-f456-4c5d-9ab1-c133e9ee1949
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995784351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.3995784351
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2048742300
Short name T534
Test name
Test status
Simulation time 2385403041 ps
CPU time 0.98 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:50:04 AM PDT 24
Peak memory 201596 kb
Host smart-d8184101-f09e-42b6-a108-449cebfc4e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048742300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2048742300
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2428724288
Short name T617
Test name
Test status
Simulation time 2511564870 ps
CPU time 7.4 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201560 kb
Host smart-7ca00422-04d0-49dd-976e-0720dabd9f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428724288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2428724288
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1481623479
Short name T392
Test name
Test status
Simulation time 67090592934 ps
CPU time 41.82 seconds
Started Jul 02 07:50:01 AM PDT 24
Finished Jul 02 07:50:48 AM PDT 24
Peak memory 201868 kb
Host smart-32809282-4c2d-4e6e-b7b4-7557576d8004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481623479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.1481623479
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3778870175
Short name T692
Test name
Test status
Simulation time 4769344046 ps
CPU time 13.14 seconds
Started Jul 02 07:49:53 AM PDT 24
Finished Jul 02 07:50:16 AM PDT 24
Peak memory 201564 kb
Host smart-5abb4a2b-1e71-48f4-ad38-e602b639f619
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778870175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3778870175
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.2652843683
Short name T168
Test name
Test status
Simulation time 5337043475 ps
CPU time 12.07 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201544 kb
Host smart-bdaf0ef3-bb28-4f71-a263-0e4da2ab3509
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652843683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.2652843683
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2235650868
Short name T437
Test name
Test status
Simulation time 2625234785 ps
CPU time 2.48 seconds
Started Jul 02 07:49:51 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201528 kb
Host smart-16db89af-c82d-445a-8d40-95a6b3e1b885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235650868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2235650868
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3756969543
Short name T433
Test name
Test status
Simulation time 2469630460 ps
CPU time 6.95 seconds
Started Jul 02 07:49:51 AM PDT 24
Finished Jul 02 07:50:08 AM PDT 24
Peak memory 201548 kb
Host smart-70f215f4-df6f-4e13-ae28-f5a833b3e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756969543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3756969543
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.2962374836
Short name T402
Test name
Test status
Simulation time 2209232496 ps
CPU time 3.36 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:01 AM PDT 24
Peak memory 201452 kb
Host smart-82c0f9ad-8f25-4037-a2be-35bce71f52d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962374836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.2962374836
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.714650557
Short name T580
Test name
Test status
Simulation time 2542922049 ps
CPU time 1.97 seconds
Started Jul 02 07:49:57 AM PDT 24
Finished Jul 02 07:50:06 AM PDT 24
Peak memory 201524 kb
Host smart-b3a2b6a6-c2d9-4aa4-8670-cbd346a49534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714650557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.714650557
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.4153717223
Short name T506
Test name
Test status
Simulation time 2120334885 ps
CPU time 2.55 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:03 AM PDT 24
Peak memory 201348 kb
Host smart-36c10721-9103-4742-b963-9a49241896b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153717223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.4153717223
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.3377803023
Short name T244
Test name
Test status
Simulation time 16263716657 ps
CPU time 33.37 seconds
Started Jul 02 07:50:01 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 201572 kb
Host smart-ab78d814-5187-444b-892e-37543844557c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377803023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.3377803023
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1724484195
Short name T201
Test name
Test status
Simulation time 57043547001 ps
CPU time 40.97 seconds
Started Jul 02 07:49:46 AM PDT 24
Finished Jul 02 07:50:38 AM PDT 24
Peak memory 201876 kb
Host smart-069dc725-d016-4ed5-b69e-274bc857897a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724484195 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.1724484195
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3180565457
Short name T735
Test name
Test status
Simulation time 3417443247 ps
CPU time 3.49 seconds
Started Jul 02 07:49:47 AM PDT 24
Finished Jul 02 07:50:01 AM PDT 24
Peak memory 201524 kb
Host smart-2818a9bc-d9d2-4f83-80b2-8910fc7da435
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180565457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.3180565457
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.1248390269
Short name T575
Test name
Test status
Simulation time 2012856870 ps
CPU time 5.58 seconds
Started Jul 02 07:50:28 AM PDT 24
Finished Jul 02 07:50:35 AM PDT 24
Peak memory 201496 kb
Host smart-090da6a4-5b02-4a3a-962a-e04cf2b8051c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248390269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.1248390269
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1938452025
Short name T663
Test name
Test status
Simulation time 31149504553 ps
CPU time 27.07 seconds
Started Jul 02 07:50:33 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 201588 kb
Host smart-38da55bf-7914-49c1-9aa2-22dd553de3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938452025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.1
938452025
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3634621286
Short name T768
Test name
Test status
Simulation time 31596880746 ps
CPU time 78.72 seconds
Started Jul 02 07:50:30 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201752 kb
Host smart-28bcd101-9e1c-4301-8de2-95070cc53863
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634621286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.3634621286
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3489973004
Short name T524
Test name
Test status
Simulation time 5103942069 ps
CPU time 7.46 seconds
Started Jul 02 07:50:30 AM PDT 24
Finished Jul 02 07:50:39 AM PDT 24
Peak memory 201596 kb
Host smart-ce4be57e-50cd-4ccc-8be3-f1f7cd258cf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489973004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.3489973004
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.2126737737
Short name T179
Test name
Test status
Simulation time 839660428649 ps
CPU time 77.15 seconds
Started Jul 02 07:50:26 AM PDT 24
Finished Jul 02 07:51:45 AM PDT 24
Peak memory 201588 kb
Host smart-28ebd882-50a3-468c-8db0-22e21be97cbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126737737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.2126737737
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.435916241
Short name T485
Test name
Test status
Simulation time 2611567376 ps
CPU time 7.84 seconds
Started Jul 02 07:50:31 AM PDT 24
Finished Jul 02 07:50:41 AM PDT 24
Peak memory 201508 kb
Host smart-a20cd639-0e03-45f2-a229-908a5b53b892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435916241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.435916241
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.758271543
Short name T61
Test name
Test status
Simulation time 2549540273 ps
CPU time 1.2 seconds
Started Jul 02 07:50:27 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 201624 kb
Host smart-0127946b-8b8b-45c1-9d0c-a08d8ec59a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758271543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.758271543
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3311148718
Short name T461
Test name
Test status
Simulation time 2199028492 ps
CPU time 6.5 seconds
Started Jul 02 07:50:30 AM PDT 24
Finished Jul 02 07:50:39 AM PDT 24
Peak memory 201600 kb
Host smart-ede6395a-76c1-4737-8cf9-ee9263af0e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311148718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3311148718
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3109026771
Short name T68
Test name
Test status
Simulation time 2513584516 ps
CPU time 7.53 seconds
Started Jul 02 07:50:29 AM PDT 24
Finished Jul 02 07:50:38 AM PDT 24
Peak memory 201512 kb
Host smart-65742ab3-58ac-4379-af55-85f029ff2e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109026771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3109026771
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.3277093532
Short name T449
Test name
Test status
Simulation time 2109769919 ps
CPU time 5.88 seconds
Started Jul 02 07:50:29 AM PDT 24
Finished Jul 02 07:50:37 AM PDT 24
Peak memory 201452 kb
Host smart-e718c20c-5bb3-466a-ba4e-6c79acf369bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277093532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.3277093532
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.2939153133
Short name T204
Test name
Test status
Simulation time 10230625984 ps
CPU time 2.6 seconds
Started Jul 02 07:50:28 AM PDT 24
Finished Jul 02 07:50:32 AM PDT 24
Peak memory 201540 kb
Host smart-9258b8d0-9995-491f-974d-6d95367205eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939153133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.2939153133
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1454210356
Short name T447
Test name
Test status
Simulation time 2021759330 ps
CPU time 3.31 seconds
Started Jul 02 07:50:35 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 201556 kb
Host smart-b735f036-30e3-4ef8-9492-3f89e5acce21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454210356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1454210356
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3584085097
Short name T104
Test name
Test status
Simulation time 125288522489 ps
CPU time 305.01 seconds
Started Jul 02 07:50:36 AM PDT 24
Finished Jul 02 07:55:43 AM PDT 24
Peak memory 201976 kb
Host smart-39e81621-a2b5-4b67-86cc-6def9d4d3bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584085097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.3
584085097
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.3065297436
Short name T102
Test name
Test status
Simulation time 30628283259 ps
CPU time 81.33 seconds
Started Jul 02 07:50:35 AM PDT 24
Finished Jul 02 07:51:57 AM PDT 24
Peak memory 201776 kb
Host smart-86229ae8-1470-4005-a471-cf727d76b251
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065297436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.3065297436
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3050441297
Short name T16
Test name
Test status
Simulation time 99538590483 ps
CPU time 65 seconds
Started Jul 02 07:50:35 AM PDT 24
Finished Jul 02 07:51:42 AM PDT 24
Peak memory 201772 kb
Host smart-151991ac-a4c1-45c7-9cf9-881d97932394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050441297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.3050441297
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2012616989
Short name T588
Test name
Test status
Simulation time 2908551819 ps
CPU time 7.95 seconds
Started Jul 02 07:50:35 AM PDT 24
Finished Jul 02 07:50:45 AM PDT 24
Peak memory 201512 kb
Host smart-88f23ef7-6656-40ae-b512-f25c56b47f32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012616989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.2012616989
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.225020276
Short name T167
Test name
Test status
Simulation time 4725914377 ps
CPU time 13.28 seconds
Started Jul 02 07:50:33 AM PDT 24
Finished Jul 02 07:50:48 AM PDT 24
Peak memory 201632 kb
Host smart-2661cad3-3788-4a6c-9c43-81b5ab34c203
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225020276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctr
l_edge_detect.225020276
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.469376050
Short name T482
Test name
Test status
Simulation time 2627355528 ps
CPU time 2.16 seconds
Started Jul 02 07:50:33 AM PDT 24
Finished Jul 02 07:50:37 AM PDT 24
Peak memory 201544 kb
Host smart-2138d0c4-8b1c-4071-9763-456e9db26784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469376050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.469376050
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1306851216
Short name T320
Test name
Test status
Simulation time 2487293762 ps
CPU time 1.81 seconds
Started Jul 02 07:50:34 AM PDT 24
Finished Jul 02 07:50:38 AM PDT 24
Peak memory 201420 kb
Host smart-85a225f3-be9d-479e-b08f-3347a7158ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306851216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1306851216
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1234307179
Short name T567
Test name
Test status
Simulation time 2050175702 ps
CPU time 3.23 seconds
Started Jul 02 07:50:35 AM PDT 24
Finished Jul 02 07:50:41 AM PDT 24
Peak memory 201400 kb
Host smart-d26abe72-8482-4375-bd73-83216e262917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234307179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1234307179
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.261920191
Short name T67
Test name
Test status
Simulation time 2513574222 ps
CPU time 6.89 seconds
Started Jul 02 07:50:32 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 201552 kb
Host smart-29348b2b-95c4-4d34-b3c1-2d3f16439f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261920191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.261920191
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.4059129355
Short name T574
Test name
Test status
Simulation time 2115542227 ps
CPU time 3.66 seconds
Started Jul 02 07:50:32 AM PDT 24
Finished Jul 02 07:50:37 AM PDT 24
Peak memory 201472 kb
Host smart-5a017262-56e9-449f-9d55-ea436b1e6b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059129355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.4059129355
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.2383257483
Short name T428
Test name
Test status
Simulation time 7688644801 ps
CPU time 18.73 seconds
Started Jul 02 07:50:33 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 201536 kb
Host smart-ead24a5d-3a4a-4239-99db-309d3fa65c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383257483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.2383257483
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2650779337
Short name T311
Test name
Test status
Simulation time 148113833997 ps
CPU time 91.69 seconds
Started Jul 02 07:50:34 AM PDT 24
Finished Jul 02 07:52:07 AM PDT 24
Peak memory 210140 kb
Host smart-62577832-cf29-475c-81e4-0618ff459878
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650779337 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2650779337
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.4209922283
Short name T57
Test name
Test status
Simulation time 10977108529 ps
CPU time 3.56 seconds
Started Jul 02 07:50:37 AM PDT 24
Finished Jul 02 07:50:43 AM PDT 24
Peak memory 201488 kb
Host smart-ab42309f-8d36-45cc-ad0b-a3ff8586b617
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209922283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.4209922283
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.277339160
Short name T46
Test name
Test status
Simulation time 3497856248 ps
CPU time 2.87 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:50 AM PDT 24
Peak memory 201652 kb
Host smart-d2f4e73a-b82f-4a0a-937b-63197ecd6c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277339160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.277339160
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.647926576
Short name T679
Test name
Test status
Simulation time 23367418939 ps
CPU time 12.85 seconds
Started Jul 02 07:50:39 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 201820 kb
Host smart-479fabbe-7672-4f1c-ad0f-4a1d66e531f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647926576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_wi
th_pre_cond.647926576
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.264615006
Short name T507
Test name
Test status
Simulation time 3024046665 ps
CPU time 8.44 seconds
Started Jul 02 07:50:41 AM PDT 24
Finished Jul 02 07:50:52 AM PDT 24
Peak memory 201480 kb
Host smart-71c59b7f-636e-4e3a-88a3-5caa8fca9621
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264615006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ec_pwr_on_rst.264615006
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.1234506698
Short name T219
Test name
Test status
Simulation time 3146504549 ps
CPU time 5.23 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:50:48 AM PDT 24
Peak memory 201524 kb
Host smart-3bed340b-b72c-43a6-84dd-d872e86215c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234506698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.1234506698
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3638617383
Short name T126
Test name
Test status
Simulation time 2658189196 ps
CPU time 1.34 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:50:44 AM PDT 24
Peak memory 201516 kb
Host smart-a7db83ee-8260-416b-aa6c-a984ad033bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638617383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3638617383
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3292528848
Short name T744
Test name
Test status
Simulation time 2465726684 ps
CPU time 5.65 seconds
Started Jul 02 07:50:36 AM PDT 24
Finished Jul 02 07:50:44 AM PDT 24
Peak memory 201508 kb
Host smart-08f23b18-092e-4d4e-8271-d966149b330f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292528848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.3292528848
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.830733994
Short name T532
Test name
Test status
Simulation time 2149666321 ps
CPU time 0.98 seconds
Started Jul 02 07:50:33 AM PDT 24
Finished Jul 02 07:50:36 AM PDT 24
Peak memory 201480 kb
Host smart-350e2070-3dab-4b60-906d-bfea2fa82e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830733994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.830733994
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1630135822
Short name T542
Test name
Test status
Simulation time 2519436392 ps
CPU time 4.13 seconds
Started Jul 02 07:50:33 AM PDT 24
Finished Jul 02 07:50:39 AM PDT 24
Peak memory 201616 kb
Host smart-df81e11f-5539-4f05-a610-c4047fc911aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630135822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1630135822
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.2713555236
Short name T619
Test name
Test status
Simulation time 2128276521 ps
CPU time 1.85 seconds
Started Jul 02 07:50:35 AM PDT 24
Finished Jul 02 07:50:39 AM PDT 24
Peak memory 201400 kb
Host smart-b580e33b-e592-4d42-b744-cf366dbe84a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713555236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2713555236
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.484674188
Short name T565
Test name
Test status
Simulation time 12580013434 ps
CPU time 29.76 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 201504 kb
Host smart-1fa3591e-e03d-4c31-b1dd-6beb93637e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484674188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.484674188
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.391055243
Short name T152
Test name
Test status
Simulation time 60340653460 ps
CPU time 35.46 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:51:23 AM PDT 24
Peak memory 217888 kb
Host smart-28f5e2ac-6f15-43ec-9edb-81262544b6c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391055243 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.391055243
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2553882721
Short name T17
Test name
Test status
Simulation time 6787663955 ps
CPU time 2.49 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:50:44 AM PDT 24
Peak memory 201876 kb
Host smart-d35c77e1-ba2b-4e15-9444-a432b7f3bac7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553882721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.2553882721
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.930781208
Short name T699
Test name
Test status
Simulation time 2030070573 ps
CPU time 1.99 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:50:47 AM PDT 24
Peak memory 201520 kb
Host smart-796f30a7-7316-4274-beeb-0bb509410063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930781208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_tes
t.930781208
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.516494315
Short name T486
Test name
Test status
Simulation time 3382931058 ps
CPU time 8.48 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:50:50 AM PDT 24
Peak memory 201676 kb
Host smart-381a8a2a-5acb-455e-bbe6-97be614eb449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516494315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.516494315
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3525250949
Short name T379
Test name
Test status
Simulation time 128480738165 ps
CPU time 328.61 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:56:16 AM PDT 24
Peak memory 201788 kb
Host smart-c8d9220f-0b6c-4798-a160-9b0750e30943
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525250949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.3525250949
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2681218054
Short name T716
Test name
Test status
Simulation time 3646543867 ps
CPU time 5.48 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 201504 kb
Host smart-06652e10-82c3-42d9-a2cb-bd274875f6f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681218054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.2681218054
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1366093996
Short name T3
Test name
Test status
Simulation time 5295947909 ps
CPU time 3.02 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:50:49 AM PDT 24
Peak memory 201484 kb
Host smart-39d75879-f43b-4324-9eb5-04aafabcb364
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366093996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.1366093996
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1698463749
Short name T207
Test name
Test status
Simulation time 2631694584 ps
CPU time 2.42 seconds
Started Jul 02 07:50:41 AM PDT 24
Finished Jul 02 07:50:47 AM PDT 24
Peak memory 201524 kb
Host smart-72c74699-ed1d-4bf4-af3d-3862ce3308b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698463749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1698463749
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1883364598
Short name T431
Test name
Test status
Simulation time 2467118607 ps
CPU time 7.32 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:50:49 AM PDT 24
Peak memory 201504 kb
Host smart-98156e9c-292b-4914-ae59-c286a8dd2d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883364598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.1883364598
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.3830650646
Short name T720
Test name
Test status
Simulation time 2124415993 ps
CPU time 4.65 seconds
Started Jul 02 07:50:39 AM PDT 24
Finished Jul 02 07:50:45 AM PDT 24
Peak memory 201404 kb
Host smart-788475aa-5206-4ba7-84b7-295e402dec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830650646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.3830650646
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.879846309
Short name T231
Test name
Test status
Simulation time 2533519196 ps
CPU time 2.31 seconds
Started Jul 02 07:50:41 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 201520 kb
Host smart-6b9c43f3-edf1-4165-b117-7aed5fe0aff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879846309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.879846309
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.3202756457
Short name T490
Test name
Test status
Simulation time 2112842578 ps
CPU time 5.97 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:50:48 AM PDT 24
Peak memory 201472 kb
Host smart-94f71be9-9b0f-4eb2-a768-e3bf95f3f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202756457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3202756457
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1938492587
Short name T147
Test name
Test status
Simulation time 3944003083 ps
CPU time 2.15 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:50:44 AM PDT 24
Peak memory 201484 kb
Host smart-eebc8792-3c81-48bb-bd4c-dfcaa0fdf78d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938492587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.1938492587
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2407597243
Short name T605
Test name
Test status
Simulation time 2012457191 ps
CPU time 5.64 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 201612 kb
Host smart-3729c087-ec03-449e-b15c-16f9e0748245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407597243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2407597243
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.731103494
Short name T775
Test name
Test status
Simulation time 4002991504 ps
CPU time 3.2 seconds
Started Jul 02 07:50:41 AM PDT 24
Finished Jul 02 07:50:47 AM PDT 24
Peak memory 201604 kb
Host smart-91011774-fc1c-4ba6-bda3-b6a711516d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731103494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.731103494
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3744405380
Short name T213
Test name
Test status
Simulation time 44897994055 ps
CPU time 27.87 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:51:11 AM PDT 24
Peak memory 201652 kb
Host smart-766d672e-5fe6-4b23-9587-a689faf04663
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744405380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3744405380
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1355189704
Short name T515
Test name
Test status
Simulation time 4517612225 ps
CPU time 10.55 seconds
Started Jul 02 07:50:37 AM PDT 24
Finished Jul 02 07:50:49 AM PDT 24
Peak memory 201544 kb
Host smart-b63593cb-3249-476e-8b9a-8b0e5bb94854
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355189704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.1355189704
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.3826578225
Short name T192
Test name
Test status
Simulation time 2629820800 ps
CPU time 5.83 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:50:52 AM PDT 24
Peak memory 201516 kb
Host smart-f886bae9-c075-490f-8d16-b61e94aa649f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826578225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.3826578225
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1207993093
Short name T530
Test name
Test status
Simulation time 2607556129 ps
CPU time 7.74 seconds
Started Jul 02 07:50:41 AM PDT 24
Finished Jul 02 07:50:52 AM PDT 24
Peak memory 201524 kb
Host smart-187be061-b9f6-4606-9e0a-5c33f0d5b896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207993093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1207993093
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.393953644
Short name T746
Test name
Test status
Simulation time 2479402276 ps
CPU time 7.34 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 201620 kb
Host smart-70062c1d-7534-4ba6-b4b5-fa31e09f75c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393953644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.393953644
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.1781115025
Short name T742
Test name
Test status
Simulation time 2270660233 ps
CPU time 1.88 seconds
Started Jul 02 07:50:39 AM PDT 24
Finished Jul 02 07:50:42 AM PDT 24
Peak memory 201520 kb
Host smart-3e91f555-e7e4-4b96-848d-7c8a761858ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781115025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.1781115025
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.4124927705
Short name T23
Test name
Test status
Simulation time 2528804503 ps
CPU time 2.48 seconds
Started Jul 02 07:50:41 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 201616 kb
Host smart-e28f1273-ebab-4c9f-bedc-ddb5c0725bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124927705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.4124927705
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.247286872
Short name T609
Test name
Test status
Simulation time 2110719839 ps
CPU time 6.07 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 201524 kb
Host smart-fcb9f390-2b58-432e-90d7-f49215c9b5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247286872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.247286872
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.4155830480
Short name T764
Test name
Test status
Simulation time 15778192624 ps
CPU time 17.95 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:51:06 AM PDT 24
Peak memory 201632 kb
Host smart-2d4477aa-2fa0-413d-b877-a414ca8c0e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155830480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.4155830480
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.965441844
Short name T312
Test name
Test status
Simulation time 36058468151 ps
CPU time 42.68 seconds
Started Jul 02 07:50:48 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 210284 kb
Host smart-5bc627f0-c7dc-4768-ab81-21185abdf8c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965441844 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.965441844
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4074171485
Short name T496
Test name
Test status
Simulation time 4620127933 ps
CPU time 2.13 seconds
Started Jul 02 07:50:40 AM PDT 24
Finished Jul 02 07:50:45 AM PDT 24
Peak memory 201440 kb
Host smart-8e61e2c2-d092-44a9-9220-6c12f03f4ad3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074171485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.4074171485
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.3748012682
Short name T624
Test name
Test status
Simulation time 2028454540 ps
CPU time 2.13 seconds
Started Jul 02 07:50:46 AM PDT 24
Finished Jul 02 07:50:52 AM PDT 24
Peak memory 201508 kb
Host smart-d94b8838-96bc-46c4-85e9-0f832e07632b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748012682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.3748012682
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3080622006
Short name T76
Test name
Test status
Simulation time 89291648930 ps
CPU time 21.06 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 202160 kb
Host smart-fe9829da-3bfa-44cb-b723-854f2d131923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080622006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.3080622006
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2583714489
Short name T551
Test name
Test status
Simulation time 92295083493 ps
CPU time 130.79 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 201816 kb
Host smart-9ec35f31-a54f-45c0-97a9-df73d97c3895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583714489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.2583714489
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.38447081
Short name T738
Test name
Test status
Simulation time 3892869939 ps
CPU time 11.13 seconds
Started Jul 02 07:50:45 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 201524 kb
Host smart-9bc3bdbd-c295-4a61-a062-285e6283b335
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38447081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_ec_pwr_on_rst.38447081
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2581792985
Short name T187
Test name
Test status
Simulation time 2784293305 ps
CPU time 4.08 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:50:50 AM PDT 24
Peak memory 201496 kb
Host smart-7e3b1d7f-8c68-40c2-874f-afd86336a02a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581792985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.2581792985
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.298464217
Short name T634
Test name
Test status
Simulation time 2640174738 ps
CPU time 2.23 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:50:50 AM PDT 24
Peak memory 201524 kb
Host smart-9eb9dc21-b0d1-4d32-bea0-54556b8fef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298464217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.298464217
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.3872945733
Short name T319
Test name
Test status
Simulation time 2484540630 ps
CPU time 7.14 seconds
Started Jul 02 07:50:45 AM PDT 24
Finished Jul 02 07:50:56 AM PDT 24
Peak memory 201548 kb
Host smart-482e9cb6-d60a-47e6-bfe9-963aac3df5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872945733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.3872945733
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.4203046944
Short name T754
Test name
Test status
Simulation time 2036819414 ps
CPU time 3.24 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:50:49 AM PDT 24
Peak memory 201396 kb
Host smart-f65bf6cd-2348-4ba1-8a8d-a921fd802a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203046944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.4203046944
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.654629127
Short name T459
Test name
Test status
Simulation time 2512955474 ps
CPU time 7.21 seconds
Started Jul 02 07:50:48 AM PDT 24
Finished Jul 02 07:50:59 AM PDT 24
Peak memory 201500 kb
Host smart-9166b00b-da38-4c3d-b221-a5044f94df23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654629127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.654629127
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3290540521
Short name T118
Test name
Test status
Simulation time 2111439511 ps
CPU time 5.57 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:52 AM PDT 24
Peak memory 201392 kb
Host smart-70592ed6-014f-4a2e-aa5b-f32657e052ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290540521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3290540521
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.386121796
Short name T363
Test name
Test status
Simulation time 140170555135 ps
CPU time 311.67 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:56:00 AM PDT 24
Peak memory 201840 kb
Host smart-7bfc41de-b650-4e9e-870a-e06a581a21fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386121796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_st
ress_all.386121796
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.4029919380
Short name T578
Test name
Test status
Simulation time 69493623547 ps
CPU time 130.35 seconds
Started Jul 02 07:50:45 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 210136 kb
Host smart-f44ae89a-4048-4aa4-8b0a-b5ddd63d462f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029919380 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.4029919380
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2611382200
Short name T132
Test name
Test status
Simulation time 12929011986 ps
CPU time 8.47 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:50:57 AM PDT 24
Peak memory 201632 kb
Host smart-01b2d20e-d03a-49f0-a907-7aeb47219aee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611382200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.2611382200
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.1278598397
Short name T245
Test name
Test status
Simulation time 2009768842 ps
CPU time 5.99 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:50:51 AM PDT 24
Peak memory 201568 kb
Host smart-e4b69e90-465e-4b09-b8ae-14137657f181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278598397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.1278598397
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2791987797
Short name T48
Test name
Test status
Simulation time 3842523628 ps
CPU time 5.45 seconds
Started Jul 02 07:50:45 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 201572 kb
Host smart-ad32a823-939a-4fef-9872-5ed6040902cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791987797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.2
791987797
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1696698165
Short name T32
Test name
Test status
Simulation time 121695234663 ps
CPU time 76.26 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:52:05 AM PDT 24
Peak memory 201776 kb
Host smart-b85f9761-d583-4b5f-907b-b5848009b754
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696698165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1696698165
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2201092220
Short name T41
Test name
Test status
Simulation time 24088429853 ps
CPU time 33.08 seconds
Started Jul 02 07:50:47 AM PDT 24
Finished Jul 02 07:51:24 AM PDT 24
Peak memory 201832 kb
Host smart-a34dea88-11c8-4b2e-879c-1840fe053c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201092220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2201092220
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.488308507
Short name T328
Test name
Test status
Simulation time 4978014797 ps
CPU time 13.11 seconds
Started Jul 02 07:50:47 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201500 kb
Host smart-3902ed0d-8829-4bbd-a560-6d3780ab65c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488308507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ec_pwr_on_rst.488308507
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.4047407135
Short name T668
Test name
Test status
Simulation time 36901430235 ps
CPU time 38.64 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:51:27 AM PDT 24
Peak memory 201596 kb
Host smart-d2380853-705d-49eb-b582-a856573f15bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047407135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.4047407135
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1440391060
Short name T495
Test name
Test status
Simulation time 2631024536 ps
CPU time 2.16 seconds
Started Jul 02 07:50:48 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 201592 kb
Host smart-c345068b-15c9-4cc4-a408-4cbe04629417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440391060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.1440391060
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2427858728
Short name T681
Test name
Test status
Simulation time 2473366956 ps
CPU time 2.16 seconds
Started Jul 02 07:50:48 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 201592 kb
Host smart-29e61452-7327-4f58-bd0f-00159a4e21f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427858728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2427858728
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.361502033
Short name T618
Test name
Test status
Simulation time 2260562542 ps
CPU time 6.27 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:51:00 AM PDT 24
Peak memory 201464 kb
Host smart-b7adc532-6ace-4757-940c-c14fad12e664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361502033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.361502033
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2787844438
Short name T593
Test name
Test status
Simulation time 2510928349 ps
CPU time 6.89 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 201568 kb
Host smart-af18d80b-92e5-49c4-b1d9-f3337b29b764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787844438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2787844438
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.4090127883
Short name T536
Test name
Test status
Simulation time 2111595333 ps
CPU time 6.3 seconds
Started Jul 02 07:50:46 AM PDT 24
Finished Jul 02 07:50:57 AM PDT 24
Peak memory 201532 kb
Host smart-8504ffb8-d73b-4285-9074-a7b097b43aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090127883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.4090127883
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.3433230615
Short name T747
Test name
Test status
Simulation time 7649540137 ps
CPU time 19.59 seconds
Started Jul 02 07:50:44 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201660 kb
Host smart-a7971c16-bea8-41e4-a295-d1ce0fa2ed33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433230615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.3433230615
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1431746886
Short name T765
Test name
Test status
Simulation time 2033719647 ps
CPU time 1.93 seconds
Started Jul 02 07:50:45 AM PDT 24
Finished Jul 02 07:50:52 AM PDT 24
Peak memory 201504 kb
Host smart-622535cd-e87a-479f-8db6-9109112d1528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431746886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1431746886
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.644256551
Short name T24
Test name
Test status
Simulation time 3801605524 ps
CPU time 7.27 seconds
Started Jul 02 07:50:46 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 201704 kb
Host smart-c85d5e16-9386-4182-ac0f-8523d66b70a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644256551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.644256551
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1847814478
Short name T266
Test name
Test status
Simulation time 25604533493 ps
CPU time 16.16 seconds
Started Jul 02 07:50:47 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201816 kb
Host smart-c032af04-cdd2-4986-8ca4-2229958dc43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847814478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.1847814478
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2789616907
Short name T559
Test name
Test status
Simulation time 5129049793 ps
CPU time 13.93 seconds
Started Jul 02 07:50:48 AM PDT 24
Finished Jul 02 07:51:05 AM PDT 24
Peak memory 201572 kb
Host smart-e5893f37-88b5-4db9-932d-52362587daa5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789616907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.2789616907
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1666089773
Short name T222
Test name
Test status
Simulation time 3715496098 ps
CPU time 7.79 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 201612 kb
Host smart-a137b803-129d-4d95-9176-0915eb062e6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666089773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.1666089773
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1767871101
Short name T141
Test name
Test status
Simulation time 2620829209 ps
CPU time 2.82 seconds
Started Jul 02 07:50:43 AM PDT 24
Finished Jul 02 07:50:49 AM PDT 24
Peak memory 201544 kb
Host smart-c75fc333-0b25-4e28-8d30-0e504b59d343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767871101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.1767871101
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.4220357033
Short name T259
Test name
Test status
Simulation time 2478583916 ps
CPU time 2.08 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:50:57 AM PDT 24
Peak memory 201548 kb
Host smart-608bb4da-31f9-494e-ab3e-126cc493f102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220357033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.4220357033
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2607459999
Short name T762
Test name
Test status
Simulation time 2107839166 ps
CPU time 1.95 seconds
Started Jul 02 07:50:49 AM PDT 24
Finished Jul 02 07:50:56 AM PDT 24
Peak memory 201452 kb
Host smart-1da3c146-7141-4f39-9313-34645a145b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607459999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.2607459999
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.294274241
Short name T510
Test name
Test status
Simulation time 2118933508 ps
CPU time 2.77 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 201376 kb
Host smart-7ecb6acd-293f-4e08-84ea-c84ce32511e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294274241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.294274241
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3620887117
Short name T635
Test name
Test status
Simulation time 5380241554 ps
CPU time 2 seconds
Started Jul 02 07:50:42 AM PDT 24
Finished Jul 02 07:50:47 AM PDT 24
Peak memory 201608 kb
Host smart-bf99ad85-1d25-46db-8d36-3b7e0794309f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620887117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.3620887117
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3172273114
Short name T157
Test name
Test status
Simulation time 2013122237 ps
CPU time 5.33 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 201540 kb
Host smart-0a2a3c27-8804-4cf5-89ff-376af3760531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172273114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3172273114
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.527759856
Short name T572
Test name
Test status
Simulation time 27367475162 ps
CPU time 69.31 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:52:08 AM PDT 24
Peak memory 201684 kb
Host smart-f5cfba3e-05aa-429c-b2b7-07e7afbe75fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527759856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.527759856
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.575098861
Short name T434
Test name
Test status
Simulation time 24582007978 ps
CPU time 63.35 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:51:58 AM PDT 24
Peak memory 201868 kb
Host smart-cb2e019b-0d6e-4aa3-a593-e3ab96ab1012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575098861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.575098861
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3898330679
Short name T568
Test name
Test status
Simulation time 4238551543 ps
CPU time 3.2 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:50:57 AM PDT 24
Peak memory 201596 kb
Host smart-53686472-88b3-4dd7-a1ac-33cb62103bbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898330679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.3898330679
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.4244817744
Short name T529
Test name
Test status
Simulation time 2612819252 ps
CPU time 6.85 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:51:00 AM PDT 24
Peak memory 201496 kb
Host smart-e1e6c56f-ae12-4022-b24c-e28e6d9c34b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244817744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.4244817744
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3749796286
Short name T672
Test name
Test status
Simulation time 2455146072 ps
CPU time 7.24 seconds
Started Jul 02 07:50:46 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 201532 kb
Host smart-cacc9274-0d16-46ab-ae19-8ff995fa5e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749796286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3749796286
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2618643978
Short name T511
Test name
Test status
Simulation time 2098307030 ps
CPU time 3.29 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:50:59 AM PDT 24
Peak memory 201452 kb
Host smart-75441781-38cd-4882-b2d7-d1d9f8680594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618643978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.2618643978
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1281030920
Short name T70
Test name
Test status
Simulation time 2535696223 ps
CPU time 2.29 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 201512 kb
Host smart-152a8e5e-4112-4573-84f6-adb191866348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281030920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1281030920
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.1777283736
Short name T582
Test name
Test status
Simulation time 2109342445 ps
CPU time 5.93 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 201476 kb
Host smart-be41f7ac-bbac-429e-8911-904e4125c354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777283736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.1777283736
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.1739980494
Short name T659
Test name
Test status
Simulation time 11555199935 ps
CPU time 8.06 seconds
Started Jul 02 07:50:49 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 201596 kb
Host smart-bb74267d-cbea-4dcf-a0da-c63f6d766b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739980494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.1739980494
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3989601294
Short name T324
Test name
Test status
Simulation time 32659846555 ps
CPU time 53.61 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:51:48 AM PDT 24
Peak memory 210112 kb
Host smart-4f23d53a-daa8-4cb9-a949-e5c01aa673b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989601294 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.3989601294
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2520010977
Short name T480
Test name
Test status
Simulation time 10943571830 ps
CPU time 1.58 seconds
Started Jul 02 07:50:47 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 201512 kb
Host smart-36d43f33-4e71-4a4b-b939-478b5a53a4e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520010977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.2520010977
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.688113631
Short name T464
Test name
Test status
Simulation time 2045504785 ps
CPU time 1.9 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:51:02 AM PDT 24
Peak memory 201492 kb
Host smart-98f09d0d-cd1c-428a-9878-c87360d3ba52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688113631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_tes
t.688113631
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.980872528
Short name T492
Test name
Test status
Simulation time 3035798519 ps
CPU time 1.06 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:03 AM PDT 24
Peak memory 201624 kb
Host smart-2b28b152-ae66-4ef5-869b-2bb18a032112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980872528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.980872528
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.115038380
Short name T2
Test name
Test status
Simulation time 165898041538 ps
CPU time 445.99 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:58:22 AM PDT 24
Peak memory 201768 kb
Host smart-da029c07-a745-4a4a-b807-058555e32bb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115038380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_combo_detect.115038380
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.705348840
Short name T376
Test name
Test status
Simulation time 105119967828 ps
CPU time 67.99 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:52:09 AM PDT 24
Peak memory 201804 kb
Host smart-7a71d1e5-2393-4fb5-b5e1-bbe9c967ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705348840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wi
th_pre_cond.705348840
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2478260605
Short name T283
Test name
Test status
Simulation time 4238229275 ps
CPU time 3.04 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:50:59 AM PDT 24
Peak memory 201572 kb
Host smart-365dd4d8-7a71-4959-8c94-6b6967f2410c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478260605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.2478260605
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3192005407
Short name T170
Test name
Test status
Simulation time 2617655726 ps
CPU time 4.15 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:50:59 AM PDT 24
Peak memory 201532 kb
Host smart-e8de38a5-e57d-463c-8f9e-c64a4d9a0cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192005407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3192005407
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1783179850
Short name T661
Test name
Test status
Simulation time 2500494135 ps
CPU time 1.47 seconds
Started Jul 02 07:50:49 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 201496 kb
Host smart-b58d6e1d-32f8-4c70-ba7c-1008a39b9359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783179850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1783179850
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1845593409
Short name T122
Test name
Test status
Simulation time 2220146654 ps
CPU time 2.04 seconds
Started Jul 02 07:50:49 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 201536 kb
Host smart-ae463592-e4bc-4ce7-bd0d-498ae18565da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845593409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1845593409
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.2119467335
Short name T159
Test name
Test status
Simulation time 2543428449 ps
CPU time 1.92 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 201500 kb
Host smart-cf1ada51-4b29-43b9-b575-d1716a5f3da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119467335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.2119467335
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.2797249347
Short name T93
Test name
Test status
Simulation time 2109226276 ps
CPU time 5.68 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:51:00 AM PDT 24
Peak memory 201520 kb
Host smart-12e285e4-34d3-4263-8d8d-5a05d5fd253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797249347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2797249347
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.674016577
Short name T727
Test name
Test status
Simulation time 7064457167 ps
CPU time 19.65 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 201600 kb
Host smart-08f740d5-071f-4847-982d-ae9858d5f989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674016577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_st
ress_all.674016577
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.4284872642
Short name T153
Test name
Test status
Simulation time 11396547635 ps
CPU time 9.24 seconds
Started Jul 02 07:50:48 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 201580 kb
Host smart-51f2c0a8-16d0-447c-818e-d7f73a3fb02d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284872642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.4284872642
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.704690784
Short name T644
Test name
Test status
Simulation time 2015631062 ps
CPU time 5.79 seconds
Started Jul 02 07:50:02 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201612 kb
Host smart-1193d60a-0401-4973-a44f-61bfd629a8d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704690784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test
.704690784
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3858566521
Short name T295
Test name
Test status
Simulation time 3238582347 ps
CPU time 4.72 seconds
Started Jul 02 07:50:02 AM PDT 24
Finished Jul 02 07:50:11 AM PDT 24
Peak memory 201652 kb
Host smart-471cb917-4610-4556-95dd-915f48d40bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858566521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.3858566521
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.475251179
Short name T97
Test name
Test status
Simulation time 47410670151 ps
CPU time 8.69 seconds
Started Jul 02 07:50:09 AM PDT 24
Finished Jul 02 07:50:20 AM PDT 24
Peak memory 201708 kb
Host smart-08201634-5792-4fd2-8700-25dc48ddadc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475251179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_combo_detect.475251179
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1856035816
Short name T229
Test name
Test status
Simulation time 2503161799 ps
CPU time 1.08 seconds
Started Jul 02 07:49:49 AM PDT 24
Finished Jul 02 07:50:01 AM PDT 24
Peak memory 201520 kb
Host smart-9c5dcd70-eb7f-4348-80b7-e73b709642a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856035816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.1856035816
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3406419273
Short name T138
Test name
Test status
Simulation time 2276718126 ps
CPU time 3.63 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201524 kb
Host smart-7d8d3f0e-3288-4c8b-950e-0f54e9f50273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406419273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3406419273
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3991933643
Short name T690
Test name
Test status
Simulation time 90666452944 ps
CPU time 59.81 seconds
Started Jul 02 07:50:00 AM PDT 24
Finished Jul 02 07:51:06 AM PDT 24
Peak memory 201744 kb
Host smart-d4770f97-21fc-43fd-929f-a3bc01840243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991933643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.3991933643
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1376607266
Short name T400
Test name
Test status
Simulation time 3085078004 ps
CPU time 8.27 seconds
Started Jul 02 07:50:06 AM PDT 24
Finished Jul 02 07:50:17 AM PDT 24
Peak memory 201596 kb
Host smart-cdd595d8-6da6-4291-b7c0-610f09830068
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376607266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.1376607266
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.2107434927
Short name T683
Test name
Test status
Simulation time 4526375613 ps
CPU time 2.51 seconds
Started Jul 02 07:50:06 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201480 kb
Host smart-be820c85-ac97-4ce3-a427-cc304b04ce88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107434927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.2107434927
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1571193725
Short name T687
Test name
Test status
Simulation time 2623854638 ps
CPU time 2.87 seconds
Started Jul 02 07:50:02 AM PDT 24
Finished Jul 02 07:50:10 AM PDT 24
Peak memory 201592 kb
Host smart-ed66f4df-f49d-48f8-892c-285788aa1d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571193725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1571193725
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.2128401553
Short name T743
Test name
Test status
Simulation time 2453689425 ps
CPU time 2.23 seconds
Started Jul 02 07:49:56 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201528 kb
Host smart-d6bfe59a-e70e-4d31-be5b-288a8b4e6d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128401553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2128401553
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2685325929
Short name T642
Test name
Test status
Simulation time 2214621081 ps
CPU time 5.81 seconds
Started Jul 02 07:50:01 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201436 kb
Host smart-1b4fe5e2-7ecd-40ac-a086-25f84c1aa8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685325929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2685325929
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.2886813159
Short name T246
Test name
Test status
Simulation time 2535259214 ps
CPU time 2.39 seconds
Started Jul 02 07:49:56 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201528 kb
Host smart-987d5bc0-b34a-4bec-b398-2ee991c8d427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886813159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2886813159
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1116464085
Short name T300
Test name
Test status
Simulation time 22014959911 ps
CPU time 56.2 seconds
Started Jul 02 07:49:59 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 221132 kb
Host smart-26e6bb32-0c51-4459-95a6-cba642598f72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116464085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1116464085
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.2829347984
Short name T154
Test name
Test status
Simulation time 2119561152 ps
CPU time 3.16 seconds
Started Jul 02 07:49:53 AM PDT 24
Finished Jul 02 07:50:06 AM PDT 24
Peak memory 201372 kb
Host smart-debe56da-9a48-4a0c-a9e3-de586e7cfc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829347984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.2829347984
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.1295079535
Short name T323
Test name
Test status
Simulation time 8264879147 ps
CPU time 8.79 seconds
Started Jul 02 07:49:52 AM PDT 24
Finished Jul 02 07:50:11 AM PDT 24
Peak memory 201500 kb
Host smart-e9aed9fa-9337-4282-8f75-6db7bb04dfe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295079535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.1295079535
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.415804459
Short name T210
Test name
Test status
Simulation time 178069157873 ps
CPU time 186.01 seconds
Started Jul 02 07:49:51 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 217804 kb
Host smart-1ae481b4-f473-4c3f-b309-096a825c5387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415804459 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.415804459
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3017374579
Short name T86
Test name
Test status
Simulation time 2919469440 ps
CPU time 1.17 seconds
Started Jul 02 07:50:06 AM PDT 24
Finished Jul 02 07:50:10 AM PDT 24
Peak memory 201504 kb
Host smart-cbb8aee6-b734-4f6a-9beb-2c979b6fc54d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017374579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.3017374579
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3321368719
Short name T734
Test name
Test status
Simulation time 2013230262 ps
CPU time 5.34 seconds
Started Jul 02 07:50:47 AM PDT 24
Finished Jul 02 07:50:57 AM PDT 24
Peak memory 201612 kb
Host smart-900a505a-f59b-4904-94b5-e3990b1a423c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321368719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3321368719
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2111432198
Short name T189
Test name
Test status
Simulation time 227007993370 ps
CPU time 154.4 seconds
Started Jul 02 07:50:49 AM PDT 24
Finished Jul 02 07:53:27 AM PDT 24
Peak memory 201672 kb
Host smart-a59bc312-e312-44e1-b2a5-4c5a2b2e97b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111432198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.2
111432198
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.1959100849
Short name T771
Test name
Test status
Simulation time 127819906500 ps
CPU time 108.49 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:52:48 AM PDT 24
Peak memory 201680 kb
Host smart-8b30583f-1be5-4333-b799-c7a50f28473b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959100849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.1959100849
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.782128519
Short name T374
Test name
Test status
Simulation time 57879806097 ps
CPU time 11.16 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:13 AM PDT 24
Peak memory 201760 kb
Host smart-98a3a2bf-0eec-44f4-b470-45740bccce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782128519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_wi
th_pre_cond.782128519
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3105283525
Short name T684
Test name
Test status
Simulation time 2539733975 ps
CPU time 3.67 seconds
Started Jul 02 07:50:49 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 201500 kb
Host smart-eb54947b-cd7f-46ea-9608-877d069d84a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105283525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3105283525
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.858313311
Short name T224
Test name
Test status
Simulation time 5076877829 ps
CPU time 1.77 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:50:56 AM PDT 24
Peak memory 201552 kb
Host smart-f9257574-a4f6-4429-a438-8af4fd8129ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858313311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr
l_edge_detect.858313311
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.933275619
Short name T413
Test name
Test status
Simulation time 2620997290 ps
CPU time 2.97 seconds
Started Jul 02 07:50:52 AM PDT 24
Finished Jul 02 07:50:59 AM PDT 24
Peak memory 201848 kb
Host smart-17e2eced-b058-4bc5-8b22-ba6b408f8f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933275619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.933275619
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.2654999479
Short name T331
Test name
Test status
Simulation time 2461983409 ps
CPU time 7.24 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:51:03 AM PDT 24
Peak memory 201504 kb
Host smart-b8b80cc6-fa9a-4e67-bd44-6f77c5677357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654999479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.2654999479
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3448255609
Short name T653
Test name
Test status
Simulation time 2177433478 ps
CPU time 1.92 seconds
Started Jul 02 07:50:49 AM PDT 24
Finished Jul 02 07:50:55 AM PDT 24
Peak memory 201440 kb
Host smart-aab8417d-1ebf-40f8-a79c-85101c0c8e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448255609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3448255609
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3208159132
Short name T498
Test name
Test status
Simulation time 2540458871 ps
CPU time 1.99 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:03 AM PDT 24
Peak memory 201528 kb
Host smart-089218cf-433d-4ce1-ac0e-1b3b10ca2688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208159132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.3208159132
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.3010811410
Short name T442
Test name
Test status
Simulation time 2129261138 ps
CPU time 1.96 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:03 AM PDT 24
Peak memory 201452 kb
Host smart-229ee9d0-3a0f-4979-a708-efebf5553dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010811410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.3010811410
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.2820124809
Short name T595
Test name
Test status
Simulation time 10899882793 ps
CPU time 4.09 seconds
Started Jul 02 07:50:54 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201596 kb
Host smart-299ff894-5e73-4f33-86cb-91c0cee142fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820124809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.2820124809
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.2969323663
Short name T697
Test name
Test status
Simulation time 35953093194 ps
CPU time 76.22 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:52:18 AM PDT 24
Peak memory 218204 kb
Host smart-8384a144-04e1-402c-a27e-d0195d80def6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969323663 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.2969323663
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2811249727
Short name T466
Test name
Test status
Simulation time 5747310734 ps
CPU time 6.68 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:51:02 AM PDT 24
Peak memory 201528 kb
Host smart-302f40d7-7269-469c-a895-48bd31e2fbb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811249727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.2811249727
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.3698616966
Short name T604
Test name
Test status
Simulation time 2015272633 ps
CPU time 5.62 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201564 kb
Host smart-83a0c9c0-a3c3-4ac1-b14e-fb6623160c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698616966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.3698616966
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.455245359
Short name T508
Test name
Test status
Simulation time 3379494857 ps
CPU time 2.6 seconds
Started Jul 02 07:50:51 AM PDT 24
Finished Jul 02 07:50:58 AM PDT 24
Peak memory 201608 kb
Host smart-ed6e3745-269e-4048-8b0c-828866484219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455245359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.455245359
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.1088272559
Short name T270
Test name
Test status
Simulation time 144401874818 ps
CPU time 35.33 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:38 AM PDT 24
Peak memory 201720 kb
Host smart-b80773c7-38a2-4081-9256-c65e54e89cea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088272559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.1088272559
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1527465209
Short name T372
Test name
Test status
Simulation time 125284983385 ps
CPU time 21.49 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:51:22 AM PDT 24
Peak memory 201708 kb
Host smart-ad7a7157-928c-4514-ad96-65f9411d8831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527465209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.1527465209
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2830409618
Short name T417
Test name
Test status
Simulation time 4145438248 ps
CPU time 1.83 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201572 kb
Host smart-6b0c49b6-d813-4f5d-9479-ccafb213d291
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830409618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.2830409618
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.2076897211
Short name T253
Test name
Test status
Simulation time 3962907711 ps
CPU time 4.12 seconds
Started Jul 02 07:50:50 AM PDT 24
Finished Jul 02 07:50:59 AM PDT 24
Peak memory 201592 kb
Host smart-d4fc2698-a3ed-40ce-b1cb-aed5e2fd491d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076897211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.2076897211
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.4095441791
Short name T203
Test name
Test status
Simulation time 2626985698 ps
CPU time 2.75 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201500 kb
Host smart-677024c5-e5db-44d1-a845-e6d63ba8e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095441791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.4095441791
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2937340903
Short name T336
Test name
Test status
Simulation time 2492024782 ps
CPU time 1.61 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:51:00 AM PDT 24
Peak memory 201624 kb
Host smart-29c32335-debe-4981-8b4d-af1b1013a139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937340903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2937340903
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.616511308
Short name T281
Test name
Test status
Simulation time 2096217251 ps
CPU time 5.89 seconds
Started Jul 02 07:50:52 AM PDT 24
Finished Jul 02 07:51:02 AM PDT 24
Peak memory 201488 kb
Host smart-6259f369-8f5f-435f-8b8c-376023755d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616511308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.616511308
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2132183702
Short name T186
Test name
Test status
Simulation time 2510530485 ps
CPU time 7.43 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:09 AM PDT 24
Peak memory 201532 kb
Host smart-d6753a95-5df0-4091-881a-3dd2489132ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132183702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2132183702
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.3406779216
Short name T285
Test name
Test status
Simulation time 2133620516 ps
CPU time 1.75 seconds
Started Jul 02 07:50:47 AM PDT 24
Finished Jul 02 07:50:53 AM PDT 24
Peak memory 201492 kb
Host smart-89694da8-b101-45a8-a3bb-7196da315f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406779216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.3406779216
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.2858911319
Short name T107
Test name
Test status
Simulation time 179363561873 ps
CPU time 39.97 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:51:38 AM PDT 24
Peak memory 201848 kb
Host smart-639590e6-7a21-4d80-a43b-dd8a3ddfd1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858911319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.2858911319
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1057348576
Short name T84
Test name
Test status
Simulation time 37749443815 ps
CPU time 90.79 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 210156 kb
Host smart-6819cacf-4a66-45ad-a148-a3511782749b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057348576 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.1057348576
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.2652618976
Short name T645
Test name
Test status
Simulation time 2030325826 ps
CPU time 1.92 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:51:02 AM PDT 24
Peak memory 201612 kb
Host smart-0da7768b-5a86-4bbf-88b2-ec141ffa4038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652618976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.2652618976
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1739621301
Short name T418
Test name
Test status
Simulation time 3610422066 ps
CPU time 9.91 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201676 kb
Host smart-3a2f0172-50ab-44e5-973d-b995423e2317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739621301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1
739621301
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.648350527
Short name T694
Test name
Test status
Simulation time 149978362848 ps
CPU time 182.86 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:54:05 AM PDT 24
Peak memory 202152 kb
Host smart-aa86730e-05f7-465f-b66d-8e81e1fb42a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648350527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_combo_detect.648350527
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.4043531352
Short name T549
Test name
Test status
Simulation time 43712613561 ps
CPU time 27.73 seconds
Started Jul 02 07:50:54 AM PDT 24
Finished Jul 02 07:51:28 AM PDT 24
Peak memory 201832 kb
Host smart-fd796e37-497e-43fb-a3fe-7815de3291c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043531352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.4043531352
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.2988924197
Short name T667
Test name
Test status
Simulation time 2841662099 ps
CPU time 2.58 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:06 AM PDT 24
Peak memory 201488 kb
Host smart-7ca023fc-c65d-4d49-a1ec-6b16585d2860
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988924197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.2988924197
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.755601013
Short name T11
Test name
Test status
Simulation time 3972612539 ps
CPU time 8.09 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:51:05 AM PDT 24
Peak memory 201560 kb
Host smart-15d94835-e33e-4bff-bec7-85a808a52934
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755601013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctr
l_edge_detect.755601013
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2383364380
Short name T535
Test name
Test status
Simulation time 2611113404 ps
CPU time 7.14 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:11 AM PDT 24
Peak memory 201500 kb
Host smart-4e92c8e0-3372-4099-bdff-1d874e69f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383364380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.2383364380
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.3127475534
Short name T715
Test name
Test status
Simulation time 2469922111 ps
CPU time 6.47 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201436 kb
Host smart-ace39055-1ea8-4732-ad75-41c0c1a6be71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127475534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.3127475534
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1409442874
Short name T286
Test name
Test status
Simulation time 2046364188 ps
CPU time 5.91 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201444 kb
Host smart-5affe340-3717-4a9f-ac76-97fb579bdbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409442874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1409442874
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2153726933
Short name T671
Test name
Test status
Simulation time 2522374102 ps
CPU time 4.05 seconds
Started Jul 02 07:50:58 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201596 kb
Host smart-309ac330-28b7-4db8-b5f0-244801eaedcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153726933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2153726933
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.231866971
Short name T669
Test name
Test status
Simulation time 2126040835 ps
CPU time 2.28 seconds
Started Jul 02 07:50:54 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 201508 kb
Host smart-83fd8443-472a-4262-aee1-89fbafe1c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231866971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.231866971
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.1306120520
Short name T597
Test name
Test status
Simulation time 18786035796 ps
CPU time 3.83 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201532 kb
Host smart-3304576d-9795-4371-847d-7e4f8d6472cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306120520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.1306120520
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.400920492
Short name T598
Test name
Test status
Simulation time 105108556156 ps
CPU time 17.52 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:21 AM PDT 24
Peak memory 210268 kb
Host smart-4388ac47-6e9a-42dc-b5e1-f930b19e0205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400920492 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.400920492
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3008829703
Short name T443
Test name
Test status
Simulation time 9427582528 ps
CPU time 2.02 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:03 AM PDT 24
Peak memory 201480 kb
Host smart-8930f839-e0db-4421-95cc-e6ed490a9f9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008829703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3008829703
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.2306885422
Short name T130
Test name
Test status
Simulation time 2029701814 ps
CPU time 1.77 seconds
Started Jul 02 07:50:54 AM PDT 24
Finished Jul 02 07:51:01 AM PDT 24
Peak memory 201608 kb
Host smart-ade70e67-33e1-46a5-91c7-a2b4e1f98f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306885422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.2306885422
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.488517508
Short name T602
Test name
Test status
Simulation time 3299633766 ps
CPU time 4.55 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201684 kb
Host smart-b33d6746-ab47-49af-907e-99d6bf0ad987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488517508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.488517508
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.4127766890
Short name T362
Test name
Test status
Simulation time 109288051460 ps
CPU time 66.92 seconds
Started Jul 02 07:50:54 AM PDT 24
Finished Jul 02 07:52:06 AM PDT 24
Peak memory 201872 kb
Host smart-a759f2bb-83a2-4351-9e05-3c5a812102e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127766890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.4127766890
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.549611583
Short name T49
Test name
Test status
Simulation time 3289719306 ps
CPU time 1.21 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:05 AM PDT 24
Peak memory 201488 kb
Host smart-6acae583-f2d1-465b-8414-b9d350c36a65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549611583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ec_pwr_on_rst.549611583
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.1812680665
Short name T180
Test name
Test status
Simulation time 3580372009 ps
CPU time 7.32 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201556 kb
Host smart-80acfc74-6834-4927-94e6-7606264285a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812680665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.1812680665
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2317630953
Short name T488
Test name
Test status
Simulation time 2613587595 ps
CPU time 7.86 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 201844 kb
Host smart-c6e3c23f-fae4-4dda-bdd6-b8e951288f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317630953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2317630953
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.497879334
Short name T5
Test name
Test status
Simulation time 2458898995 ps
CPU time 3.7 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201608 kb
Host smart-58c636a8-b248-4c28-a4ce-c4d4245e14f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497879334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.497879334
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.2270297586
Short name T322
Test name
Test status
Simulation time 2256954036 ps
CPU time 6.44 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:09 AM PDT 24
Peak memory 201596 kb
Host smart-f9944257-2d5a-4caf-ae19-b01a660749e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270297586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2270297586
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1558234020
Short name T250
Test name
Test status
Simulation time 2512647334 ps
CPU time 7.51 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:11 AM PDT 24
Peak memory 201528 kb
Host smart-a6a936c1-76e5-43d8-a8d4-39d2e08a787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558234020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.1558234020
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.1191824411
Short name T404
Test name
Test status
Simulation time 2110240758 ps
CPU time 6 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201436 kb
Host smart-dd8aaf89-1011-4723-8376-aa3e98071f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191824411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.1191824411
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1752205683
Short name T316
Test name
Test status
Simulation time 27369025988 ps
CPU time 73.57 seconds
Started Jul 02 07:51:00 AM PDT 24
Finished Jul 02 07:52:18 AM PDT 24
Peak memory 218268 kb
Host smart-e01fb90c-d0a3-4e6c-af49-ad22b789c6e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752205683 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.1752205683
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3838377757
Short name T472
Test name
Test status
Simulation time 5327866440 ps
CPU time 5.88 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:09 AM PDT 24
Peak memory 201596 kb
Host smart-796c2c03-07a4-4f6c-a6f3-4daa4e7573b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838377757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.3838377757
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.9516008
Short name T500
Test name
Test status
Simulation time 2016438658 ps
CPU time 5.59 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 07:51:03 AM PDT 24
Peak memory 201512 kb
Host smart-902de43d-97b2-4eb9-a629-e25cdea0c07a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9516008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.9516008
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2142730120
Short name T487
Test name
Test status
Simulation time 3464139171 ps
CPU time 5.14 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201604 kb
Host smart-840bc943-4781-4831-ac30-06778ee122fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142730120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2
142730120
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.673633181
Short name T680
Test name
Test status
Simulation time 156793969270 ps
CPU time 194.83 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:54:16 AM PDT 24
Peak memory 201768 kb
Host smart-d5f33afd-67fb-4df5-a479-c0270e576360
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673633181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_combo_detect.673633181
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.944785283
Short name T465
Test name
Test status
Simulation time 484637457277 ps
CPU time 1263.63 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 201520 kb
Host smart-0c4eb255-df22-49cf-ae25-8ca5b18cb40a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944785283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ec_pwr_on_rst.944785283
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3627262785
Short name T429
Test name
Test status
Simulation time 2612196818 ps
CPU time 7.11 seconds
Started Jul 02 07:50:56 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201544 kb
Host smart-ce9fb439-c918-4ea9-8fe8-ceb8937b5ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627262785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3627262785
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3623352507
Short name T333
Test name
Test status
Simulation time 2499907556 ps
CPU time 1.96 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201624 kb
Host smart-8789941a-9a6c-46a0-a0b8-2f4f95b5d7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623352507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3623352507
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1437978697
Short name T714
Test name
Test status
Simulation time 2154311036 ps
CPU time 3.25 seconds
Started Jul 02 07:50:55 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201444 kb
Host smart-44a2e49a-1ce7-41fe-a747-8e7460ed8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437978697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1437978697
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.1804734131
Short name T517
Test name
Test status
Simulation time 2528304732 ps
CPU time 2.29 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:05 AM PDT 24
Peak memory 201524 kb
Host smart-19f9abc4-216a-4aa3-9189-18848f14344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804734131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1804734131
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.1202095733
Short name T455
Test name
Test status
Simulation time 2115821235 ps
CPU time 3.31 seconds
Started Jul 02 07:50:54 AM PDT 24
Finished Jul 02 07:51:03 AM PDT 24
Peak memory 201480 kb
Host smart-894e3364-3f85-44b9-9196-4bfa3acab440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202095733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1202095733
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.4272837484
Short name T783
Test name
Test status
Simulation time 6926906317 ps
CPU time 17 seconds
Started Jul 02 07:50:54 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201524 kb
Host smart-94b4fe19-d264-4881-b116-8772ac4b5f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272837484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.4272837484
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.4036948699
Short name T446
Test name
Test status
Simulation time 2076061738378 ps
CPU time 555 seconds
Started Jul 02 07:50:53 AM PDT 24
Finished Jul 02 08:00:13 AM PDT 24
Peak memory 201596 kb
Host smart-5253e94b-5202-4bc5-bc63-9a01373754a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036948699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.4036948699
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.3448404361
Short name T491
Test name
Test status
Simulation time 2010123465 ps
CPU time 5.29 seconds
Started Jul 02 07:51:00 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 201512 kb
Host smart-8d412051-88c5-44d1-92c1-ec9dc9a0fa8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448404361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.3448404361
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.681687168
Short name T47
Test name
Test status
Simulation time 3313312743 ps
CPU time 1.88 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:06 AM PDT 24
Peak memory 201668 kb
Host smart-adcb4675-db93-4f80-b243-22b23cdc0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681687168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.681687168
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.3355035285
Short name T457
Test name
Test status
Simulation time 53558490996 ps
CPU time 34.98 seconds
Started Jul 02 07:51:01 AM PDT 24
Finished Jul 02 07:51:40 AM PDT 24
Peak memory 201788 kb
Host smart-b9f69b91-3fe8-40cf-94fc-399b3243bf92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355035285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.3355035285
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1473682348
Short name T730
Test name
Test status
Simulation time 25088265202 ps
CPU time 34.05 seconds
Started Jul 02 07:51:00 AM PDT 24
Finished Jul 02 07:51:39 AM PDT 24
Peak memory 201876 kb
Host smart-e7a2d86b-3424-49ba-b5ed-56dd87d88093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473682348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.1473682348
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1043894062
Short name T287
Test name
Test status
Simulation time 3739048441 ps
CPU time 9.92 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:19 AM PDT 24
Peak memory 201508 kb
Host smart-2eec48e4-77db-47f8-a0ad-069bb3f786bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043894062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.1043894062
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2986430502
Short name T177
Test name
Test status
Simulation time 3569764254 ps
CPU time 6.46 seconds
Started Jul 02 07:51:04 AM PDT 24
Finished Jul 02 07:51:13 AM PDT 24
Peak memory 201560 kb
Host smart-63bd44ff-6c46-4933-890d-47fea7dfb00d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986430502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.2986430502
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3291437391
Short name T112
Test name
Test status
Simulation time 2610189389 ps
CPU time 7.96 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:12 AM PDT 24
Peak memory 201588 kb
Host smart-0a206311-dfd8-4edd-a2b9-9c3a70ecabdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291437391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3291437391
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.4028686438
Short name T4
Test name
Test status
Simulation time 2471253269 ps
CPU time 7.33 seconds
Started Jul 02 07:50:57 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 201512 kb
Host smart-24cc08f7-1d8a-4571-982c-8fffe7ff2a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028686438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.4028686438
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.307024885
Short name T184
Test name
Test status
Simulation time 2065246948 ps
CPU time 5.68 seconds
Started Jul 02 07:51:04 AM PDT 24
Finished Jul 02 07:51:12 AM PDT 24
Peak memory 201380 kb
Host smart-ccd117c0-638d-40e7-83c3-d3a9fe3390f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307024885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.307024885
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3017677836
Short name T169
Test name
Test status
Simulation time 2524145326 ps
CPU time 2.38 seconds
Started Jul 02 07:51:04 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 201580 kb
Host smart-516f4fcb-6577-4507-acac-0d23c31a1951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017677836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3017677836
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.1492446396
Short name T614
Test name
Test status
Simulation time 2123699850 ps
CPU time 2.04 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:06 AM PDT 24
Peak memory 201460 kb
Host smart-8256ded8-021e-41ed-a1f4-55a5d443631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492446396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.1492446396
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.302796242
Short name T279
Test name
Test status
Simulation time 103105767365 ps
CPU time 58.7 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:52:03 AM PDT 24
Peak memory 201872 kb
Host smart-7a0f469e-5938-4c7a-8d06-435aef3b17e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302796242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_st
ress_all.302796242
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.506767767
Short name T273
Test name
Test status
Simulation time 4175591598 ps
CPU time 6.45 seconds
Started Jul 02 07:51:00 AM PDT 24
Finished Jul 02 07:51:11 AM PDT 24
Peak memory 201544 kb
Host smart-e9f28367-9564-48d6-b67e-6808f98dbf12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506767767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ultra_low_pwr.506767767
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.2422440731
Short name T470
Test name
Test status
Simulation time 2014322414 ps
CPU time 5.6 seconds
Started Jul 02 07:50:59 AM PDT 24
Finished Jul 02 07:51:09 AM PDT 24
Peak memory 201616 kb
Host smart-96a7ec31-63f9-45de-b3a3-1ad335be6055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422440731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.2422440731
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2287634396
Short name T561
Test name
Test status
Simulation time 3165635882 ps
CPU time 8.86 seconds
Started Jul 02 07:51:26 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 201556 kb
Host smart-597863b1-2f95-4108-9626-12f748ccfd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287634396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
287634396
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3673298034
Short name T361
Test name
Test status
Simulation time 145814015555 ps
CPU time 94.33 seconds
Started Jul 02 07:51:02 AM PDT 24
Finished Jul 02 07:52:40 AM PDT 24
Peak memory 201792 kb
Host smart-01d8c2c5-0d03-4e6c-b03c-75819c3379a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673298034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.3673298034
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3223072551
Short name T725
Test name
Test status
Simulation time 4707490808 ps
CPU time 12.49 seconds
Started Jul 02 07:51:04 AM PDT 24
Finished Jul 02 07:51:19 AM PDT 24
Peak memory 201484 kb
Host smart-5120427e-8cf1-4c13-9fca-4dca2332cef8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223072551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.3223072551
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.109742879
Short name T165
Test name
Test status
Simulation time 3386316426 ps
CPU time 3.35 seconds
Started Jul 02 07:50:58 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201556 kb
Host smart-1d899467-a6c2-41c6-b532-0f9f9b88da10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109742879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctr
l_edge_detect.109742879
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1557330484
Short name T688
Test name
Test status
Simulation time 2629393250 ps
CPU time 2.21 seconds
Started Jul 02 07:51:01 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201544 kb
Host smart-2631f301-6dcb-45e9-9aef-30b4d9003558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557330484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1557330484
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.285155847
Short name T637
Test name
Test status
Simulation time 2494494623 ps
CPU time 2.13 seconds
Started Jul 02 07:51:18 AM PDT 24
Finished Jul 02 07:51:23 AM PDT 24
Peak memory 201500 kb
Host smart-a99c5d9f-6e6a-40c5-82e4-18e9641e83b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285155847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.285155847
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.1563598251
Short name T696
Test name
Test status
Simulation time 2066457838 ps
CPU time 1.99 seconds
Started Jul 02 07:51:00 AM PDT 24
Finished Jul 02 07:51:07 AM PDT 24
Peak memory 201560 kb
Host smart-cb390887-d3ef-4d85-a268-ee41485998bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563598251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1563598251
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3758867098
Short name T503
Test name
Test status
Simulation time 2507656578 ps
CPU time 7.3 seconds
Started Jul 02 07:51:26 AM PDT 24
Finished Jul 02 07:51:34 AM PDT 24
Peak memory 201516 kb
Host smart-0b10595d-105b-458a-b504-c664cb9892ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758867098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3758867098
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.3574950213
Short name T646
Test name
Test status
Simulation time 2117116379 ps
CPU time 3.17 seconds
Started Jul 02 07:51:00 AM PDT 24
Finished Jul 02 07:51:08 AM PDT 24
Peak memory 201452 kb
Host smart-52510690-b4cf-4f11-95ce-c92c3c49e760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574950213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3574950213
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.1968815384
Short name T217
Test name
Test status
Simulation time 98301751290 ps
CPU time 19.46 seconds
Started Jul 02 07:51:03 AM PDT 24
Finished Jul 02 07:51:26 AM PDT 24
Peak memory 201768 kb
Host smart-7e795326-e245-4b9c-ad7f-8955bf60e332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968815384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.1968815384
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2556051487
Short name T303
Test name
Test status
Simulation time 1429353827109 ps
CPU time 163.12 seconds
Started Jul 02 07:51:04 AM PDT 24
Finished Jul 02 07:53:51 AM PDT 24
Peak memory 218264 kb
Host smart-3e3c3eb7-1733-4d9d-a5dd-5736c5e0a611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556051487 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2556051487
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.827614968
Short name T698
Test name
Test status
Simulation time 6680940988 ps
CPU time 3.92 seconds
Started Jul 02 07:51:22 AM PDT 24
Finished Jul 02 07:51:28 AM PDT 24
Peak memory 201488 kb
Host smart-7f62c7eb-a20c-4b46-8e2b-948f80bfab7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827614968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.827614968
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.4038058723
Short name T243
Test name
Test status
Simulation time 2011175369 ps
CPU time 5.89 seconds
Started Jul 02 07:51:00 AM PDT 24
Finished Jul 02 07:51:11 AM PDT 24
Peak memory 201484 kb
Host smart-08e7df72-e15a-4a2a-b7d6-710d89d9c7a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038058723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.4038058723
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.164212415
Short name T722
Test name
Test status
Simulation time 203928607894 ps
CPU time 195.84 seconds
Started Jul 02 07:51:03 AM PDT 24
Finished Jul 02 07:54:22 AM PDT 24
Peak memory 201688 kb
Host smart-9e6479dc-600a-497b-aed1-0d0f948f081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164212415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.164212415
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3719563889
Short name T543
Test name
Test status
Simulation time 90421408609 ps
CPU time 237.69 seconds
Started Jul 02 07:51:13 AM PDT 24
Finished Jul 02 07:55:12 AM PDT 24
Peak memory 201700 kb
Host smart-e1f8e89a-c29e-46c5-b5b7-f7a1e300a9ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719563889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.3719563889
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.311947724
Short name T215
Test name
Test status
Simulation time 35335857348 ps
CPU time 46.24 seconds
Started Jul 02 07:51:08 AM PDT 24
Finished Jul 02 07:51:57 AM PDT 24
Peak memory 201800 kb
Host smart-9b470adb-31ed-40c9-94d4-bcd01caf45bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311947724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_wi
th_pre_cond.311947724
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3653147985
Short name T173
Test name
Test status
Simulation time 4287107981 ps
CPU time 11.96 seconds
Started Jul 02 07:51:05 AM PDT 24
Finished Jul 02 07:51:20 AM PDT 24
Peak memory 201564 kb
Host smart-3e51c89d-5b72-4c7e-ade4-ab4c6dad8a62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653147985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.3653147985
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.3696176042
Short name T737
Test name
Test status
Simulation time 3029521847 ps
CPU time 2.45 seconds
Started Jul 02 07:51:04 AM PDT 24
Finished Jul 02 07:51:09 AM PDT 24
Peak memory 201620 kb
Host smart-a2992f33-9b17-4e8c-9107-32c99bac0535
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696176042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.3696176042
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3529787244
Short name T430
Test name
Test status
Simulation time 2615792135 ps
CPU time 3.94 seconds
Started Jul 02 07:51:04 AM PDT 24
Finished Jul 02 07:51:11 AM PDT 24
Peak memory 201496 kb
Host smart-136b61a3-860d-457a-a333-197d6453f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529787244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.3529787244
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.421598020
Short name T639
Test name
Test status
Simulation time 2461138042 ps
CPU time 7.25 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201532 kb
Host smart-0660fdd1-5fb2-4597-af9e-8374fe788f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421598020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.421598020
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1496483953
Short name T620
Test name
Test status
Simulation time 2182332151 ps
CPU time 2.2 seconds
Started Jul 02 07:51:18 AM PDT 24
Finished Jul 02 07:51:24 AM PDT 24
Peak memory 201512 kb
Host smart-9a725dbd-7a89-4918-be42-d0e8821981fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496483953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1496483953
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.991377361
Short name T441
Test name
Test status
Simulation time 2530139721 ps
CPU time 2.46 seconds
Started Jul 02 07:51:05 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 201568 kb
Host smart-a1522bce-1c05-4204-9992-f07eb1508e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991377361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.991377361
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.1704747050
Short name T240
Test name
Test status
Simulation time 2113153205 ps
CPU time 6.13 seconds
Started Jul 02 07:51:23 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201364 kb
Host smart-88ac36bd-5162-4a66-94ed-3234b2bba5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704747050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.1704747050
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1221706025
Short name T124
Test name
Test status
Simulation time 921246108566 ps
CPU time 24.84 seconds
Started Jul 02 07:51:17 AM PDT 24
Finished Jul 02 07:51:46 AM PDT 24
Peak memory 201472 kb
Host smart-ef55ebbb-12ef-4daa-9ae1-69bd89de5f14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221706025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1221706025
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2020885669
Short name T54
Test name
Test status
Simulation time 14164389269 ps
CPU time 10.61 seconds
Started Jul 02 07:51:00 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201632 kb
Host smart-a2dc9c75-df78-48d5-8f72-c2112b5ae526
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020885669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.2020885669
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.947035127
Short name T129
Test name
Test status
Simulation time 2123305345 ps
CPU time 0.94 seconds
Started Jul 02 07:51:17 AM PDT 24
Finished Jul 02 07:51:22 AM PDT 24
Peak memory 201544 kb
Host smart-00f95947-8847-4963-a34d-167fb14e3100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947035127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_tes
t.947035127
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2044467401
Short name T230
Test name
Test status
Simulation time 3079333006 ps
CPU time 8.19 seconds
Started Jul 02 07:51:07 AM PDT 24
Finished Jul 02 07:51:18 AM PDT 24
Peak memory 201636 kb
Host smart-ce7f7870-4ee5-4379-baeb-de2ddd11fddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044467401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2
044467401
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.3944267784
Short name T101
Test name
Test status
Simulation time 95807643478 ps
CPU time 67.66 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:52:28 AM PDT 24
Peak memory 201804 kb
Host smart-09c09308-61c9-4f88-b0fd-62b0eb3952be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944267784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.3944267784
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1578362382
Short name T182
Test name
Test status
Simulation time 3636065569 ps
CPU time 3.84 seconds
Started Jul 02 07:51:20 AM PDT 24
Finished Jul 02 07:51:26 AM PDT 24
Peak memory 201508 kb
Host smart-bcf697ae-9b55-46f7-862a-3ef1ff70983d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578362382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.1578362382
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.2206383487
Short name T686
Test name
Test status
Simulation time 3575979302 ps
CPU time 1.62 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:51:22 AM PDT 24
Peak memory 201484 kb
Host smart-53efbfb2-5883-4d22-9f7c-7a86f97e8d1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206383487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.2206383487
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.231190148
Short name T504
Test name
Test status
Simulation time 2619358861 ps
CPU time 3.98 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:13 AM PDT 24
Peak memory 201524 kb
Host smart-b4479526-594f-47b7-9cf9-bff1f5e547ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231190148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.231190148
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1729190026
Short name T770
Test name
Test status
Simulation time 2443675575 ps
CPU time 7.09 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201520 kb
Host smart-aff8a41f-eb5f-401e-8e52-ed6b57fa6738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729190026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.1729190026
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2630585762
Short name T555
Test name
Test status
Simulation time 2115577140 ps
CPU time 6.18 seconds
Started Jul 02 07:51:05 AM PDT 24
Finished Jul 02 07:51:14 AM PDT 24
Peak memory 201472 kb
Host smart-68777a7f-5ca9-4406-8f32-b21ad0b22883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630585762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2630585762
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.227979924
Short name T505
Test name
Test status
Simulation time 2112598201 ps
CPU time 6.15 seconds
Started Jul 02 07:51:24 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201444 kb
Host smart-e4e441fe-4b8c-4b7e-ac86-4bea6e4404d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227979924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.227979924
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.903465217
Short name T665
Test name
Test status
Simulation time 6584103331 ps
CPU time 17.99 seconds
Started Jul 02 07:51:22 AM PDT 24
Finished Jul 02 07:51:41 AM PDT 24
Peak memory 201504 kb
Host smart-428f1b55-ba2b-4280-8c4b-7f9efce8ddd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903465217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_st
ress_all.903465217
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3288638772
Short name T263
Test name
Test status
Simulation time 25625869820 ps
CPU time 68.78 seconds
Started Jul 02 07:51:19 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 210336 kb
Host smart-043225d2-ea10-4289-b8a2-173d645dbfe9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288638772 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.3288638772
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.4212538443
Short name T739
Test name
Test status
Simulation time 6062759679 ps
CPU time 2.7 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:11 AM PDT 24
Peak memory 201604 kb
Host smart-71f22d79-7aa5-4332-975e-8490840d25c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212538443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.4212538443
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.2749007208
Short name T677
Test name
Test status
Simulation time 2038053345 ps
CPU time 1.92 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:15 AM PDT 24
Peak memory 201592 kb
Host smart-ed080f66-4072-411c-a564-d774c57b969c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749007208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.2749007208
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2666655697
Short name T45
Test name
Test status
Simulation time 3680140994 ps
CPU time 1.67 seconds
Started Jul 02 07:51:08 AM PDT 24
Finished Jul 02 07:51:12 AM PDT 24
Peak memory 201636 kb
Host smart-b9e47540-b0b6-420b-b5c0-10b65da59f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666655697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.2
666655697
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3153380481
Short name T100
Test name
Test status
Simulation time 22332681610 ps
CPU time 60.13 seconds
Started Jul 02 07:51:17 AM PDT 24
Finished Jul 02 07:52:21 AM PDT 24
Peak memory 201804 kb
Host smart-006bc446-343f-487c-8e62-689f8a109fb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153380481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.3153380481
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2225382719
Short name T369
Test name
Test status
Simulation time 170359590667 ps
CPU time 441.82 seconds
Started Jul 02 07:51:18 AM PDT 24
Finished Jul 02 07:58:43 AM PDT 24
Peak memory 201796 kb
Host smart-297d830b-7ef0-426a-bbcd-3a8bd5ff9f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225382719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2225382719
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3781246895
Short name T156
Test name
Test status
Simulation time 782988484507 ps
CPU time 523.36 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:59:55 AM PDT 24
Peak memory 201504 kb
Host smart-09613ca8-7de1-45ef-884d-5f068e462d76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781246895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.3781246895
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2277053134
Short name T12
Test name
Test status
Simulation time 3677170395 ps
CPU time 8.45 seconds
Started Jul 02 07:51:08 AM PDT 24
Finished Jul 02 07:51:19 AM PDT 24
Peak memory 201520 kb
Host smart-335341b9-cb8e-4f94-88d3-3a7d63fb4d41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277053134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.2277053134
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1460289095
Short name T497
Test name
Test status
Simulation time 2613374214 ps
CPU time 7.03 seconds
Started Jul 02 07:51:07 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201572 kb
Host smart-2ab6d291-b4bc-4d9d-8d2d-f19f6b94fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460289095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1460289095
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2932546112
Short name T474
Test name
Test status
Simulation time 2483595383 ps
CPU time 2.14 seconds
Started Jul 02 07:51:13 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 201628 kb
Host smart-84056514-9978-46ca-a68f-439136a6f4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932546112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2932546112
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1610244969
Short name T439
Test name
Test status
Simulation time 2253570963 ps
CPU time 2.31 seconds
Started Jul 02 07:51:08 AM PDT 24
Finished Jul 02 07:51:13 AM PDT 24
Peak memory 201540 kb
Host smart-ddc26b33-929b-4e3a-a648-8d9d75fee392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610244969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1610244969
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3488001834
Short name T628
Test name
Test status
Simulation time 2518934180 ps
CPU time 3.8 seconds
Started Jul 02 07:51:17 AM PDT 24
Finished Jul 02 07:51:25 AM PDT 24
Peak memory 201620 kb
Host smart-0bcd6eee-393d-405b-a932-cf143475befa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488001834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3488001834
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.1201475432
Short name T599
Test name
Test status
Simulation time 2134722524 ps
CPU time 1.78 seconds
Started Jul 02 07:51:23 AM PDT 24
Finished Jul 02 07:51:27 AM PDT 24
Peak memory 201456 kb
Host smart-a99af2be-976c-449d-a4d2-b83297a01a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201475432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.1201475432
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.2594506689
Short name T476
Test name
Test status
Simulation time 14287783724 ps
CPU time 38.5 seconds
Started Jul 02 07:51:07 AM PDT 24
Finished Jul 02 07:51:48 AM PDT 24
Peak memory 201808 kb
Host smart-b12b80bb-9603-45bc-a979-5147fd1d7512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594506689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.2594506689
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3231733000
Short name T277
Test name
Test status
Simulation time 91237122243 ps
CPU time 20.94 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:30 AM PDT 24
Peak memory 210240 kb
Host smart-4be30f3f-dc32-4e60-8bed-b5d13e7cb4dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231733000 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.3231733000
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2039494467
Short name T550
Test name
Test status
Simulation time 5888754912 ps
CPU time 3.14 seconds
Started Jul 02 07:51:25 AM PDT 24
Finished Jul 02 07:51:29 AM PDT 24
Peak memory 201480 kb
Host smart-1e1905e0-9fdf-4203-bd64-6d72ccbcde10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039494467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2039494467
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.2248879307
Short name T640
Test name
Test status
Simulation time 2024096677 ps
CPU time 1.93 seconds
Started Jul 02 07:50:03 AM PDT 24
Finished Jul 02 07:50:09 AM PDT 24
Peak memory 201512 kb
Host smart-cbb1845a-aef7-407c-93cf-82be367020b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248879307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.2248879307
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3657860788
Short name T467
Test name
Test status
Simulation time 3572708925 ps
CPU time 9.64 seconds
Started Jul 02 07:50:01 AM PDT 24
Finished Jul 02 07:50:16 AM PDT 24
Peak memory 201660 kb
Host smart-243b1f2c-d453-49ad-acda-bf29ee80ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657860788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3657860788
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.268532914
Short name T481
Test name
Test status
Simulation time 49232304637 ps
CPU time 20.77 seconds
Started Jul 02 07:49:59 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 201800 kb
Host smart-bcc94ecb-8926-4899-8f63-11bb7a84cd34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268532914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_combo_detect.268532914
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3688288619
Short name T195
Test name
Test status
Simulation time 2420881179 ps
CPU time 2.38 seconds
Started Jul 02 07:50:00 AM PDT 24
Finished Jul 02 07:50:08 AM PDT 24
Peak memory 201552 kb
Host smart-669b6b5a-5fd9-41d3-b12c-a503d45d60ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688288619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3688288619
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2624722337
Short name T484
Test name
Test status
Simulation time 2296330539 ps
CPU time 6.69 seconds
Started Jul 02 07:50:00 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201560 kb
Host smart-92fb75f3-8e89-4baa-b5c1-745b69734415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624722337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2624722337
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1120001512
Short name T586
Test name
Test status
Simulation time 3808762257 ps
CPU time 10.47 seconds
Started Jul 02 07:49:56 AM PDT 24
Finished Jul 02 07:50:15 AM PDT 24
Peak memory 201496 kb
Host smart-7b018bd4-3ba7-4e24-a68d-8dbff42cd910
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120001512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.1120001512
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.4013804456
Short name T704
Test name
Test status
Simulation time 5065333965 ps
CPU time 12.99 seconds
Started Jul 02 07:50:07 AM PDT 24
Finished Jul 02 07:50:22 AM PDT 24
Peak memory 201508 kb
Host smart-897d15b9-d93d-4a12-83ad-556395fe6372
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013804456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.4013804456
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2892807646
Short name T726
Test name
Test status
Simulation time 2622141074 ps
CPU time 2.43 seconds
Started Jul 02 07:49:57 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201600 kb
Host smart-96263705-f388-4f7e-9858-f6c26b5f13aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892807646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2892807646
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1866643804
Short name T420
Test name
Test status
Simulation time 2466454225 ps
CPU time 3.9 seconds
Started Jul 02 07:49:54 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201604 kb
Host smart-fd0635a7-2240-4f27-8f64-b3ad54e2418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866643804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1866643804
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.916881043
Short name T399
Test name
Test status
Simulation time 2095618757 ps
CPU time 1.16 seconds
Started Jul 02 07:50:05 AM PDT 24
Finished Jul 02 07:50:09 AM PDT 24
Peak memory 201440 kb
Host smart-94ca20f4-0ff8-4c56-8ac5-966c06c1b52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916881043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.916881043
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.397568596
Short name T452
Test name
Test status
Simulation time 2521703810 ps
CPU time 4.21 seconds
Started Jul 02 07:50:04 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201508 kb
Host smart-af204fb3-7658-49bf-8ff0-cc53d54fe8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397568596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.397568596
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.1178927421
Short name T314
Test name
Test status
Simulation time 42012050231 ps
CPU time 109.55 seconds
Started Jul 02 07:50:08 AM PDT 24
Finished Jul 02 07:51:59 AM PDT 24
Peak memory 220956 kb
Host smart-2858dd8c-e995-4334-aa75-5c0e6a4c3a8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178927421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1178927421
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.1252904566
Short name T280
Test name
Test status
Simulation time 2114940563 ps
CPU time 5.81 seconds
Started Jul 02 07:50:06 AM PDT 24
Finished Jul 02 07:50:15 AM PDT 24
Peak memory 201416 kb
Host smart-65e4c681-5f16-4689-a171-7ee6182a88a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252904566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.1252904566
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.2271923785
Short name T759
Test name
Test status
Simulation time 7075558161 ps
CPU time 17.55 seconds
Started Jul 02 07:50:01 AM PDT 24
Finished Jul 02 07:50:24 AM PDT 24
Peak memory 201568 kb
Host smart-3fe0f230-37a3-4adf-a8b4-0c0664d7fbe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271923785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.2271923785
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4144771070
Short name T59
Test name
Test status
Simulation time 2622019627 ps
CPU time 1.8 seconds
Started Jul 02 07:50:10 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 201520 kb
Host smart-ee3162a4-12e8-4745-84ae-ea9f7b3faea4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144771070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.4144771070
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.602014524
Short name T576
Test name
Test status
Simulation time 2127398166 ps
CPU time 1.11 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201648 kb
Host smart-9e35409a-a017-4893-a501-b4363aa13387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602014524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_tes
t.602014524
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.894974410
Short name T691
Test name
Test status
Simulation time 3434968010 ps
CPU time 4.69 seconds
Started Jul 02 07:51:11 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 201656 kb
Host smart-31b24bc9-e23d-4723-b695-cb6894af0fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894974410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.894974410
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.74733635
Short name T570
Test name
Test status
Simulation time 100081888699 ps
CPU time 243.57 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:55:16 AM PDT 24
Peak memory 201724 kb
Host smart-91626399-fbd7-4ec3-8f4f-8973256b3fd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74733635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctr
l_combo_detect.74733635
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.163343063
Short name T636
Test name
Test status
Simulation time 4583640548 ps
CPU time 6.2 seconds
Started Jul 02 07:51:15 AM PDT 24
Finished Jul 02 07:51:25 AM PDT 24
Peak memory 201564 kb
Host smart-52fb9107-05a5-4756-b7ca-01a2edbc4f3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163343063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ec_pwr_on_rst.163343063
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1846291247
Short name T741
Test name
Test status
Simulation time 4598120467 ps
CPU time 4.89 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:14 AM PDT 24
Peak memory 201544 kb
Host smart-baf1195a-30f7-4627-8efb-75a5c046073c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846291247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.1846291247
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1088302033
Short name T540
Test name
Test status
Simulation time 2631712708 ps
CPU time 2.59 seconds
Started Jul 02 07:51:18 AM PDT 24
Finished Jul 02 07:51:24 AM PDT 24
Peak memory 201568 kb
Host smart-197fe0e9-2577-4263-b3ec-742cbc31429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088302033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1088302033
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3541763584
Short name T445
Test name
Test status
Simulation time 2450788751 ps
CPU time 7.99 seconds
Started Jul 02 07:51:21 AM PDT 24
Finished Jul 02 07:51:31 AM PDT 24
Peak memory 201304 kb
Host smart-77385299-1e5d-4cba-b560-6a916e8480bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541763584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3541763584
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.2034634238
Short name T589
Test name
Test status
Simulation time 2232414445 ps
CPU time 0.97 seconds
Started Jul 02 07:51:06 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 201544 kb
Host smart-1faf7a1b-057b-46db-af6f-148e29c1369d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034634238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.2034634238
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3856749171
Short name T239
Test name
Test status
Simulation time 2512512393 ps
CPU time 7.28 seconds
Started Jul 02 07:51:20 AM PDT 24
Finished Jul 02 07:51:30 AM PDT 24
Peak memory 201292 kb
Host smart-41f4e974-761c-4fb6-8ef4-f0ea832951c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856749171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3856749171
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.29050732
Short name T553
Test name
Test status
Simulation time 2137770035 ps
CPU time 1.7 seconds
Started Jul 02 07:51:05 AM PDT 24
Finished Jul 02 07:51:10 AM PDT 24
Peak memory 201396 kb
Host smart-30d7cff2-a987-4fd0-9806-36dda1313bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29050732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.29050732
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.1493506109
Short name T209
Test name
Test status
Simulation time 467821993829 ps
CPU time 32.97 seconds
Started Jul 02 07:51:22 AM PDT 24
Finished Jul 02 07:51:57 AM PDT 24
Peak memory 201512 kb
Host smart-7b5d3348-c81d-4598-8430-9ce415289a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493506109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.1493506109
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1018970281
Short name T539
Test name
Test status
Simulation time 8078779641 ps
CPU time 3.16 seconds
Started Jul 02 07:51:11 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201508 kb
Host smart-214315a6-3d45-4fd9-ba41-0c720d73a0bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018970281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.1018970281
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.802348569
Short name T171
Test name
Test status
Simulation time 2014188883 ps
CPU time 6.03 seconds
Started Jul 02 07:51:09 AM PDT 24
Finished Jul 02 07:51:18 AM PDT 24
Peak memory 201484 kb
Host smart-8a047aa8-4407-42e2-b47f-a5709def5862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802348569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_tes
t.802348569
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2372617754
Short name T471
Test name
Test status
Simulation time 3439939096 ps
CPU time 4.97 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:48 AM PDT 24
Peak memory 201728 kb
Host smart-0500f2cd-2ac1-4458-a6cc-1a94d07a053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372617754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.2
372617754
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.2092263784
Short name T127
Test name
Test status
Simulation time 86438099185 ps
CPU time 21.04 seconds
Started Jul 02 07:51:12 AM PDT 24
Finished Jul 02 07:51:34 AM PDT 24
Peak memory 201884 kb
Host smart-0baf8999-a3cb-4a37-9bb2-a70ff35f4032
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092263784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.2092263784
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1560917915
Short name T649
Test name
Test status
Simulation time 68284393649 ps
CPU time 46.35 seconds
Started Jul 02 07:51:13 AM PDT 24
Finished Jul 02 07:52:01 AM PDT 24
Peak memory 201792 kb
Host smart-5932547c-f1c3-47ef-b8d2-1e1cfc2fcc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560917915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.1560917915
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2621726518
Short name T612
Test name
Test status
Simulation time 3085087848 ps
CPU time 4.77 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:51:24 AM PDT 24
Peak memory 201472 kb
Host smart-a1c4188d-78a7-4533-8b5a-e988b74d7ef8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621726518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.2621726518
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.3690459239
Short name T544
Test name
Test status
Simulation time 3180848808 ps
CPU time 1.84 seconds
Started Jul 02 07:51:24 AM PDT 24
Finished Jul 02 07:51:28 AM PDT 24
Peak memory 201492 kb
Host smart-9126c053-9a22-43aa-9ee0-589a651ef162
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690459239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.3690459239
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.4040045280
Short name T585
Test name
Test status
Simulation time 2698345267 ps
CPU time 1.25 seconds
Started Jul 02 07:51:11 AM PDT 24
Finished Jul 02 07:51:14 AM PDT 24
Peak memory 201528 kb
Host smart-36077b58-fa41-4efd-a876-4f832d33ed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040045280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.4040045280
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2064271151
Short name T499
Test name
Test status
Simulation time 2495566234 ps
CPU time 2.01 seconds
Started Jul 02 07:51:13 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 201628 kb
Host smart-d328f633-6963-4c1a-a400-15f39a3abe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064271151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2064271151
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1653431228
Short name T419
Test name
Test status
Simulation time 2088299300 ps
CPU time 1.59 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:44 AM PDT 24
Peak memory 201552 kb
Host smart-2b3d72d5-a69a-42cf-909b-0377e24758b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653431228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1653431228
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.33647427
Short name T64
Test name
Test status
Simulation time 2511166227 ps
CPU time 3.86 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:51:24 AM PDT 24
Peak memory 201504 kb
Host smart-dac53194-55ca-44f1-92c4-441add8ce06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33647427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.33647427
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.2469882474
Short name T773
Test name
Test status
Simulation time 2109739065 ps
CPU time 5.88 seconds
Started Jul 02 07:51:12 AM PDT 24
Finished Jul 02 07:51:19 AM PDT 24
Peak memory 201492 kb
Host smart-55efee16-63db-4650-bf05-4389d85e916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469882474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.2469882474
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1699100911
Short name T733
Test name
Test status
Simulation time 115260762514 ps
CPU time 64.34 seconds
Started Jul 02 07:51:13 AM PDT 24
Finished Jul 02 07:52:19 AM PDT 24
Peak memory 201812 kb
Host smart-5d32f9d0-8a9e-442c-b2f8-949837f0f2de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699100911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1699100911
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1516480534
Short name T693
Test name
Test status
Simulation time 29787331953 ps
CPU time 22.69 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 210052 kb
Host smart-c6221520-2725-4298-9f94-37f6586bbd04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516480534 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1516480534
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3529033315
Short name T133
Test name
Test status
Simulation time 6048377990 ps
CPU time 8.13 seconds
Started Jul 02 07:51:34 AM PDT 24
Finished Jul 02 07:51:46 AM PDT 24
Peak memory 201648 kb
Host smart-9e9da146-0c58-497e-8100-a9321ef21c1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529033315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.3529033315
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.4085057170
Short name T242
Test name
Test status
Simulation time 2010980168 ps
CPU time 5.69 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:51:18 AM PDT 24
Peak memory 201564 kb
Host smart-a0f375b1-9b39-4e10-8e62-6b5ec786cd15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085057170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.4085057170
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2842343681
Short name T579
Test name
Test status
Simulation time 3333842122 ps
CPU time 4.84 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 201512 kb
Host smart-7df5dc6f-61cc-4557-b734-6ede96df59a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842343681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2
842343681
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.1413659446
Short name T335
Test name
Test status
Simulation time 128600611507 ps
CPU time 160.63 seconds
Started Jul 02 07:51:20 AM PDT 24
Finished Jul 02 07:54:03 AM PDT 24
Peak memory 201736 kb
Host smart-5db5932a-83d5-47fd-9469-7abc59a853e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413659446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.1413659446
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3645361301
Short name T584
Test name
Test status
Simulation time 3182192390 ps
CPU time 4.66 seconds
Started Jul 02 07:51:11 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 201868 kb
Host smart-c947558d-efc2-42c9-a377-cc4603d2518e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645361301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.3645361301
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3479234944
Short name T33
Test name
Test status
Simulation time 3750459636 ps
CPU time 6.48 seconds
Started Jul 02 07:51:22 AM PDT 24
Finished Jul 02 07:51:31 AM PDT 24
Peak memory 201844 kb
Host smart-3fa8777f-5af6-40f2-b672-e7ae282b19af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479234944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.3479234944
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3892664915
Short name T648
Test name
Test status
Simulation time 2611809966 ps
CPU time 5.26 seconds
Started Jul 02 07:51:18 AM PDT 24
Finished Jul 02 07:51:27 AM PDT 24
Peak memory 201504 kb
Host smart-925511b2-e62b-4ae5-b6b5-191fbb2035e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892664915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3892664915
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.2685743684
Short name T125
Test name
Test status
Simulation time 2484091099 ps
CPU time 8.1 seconds
Started Jul 02 07:51:24 AM PDT 24
Finished Jul 02 07:51:34 AM PDT 24
Peak memory 201620 kb
Host smart-7ab9ce7d-24d5-4144-a6f0-d113cef05062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685743684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.2685743684
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.2074918904
Short name T729
Test name
Test status
Simulation time 2215056886 ps
CPU time 2.24 seconds
Started Jul 02 07:51:09 AM PDT 24
Finished Jul 02 07:51:14 AM PDT 24
Peak memory 201460 kb
Host smart-754939a8-f756-4def-a9d7-b4dfea180f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074918904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.2074918904
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.650359900
Short name T407
Test name
Test status
Simulation time 2549995301 ps
CPU time 1.64 seconds
Started Jul 02 07:51:27 AM PDT 24
Finished Jul 02 07:51:30 AM PDT 24
Peak memory 201492 kb
Host smart-22fbe319-1d19-4102-91ae-f13202b11b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650359900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.650359900
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.236276438
Short name T241
Test name
Test status
Simulation time 2159021366 ps
CPU time 1.42 seconds
Started Jul 02 07:51:23 AM PDT 24
Finished Jul 02 07:51:26 AM PDT 24
Peak memory 201488 kb
Host smart-3310074e-a8ca-4753-add6-70feae22c66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236276438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.236276438
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.3653594241
Short name T657
Test name
Test status
Simulation time 488337280890 ps
CPU time 164.43 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:53:56 AM PDT 24
Peak memory 201656 kb
Host smart-4bba80d1-b96c-4de9-b73b-de870d5ddd9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653594241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.3653594241
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1475041173
Short name T326
Test name
Test status
Simulation time 23596419700 ps
CPU time 61.11 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:52:30 AM PDT 24
Peak memory 210196 kb
Host smart-83c65122-643c-40b5-a9f9-a3ef852fc4f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475041173 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1475041173
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2499628575
Short name T753
Test name
Test status
Simulation time 7006388997 ps
CPU time 4.41 seconds
Started Jul 02 07:51:08 AM PDT 24
Finished Jul 02 07:51:15 AM PDT 24
Peak memory 201492 kb
Host smart-870cbf56-85da-4e88-af9b-2d7fff2d2e84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499628575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.2499628575
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.3745813286
Short name T537
Test name
Test status
Simulation time 2014455667 ps
CPU time 5.84 seconds
Started Jul 02 07:51:17 AM PDT 24
Finished Jul 02 07:51:26 AM PDT 24
Peak memory 201604 kb
Host smart-bdfcfe9a-8817-4035-96f3-66c3abfc2bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745813286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.3745813286
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2213416119
Short name T556
Test name
Test status
Simulation time 3494560798 ps
CPU time 2.86 seconds
Started Jul 02 07:51:09 AM PDT 24
Finished Jul 02 07:51:14 AM PDT 24
Peak memory 201588 kb
Host smart-0ee20108-7445-477b-a0ba-433770987e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213416119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2
213416119
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.2610360387
Short name T358
Test name
Test status
Simulation time 113442909367 ps
CPU time 29.57 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:59 AM PDT 24
Peak memory 201764 kb
Host smart-95963dd8-b96c-4198-b0d4-e4e59ebe54a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610360387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.2610360387
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1614292415
Short name T658
Test name
Test status
Simulation time 92140287340 ps
CPU time 216.87 seconds
Started Jul 02 07:51:32 AM PDT 24
Finished Jul 02 07:55:12 AM PDT 24
Peak memory 201744 kb
Host smart-535d48d1-8a94-4243-8d0e-9a1c51ef4268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614292415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.1614292415
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3703121523
Short name T676
Test name
Test status
Simulation time 4044261495 ps
CPU time 5.88 seconds
Started Jul 02 07:51:13 AM PDT 24
Finished Jul 02 07:51:21 AM PDT 24
Peak memory 201604 kb
Host smart-c5abaaea-1261-4aad-91a4-ceff53cb4215
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703121523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.3703121523
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.9495726
Short name T682
Test name
Test status
Simulation time 2612897835 ps
CPU time 7.31 seconds
Started Jul 02 07:51:10 AM PDT 24
Finished Jul 02 07:51:19 AM PDT 24
Peak memory 201568 kb
Host smart-02310285-fd49-44e4-8b1d-4dbfcd9376a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9495726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.9495726
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.51626769
Short name T641
Test name
Test status
Simulation time 2478075847 ps
CPU time 2.19 seconds
Started Jul 02 07:51:12 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201568 kb
Host smart-6423b3a8-bcb9-4769-b82f-4eb89f6f2fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51626769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.51626769
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3819157081
Short name T483
Test name
Test status
Simulation time 2100942976 ps
CPU time 5.88 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 201364 kb
Host smart-c6e0c90b-b5fa-4c1c-a4bc-a130697efe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819157081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3819157081
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2654070300
Short name T412
Test name
Test status
Simulation time 2512399864 ps
CPU time 6.74 seconds
Started Jul 02 07:51:09 AM PDT 24
Finished Jul 02 07:51:18 AM PDT 24
Peak memory 201536 kb
Host smart-683cb92f-cb3e-4c45-856e-70b916fd8b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654070300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.2654070300
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.2382183867
Short name T405
Test name
Test status
Simulation time 2118275637 ps
CPU time 3.38 seconds
Started Jul 02 07:51:11 AM PDT 24
Finished Jul 02 07:51:16 AM PDT 24
Peak memory 201736 kb
Host smart-5deec5e9-4a89-4f8e-9d3f-d784b10380ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382183867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.2382183867
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.1234981942
Short name T276
Test name
Test status
Simulation time 905845091022 ps
CPU time 35.96 seconds
Started Jul 02 07:51:15 AM PDT 24
Finished Jul 02 07:51:56 AM PDT 24
Peak memory 201864 kb
Host smart-c5fe363a-d3e0-421c-9347-83cd167bee25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234981942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.1234981942
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1708161718
Short name T533
Test name
Test status
Simulation time 4903273779547 ps
CPU time 279 seconds
Started Jul 02 07:51:12 AM PDT 24
Finished Jul 02 07:55:54 AM PDT 24
Peak memory 201540 kb
Host smart-f4594ab7-27e1-496b-bdcb-594c0e3afb0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708161718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.1708161718
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.2473054147
Short name T463
Test name
Test status
Simulation time 2013134176 ps
CPU time 5.52 seconds
Started Jul 02 07:51:15 AM PDT 24
Finished Jul 02 07:51:23 AM PDT 24
Peak memory 201540 kb
Host smart-53b4f723-5be3-465b-bd37-3d664b72e80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473054147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.2473054147
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3387050335
Short name T423
Test name
Test status
Simulation time 3403885822 ps
CPU time 1.11 seconds
Started Jul 02 07:51:15 AM PDT 24
Finished Jul 02 07:51:20 AM PDT 24
Peak memory 201684 kb
Host smart-7634a1fc-e5c0-447a-8b85-ef63a347b10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387050335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.3
387050335
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.509017726
Short name T77
Test name
Test status
Simulation time 85488215323 ps
CPU time 114.62 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:53:14 AM PDT 24
Peak memory 201768 kb
Host smart-9a80b0be-4222-4e32-836d-4e258e34297a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509017726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_combo_detect.509017726
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.4063515168
Short name T673
Test name
Test status
Simulation time 57801159373 ps
CPU time 76.37 seconds
Started Jul 02 07:51:15 AM PDT 24
Finished Jul 02 07:52:35 AM PDT 24
Peak memory 201756 kb
Host smart-8116d687-4ce5-41d8-948b-0345e5557d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063515168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.4063515168
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2662300778
Short name T778
Test name
Test status
Simulation time 4584264405 ps
CPU time 11.81 seconds
Started Jul 02 07:51:32 AM PDT 24
Finished Jul 02 07:51:47 AM PDT 24
Peak memory 201612 kb
Host smart-a88f36fe-07da-4662-9a9c-1b5b614eee15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662300778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.2662300778
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1974536160
Short name T221
Test name
Test status
Simulation time 3496598510 ps
CPU time 2.08 seconds
Started Jul 02 07:51:26 AM PDT 24
Finished Jul 02 07:51:29 AM PDT 24
Peak memory 201504 kb
Host smart-6d0fa6f9-8f02-4bc0-9edd-55f39c1e7686
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974536160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1974536160
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.520516337
Short name T777
Test name
Test status
Simulation time 2613365028 ps
CPU time 7.5 seconds
Started Jul 02 07:51:14 AM PDT 24
Finished Jul 02 07:51:23 AM PDT 24
Peak memory 201604 kb
Host smart-04281f11-a762-479a-8db4-fa45cd2e9e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520516337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.520516337
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2740114143
Short name T594
Test name
Test status
Simulation time 2452579063 ps
CPU time 7.28 seconds
Started Jul 02 07:51:24 AM PDT 24
Finished Jul 02 07:51:33 AM PDT 24
Peak memory 201528 kb
Host smart-862f6e29-3414-4aac-ab1e-eb582554407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740114143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2740114143
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.1880085251
Short name T282
Test name
Test status
Simulation time 2066922592 ps
CPU time 1.89 seconds
Started Jul 02 07:51:24 AM PDT 24
Finished Jul 02 07:51:27 AM PDT 24
Peak memory 201308 kb
Host smart-55efca0b-92b6-4460-80dd-06a0efa0db2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880085251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.1880085251
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1407899349
Short name T284
Test name
Test status
Simulation time 2511131467 ps
CPU time 6.79 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:36 AM PDT 24
Peak memory 201552 kb
Host smart-e52701fb-0cd5-406c-916f-06d945e39ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407899349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.1407899349
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.286257836
Short name T547
Test name
Test status
Simulation time 2165034550 ps
CPU time 1.42 seconds
Started Jul 02 07:51:15 AM PDT 24
Finished Jul 02 07:51:18 AM PDT 24
Peak memory 201608 kb
Host smart-1ca80c62-1f4a-4dcc-a332-95ce3147927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286257836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.286257836
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.2574914114
Short name T63
Test name
Test status
Simulation time 7063448051 ps
CPU time 20.67 seconds
Started Jul 02 07:51:27 AM PDT 24
Finished Jul 02 07:51:49 AM PDT 24
Peak memory 201556 kb
Host smart-d7c0f8b6-ea81-4875-9e6e-9a927b298ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574914114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.2574914114
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3146362079
Short name T148
Test name
Test status
Simulation time 3472061348 ps
CPU time 6.19 seconds
Started Jul 02 07:51:15 AM PDT 24
Finished Jul 02 07:51:25 AM PDT 24
Peak memory 201476 kb
Host smart-8f13f8c8-0d64-42ae-a1c3-0c927fb08c33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146362079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.3146362079
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.663843110
Short name T214
Test name
Test status
Simulation time 2036227846 ps
CPU time 1.51 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:30 AM PDT 24
Peak memory 201500 kb
Host smart-5168ecd3-f478-499c-97ef-f214ec3b82a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663843110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_tes
t.663843110
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2093929278
Short name T448
Test name
Test status
Simulation time 3423431552 ps
CPU time 9.76 seconds
Started Jul 02 07:51:14 AM PDT 24
Finished Jul 02 07:51:25 AM PDT 24
Peak memory 201660 kb
Host smart-7d632fbd-49fb-47ec-bbf0-34a785fe9a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093929278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2
093929278
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.1247648933
Short name T289
Test name
Test status
Simulation time 90074530723 ps
CPU time 213.35 seconds
Started Jul 02 07:51:14 AM PDT 24
Finished Jul 02 07:54:49 AM PDT 24
Peak memory 201804 kb
Host smart-72653af8-df9f-4bcd-9ca0-476b008689e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247648933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.1247648933
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1197444248
Short name T13
Test name
Test status
Simulation time 28833836084 ps
CPU time 72.49 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:52:33 AM PDT 24
Peak memory 201684 kb
Host smart-7d014323-42b9-430d-8de0-5eb32d49b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197444248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.1197444248
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.588344008
Short name T218
Test name
Test status
Simulation time 3064083818 ps
CPU time 2.41 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:51:22 AM PDT 24
Peak memory 201564 kb
Host smart-88b30f08-22fd-4fb4-a53b-f034fce73fdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588344008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ec_pwr_on_rst.588344008
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.1798284314
Short name T199
Test name
Test status
Simulation time 4201832978 ps
CPU time 6.67 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:51:27 AM PDT 24
Peak memory 201624 kb
Host smart-d8aede7a-fd47-4eb4-9a52-b9fded5fd0e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798284314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.1798284314
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2701433623
Short name T296
Test name
Test status
Simulation time 2608983139 ps
CPU time 6.93 seconds
Started Jul 02 07:51:16 AM PDT 24
Finished Jul 02 07:51:27 AM PDT 24
Peak memory 201424 kb
Host smart-3f595671-fd43-4424-acbd-37f2b7719307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701433623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2701433623
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1989333779
Short name T518
Test name
Test status
Simulation time 2451368767 ps
CPU time 6.41 seconds
Started Jul 02 07:51:15 AM PDT 24
Finished Jul 02 07:51:23 AM PDT 24
Peak memory 201524 kb
Host smart-e9ff7430-c361-4964-a031-1d042af68c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989333779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1989333779
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1301859564
Short name T512
Test name
Test status
Simulation time 2154161953 ps
CPU time 1.96 seconds
Started Jul 02 07:51:30 AM PDT 24
Finished Jul 02 07:51:36 AM PDT 24
Peak memory 201548 kb
Host smart-e5fd5874-afc6-45da-bf84-100cb7b50b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301859564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1301859564
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.308911253
Short name T493
Test name
Test status
Simulation time 2509825396 ps
CPU time 6.82 seconds
Started Jul 02 07:51:24 AM PDT 24
Finished Jul 02 07:51:33 AM PDT 24
Peak memory 201620 kb
Host smart-084658dd-fcd2-40e3-a036-5f6701d72af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308911253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.308911253
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.1960374559
Short name T191
Test name
Test status
Simulation time 2120427158 ps
CPU time 3.01 seconds
Started Jul 02 07:51:27 AM PDT 24
Finished Jul 02 07:51:31 AM PDT 24
Peak memory 201388 kb
Host smart-8ca357e4-84ab-4fc8-b1c6-261859b45d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960374559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.1960374559
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.1182942513
Short name T85
Test name
Test status
Simulation time 11693964584 ps
CPU time 7.42 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:51:43 AM PDT 24
Peak memory 201564 kb
Host smart-2c736aa0-ccf8-442e-8c2f-a50896be5a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182942513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.1182942513
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3273943323
Short name T325
Test name
Test status
Simulation time 193557116982 ps
CPU time 124.48 seconds
Started Jul 02 07:51:31 AM PDT 24
Finished Jul 02 07:53:39 AM PDT 24
Peak memory 210192 kb
Host smart-5b2ffb19-8b7b-45c2-bb67-026c39486303
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273943323 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.3273943323
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3859273858
Short name T56
Test name
Test status
Simulation time 713930951025 ps
CPU time 35.07 seconds
Started Jul 02 07:51:34 AM PDT 24
Finished Jul 02 07:52:13 AM PDT 24
Peak memory 201512 kb
Host smart-3b04a396-10c8-4863-98fa-06c119dbd122
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859273858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3859273858
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.1546809619
Short name T408
Test name
Test status
Simulation time 2089937786 ps
CPU time 0.99 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:44 AM PDT 24
Peak memory 201640 kb
Host smart-705ccea4-cb4c-42f1-8e7c-25d77de6c6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546809619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.1546809619
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1958940650
Short name T479
Test name
Test status
Simulation time 3017562278 ps
CPU time 8.9 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:38 AM PDT 24
Peak memory 201592 kb
Host smart-2b79f3b1-723a-4fb9-8e20-91429b813b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958940650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1
958940650
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.794317911
Short name T606
Test name
Test status
Simulation time 150470613472 ps
CPU time 100.43 seconds
Started Jul 02 07:51:36 AM PDT 24
Finished Jul 02 07:53:21 AM PDT 24
Peak memory 201796 kb
Host smart-73d8b04e-1cce-4c61-b49e-fe6cc20e92b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794317911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.794317911
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3515423271
Short name T391
Test name
Test status
Simulation time 28581840270 ps
CPU time 74.13 seconds
Started Jul 02 07:51:18 AM PDT 24
Finished Jul 02 07:52:36 AM PDT 24
Peak memory 201764 kb
Host smart-4e50a35f-a639-4110-9b19-7c17899cab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515423271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.3515423271
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2477050821
Short name T416
Test name
Test status
Simulation time 3544830135 ps
CPU time 2.93 seconds
Started Jul 02 07:51:32 AM PDT 24
Finished Jul 02 07:51:38 AM PDT 24
Peak memory 201472 kb
Host smart-a415a615-ef3e-40ed-98c6-cdb967737a07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477050821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.2477050821
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2444668131
Short name T440
Test name
Test status
Simulation time 2665728592 ps
CPU time 3.99 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:34 AM PDT 24
Peak memory 201492 kb
Host smart-e824beff-40b4-4019-80cd-1bc0f14fabcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444668131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.2444668131
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1886898556
Short name T781
Test name
Test status
Simulation time 2632854924 ps
CPU time 2.31 seconds
Started Jul 02 07:51:17 AM PDT 24
Finished Jul 02 07:51:23 AM PDT 24
Peak memory 201588 kb
Host smart-2bfc81ed-829a-4766-b75b-1ed4bbbc90a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886898556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1886898556
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3978289415
Short name T626
Test name
Test status
Simulation time 2477621094 ps
CPU time 6.53 seconds
Started Jul 02 07:51:17 AM PDT 24
Finished Jul 02 07:51:27 AM PDT 24
Peak memory 201552 kb
Host smart-bf52070e-144a-4d95-a3ec-3578ea00fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978289415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3978289415
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1882101896
Short name T454
Test name
Test status
Simulation time 2245686029 ps
CPU time 2.12 seconds
Started Jul 02 07:51:21 AM PDT 24
Finished Jul 02 07:51:25 AM PDT 24
Peak memory 201628 kb
Host smart-10fd22ad-a1fa-4990-9662-726048d759e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882101896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1882101896
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.392964020
Short name T438
Test name
Test status
Simulation time 2516428149 ps
CPU time 3.81 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:51:41 AM PDT 24
Peak memory 201508 kb
Host smart-3db24fb7-8b84-4748-80c2-db86cfb336b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392964020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.392964020
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.2698517531
Short name T701
Test name
Test status
Simulation time 2114723857 ps
CPU time 5.77 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:37 AM PDT 24
Peak memory 201396 kb
Host smart-5b9021a7-f1eb-4181-bf99-80151fe19159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698517531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.2698517531
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.3619597699
Short name T748
Test name
Test status
Simulation time 13860846612 ps
CPU time 37.28 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:52:14 AM PDT 24
Peak memory 202064 kb
Host smart-cc77077a-72d5-4be1-81a3-3234afc155fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619597699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.3619597699
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.747239609
Short name T755
Test name
Test status
Simulation time 3626841355 ps
CPU time 2.5 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:42 AM PDT 24
Peak memory 201600 kb
Host smart-d6302c1b-ae9b-4717-b8b4-21c03b40e045
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747239609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ultra_low_pwr.747239609
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.3761889106
Short name T293
Test name
Test status
Simulation time 2063000083 ps
CPU time 1.26 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:41 AM PDT 24
Peak memory 201520 kb
Host smart-33eef654-6bbf-460c-a910-988697133bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761889106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.3761889106
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3720554734
Short name T25
Test name
Test status
Simulation time 3166538241 ps
CPU time 2.54 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:51:40 AM PDT 24
Peak memory 201576 kb
Host smart-1b5d0826-9ae5-427b-86d1-5e6a35866ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720554734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.3
720554734
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.1666781771
Short name T175
Test name
Test status
Simulation time 77066250776 ps
CPU time 25.62 seconds
Started Jul 02 07:51:23 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201780 kb
Host smart-fc6dbac9-cfa4-4e0e-ae5a-3b671eb564b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666781771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.1666781771
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2210846309
Short name T769
Test name
Test status
Simulation time 3639615863 ps
CPU time 2.72 seconds
Started Jul 02 07:51:26 AM PDT 24
Finished Jul 02 07:51:29 AM PDT 24
Peak memory 201872 kb
Host smart-dde6010f-99b5-4cbd-9102-2227fb766436
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210846309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2210846309
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.4265154672
Short name T234
Test name
Test status
Simulation time 2414772403 ps
CPU time 3.69 seconds
Started Jul 02 07:51:30 AM PDT 24
Finished Jul 02 07:51:37 AM PDT 24
Peak memory 201524 kb
Host smart-d59f0739-9fc6-46ac-b9d4-29ce6ae380ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265154672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.4265154672
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2730435097
Short name T622
Test name
Test status
Simulation time 2611184442 ps
CPU time 7.28 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:47 AM PDT 24
Peak memory 201624 kb
Host smart-249e13d9-4792-40ce-8207-458664db9c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730435097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.2730435097
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.3051134402
Short name T736
Test name
Test status
Simulation time 2467399522 ps
CPU time 6.91 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:49 AM PDT 24
Peak memory 201620 kb
Host smart-20e846c8-ebe9-4674-8720-67c9954bdc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051134402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.3051134402
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3451759772
Short name T700
Test name
Test status
Simulation time 2256083746 ps
CPU time 3.6 seconds
Started Jul 02 07:51:24 AM PDT 24
Finished Jul 02 07:51:29 AM PDT 24
Peak memory 201460 kb
Host smart-08020d0b-f6f1-4ffc-94fe-cefb176fd6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451759772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3451759772
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3125087897
Short name T558
Test name
Test status
Simulation time 2509988733 ps
CPU time 6.7 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:51:43 AM PDT 24
Peak memory 201528 kb
Host smart-26c2b663-1b58-4042-a80f-200e58f0d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125087897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3125087897
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1868689446
Short name T643
Test name
Test status
Simulation time 2131670172 ps
CPU time 1.8 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:31 AM PDT 24
Peak memory 201400 kb
Host smart-aaa749f7-2f4e-48a3-8418-aa2ba9cc0eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868689446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1868689446
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.3915804454
Short name T674
Test name
Test status
Simulation time 10007789411 ps
CPU time 2.99 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 201600 kb
Host smart-625d7d02-12ae-4a3f-a295-b6e105b958bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915804454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.3915804454
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1452570716
Short name T109
Test name
Test status
Simulation time 44554134507 ps
CPU time 106.44 seconds
Started Jul 02 07:51:25 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 210152 kb
Host smart-edf32b27-b6d7-4556-857e-04c4d7dd6dde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452570716 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1452570716
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4041103944
Short name T146
Test name
Test status
Simulation time 5185554374 ps
CPU time 7.41 seconds
Started Jul 02 07:51:22 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201512 kb
Host smart-b2e34a2e-20f0-4a23-92c6-bc0a2c0ea025
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041103944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.4041103944
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.60411683
Short name T255
Test name
Test status
Simulation time 2074467736 ps
CPU time 1.1 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201592 kb
Host smart-d565c8c3-74b0-471a-959f-b28952789a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60411683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test
.60411683
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.4210579987
Short name T258
Test name
Test status
Simulation time 3809050407 ps
CPU time 10.42 seconds
Started Jul 02 07:51:37 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201608 kb
Host smart-cb23059b-7517-4216-b26c-8f7d99906dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210579987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.4
210579987
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2499799349
Short name T360
Test name
Test status
Simulation time 76123281302 ps
CPU time 92.6 seconds
Started Jul 02 07:51:40 AM PDT 24
Finished Jul 02 07:53:16 AM PDT 24
Peak memory 201700 kb
Host smart-cc6e5a2e-f201-4825-add8-36af1e6cfcf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499799349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2499799349
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.737123874
Short name T723
Test name
Test status
Simulation time 34201567075 ps
CPU time 21.48 seconds
Started Jul 02 07:51:32 AM PDT 24
Finished Jul 02 07:51:57 AM PDT 24
Peak memory 201792 kb
Host smart-2c169509-d076-4f4c-adc3-8c461e33f60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737123874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_wi
th_pre_cond.737123874
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1549957510
Short name T564
Test name
Test status
Simulation time 3684301382 ps
CPU time 3.1 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:43 AM PDT 24
Peak memory 201872 kb
Host smart-b8637ce5-99b5-479b-8e63-fa49926925d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549957510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.1549957510
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2905022173
Short name T188
Test name
Test status
Simulation time 3164987310 ps
CPU time 8.65 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:49 AM PDT 24
Peak memory 201592 kb
Host smart-28eacd82-ae1e-45a3-a59a-ccc54bf1c3b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905022173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.2905022173
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3128879864
Short name T172
Test name
Test status
Simulation time 2627478231 ps
CPU time 2.34 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:34 AM PDT 24
Peak memory 201496 kb
Host smart-fbddd502-8d64-4222-80b7-e8c88168a844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128879864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3128879864
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3708111265
Short name T62
Test name
Test status
Simulation time 2460134662 ps
CPU time 6.92 seconds
Started Jul 02 07:51:26 AM PDT 24
Finished Jul 02 07:51:34 AM PDT 24
Peak memory 201568 kb
Host smart-941d36d6-e9ad-42bb-8268-3d7318627d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708111265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3708111265
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.934612160
Short name T713
Test name
Test status
Simulation time 2055048722 ps
CPU time 3.33 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:46 AM PDT 24
Peak memory 201556 kb
Host smart-5f41af63-9588-4ac8-8e44-c70b75898898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934612160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.934612160
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.2995640244
Short name T776
Test name
Test status
Simulation time 2512228660 ps
CPU time 7.24 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:46 AM PDT 24
Peak memory 201512 kb
Host smart-0a3d0a0e-30be-45aa-b8bb-c2b377485c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995640244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.2995640244
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.326889141
Short name T633
Test name
Test status
Simulation time 2107190310 ps
CPU time 6.03 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:37 AM PDT 24
Peak memory 201460 kb
Host smart-f2577cb0-4308-4af0-ac1a-1b62fd8000cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326889141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.326889141
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.2505948440
Short name T740
Test name
Test status
Simulation time 9617737505 ps
CPU time 20.2 seconds
Started Jul 02 07:51:30 AM PDT 24
Finished Jul 02 07:51:53 AM PDT 24
Peak memory 201516 kb
Host smart-8c055b1c-7676-4160-9f3e-22c7d200bd8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505948440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.2505948440
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1289298478
Short name T318
Test name
Test status
Simulation time 17320394719 ps
CPU time 46.04 seconds
Started Jul 02 07:51:38 AM PDT 24
Finished Jul 02 07:52:28 AM PDT 24
Peak memory 217952 kb
Host smart-123a4422-9319-40f9-b7ea-4e02567f8836
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289298478 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.1289298478
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.532816940
Short name T613
Test name
Test status
Simulation time 2025279493 ps
CPU time 1.98 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:51:39 AM PDT 24
Peak memory 201520 kb
Host smart-b8f6271c-234e-4331-9aa4-6519cb6fafff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532816940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_tes
t.532816940
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3485288962
Short name T563
Test name
Test status
Simulation time 3537570963 ps
CPU time 9.81 seconds
Started Jul 02 07:51:36 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201608 kb
Host smart-7ad388b1-efba-4e7a-8d84-f8381b5f444c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485288962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.3
485288962
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1625222713
Short name T591
Test name
Test status
Simulation time 190752567554 ps
CPU time 259.99 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:55:52 AM PDT 24
Peak memory 201844 kb
Host smart-997cc423-c06e-4367-bc52-ae993d3b7b11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625222713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1625222713
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1633796045
Short name T772
Test name
Test status
Simulation time 3112743931 ps
CPU time 2.43 seconds
Started Jul 02 07:51:30 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 201496 kb
Host smart-29616ca4-4b0c-47a1-bc57-5ad609694567
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633796045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.1633796045
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.1291331340
Short name T252
Test name
Test status
Simulation time 3097277678 ps
CPU time 1.39 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201564 kb
Host smart-7517370b-7eef-4732-b8d9-7f4522fbce51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291331340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.1291331340
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.892611760
Short name T206
Test name
Test status
Simulation time 2623961073 ps
CPU time 2.29 seconds
Started Jul 02 07:51:34 AM PDT 24
Finished Jul 02 07:51:41 AM PDT 24
Peak memory 201596 kb
Host smart-afc4326f-e4e9-45c9-9c2e-b1915b5a791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892611760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.892611760
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.1012863080
Short name T426
Test name
Test status
Simulation time 2469638184 ps
CPU time 2.16 seconds
Started Jul 02 07:51:31 AM PDT 24
Finished Jul 02 07:51:36 AM PDT 24
Peak memory 201600 kb
Host smart-45da3e54-b8cc-452d-8832-ea4e1c5cc1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012863080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.1012863080
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.1401410979
Short name T116
Test name
Test status
Simulation time 2023889349 ps
CPU time 5.91 seconds
Started Jul 02 07:51:32 AM PDT 24
Finished Jul 02 07:51:41 AM PDT 24
Peak memory 201376 kb
Host smart-3e87c929-e06a-48af-aa3c-591bb979038e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401410979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.1401410979
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1023903881
Short name T321
Test name
Test status
Simulation time 2538736432 ps
CPU time 2.35 seconds
Started Jul 02 07:51:31 AM PDT 24
Finished Jul 02 07:51:37 AM PDT 24
Peak memory 201624 kb
Host smart-bb564d32-7243-4944-8672-349766824cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023903881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1023903881
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.4125092045
Short name T528
Test name
Test status
Simulation time 2136052014 ps
CPU time 2.06 seconds
Started Jul 02 07:51:31 AM PDT 24
Finished Jul 02 07:51:36 AM PDT 24
Peak memory 201368 kb
Host smart-9ef481b6-b5d2-40aa-9dd6-e3e77cc58177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125092045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.4125092045
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.925173282
Short name T58
Test name
Test status
Simulation time 857816611416 ps
CPU time 269.95 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:56:00 AM PDT 24
Peak memory 201660 kb
Host smart-340fbad4-cae4-4278-a859-b28313d914ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925173282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_st
ress_all.925173282
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2616885167
Short name T330
Test name
Test status
Simulation time 4161475430 ps
CPU time 3.81 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:36 AM PDT 24
Peak memory 201548 kb
Host smart-5a9db647-5eb3-44f7-b81e-f4efbd4fdc1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616885167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.2616885167
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.3806605233
Short name T758
Test name
Test status
Simulation time 2011790076 ps
CPU time 5.62 seconds
Started Jul 02 07:50:08 AM PDT 24
Finished Jul 02 07:50:16 AM PDT 24
Peak memory 201616 kb
Host smart-0ff5d1ed-98d2-4476-bf5b-f6b677a4304d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806605233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.3806605233
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.1595180534
Short name T233
Test name
Test status
Simulation time 206165444394 ps
CPU time 535.69 seconds
Started Jul 02 07:50:07 AM PDT 24
Finished Jul 02 07:59:05 AM PDT 24
Peak memory 201644 kb
Host smart-60ad0787-9bfb-4014-8b1c-44733ffdf149
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595180534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.1595180534
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2372476617
Short name T707
Test name
Test status
Simulation time 2240981589 ps
CPU time 2.77 seconds
Started Jul 02 07:49:56 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201516 kb
Host smart-84b9f33f-6556-48dc-b5dd-9f40ddd342db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372476617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2372476617
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.794502380
Short name T571
Test name
Test status
Simulation time 2525681433 ps
CPU time 1.82 seconds
Started Jul 02 07:50:10 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 201508 kb
Host smart-c91c9703-2e8c-4c99-bb61-bbf2a966ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794502380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.794502380
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1441904368
Short name T10
Test name
Test status
Simulation time 73565498117 ps
CPU time 60.92 seconds
Started Jul 02 07:50:10 AM PDT 24
Finished Jul 02 07:51:12 AM PDT 24
Peak memory 201824 kb
Host smart-f84dd95b-5f26-4a2e-a94b-4c1feb83f96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441904368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.1441904368
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.96519588
Short name T717
Test name
Test status
Simulation time 3378763143 ps
CPU time 4.73 seconds
Started Jul 02 07:50:06 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 201580 kb
Host smart-d9c04c28-fafc-467d-b4db-3ec6f47dc43e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96519588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_ec_pwr_on_rst.96519588
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1685769358
Short name T577
Test name
Test status
Simulation time 3083086422 ps
CPU time 1.47 seconds
Started Jul 02 07:50:10 AM PDT 24
Finished Jul 02 07:50:13 AM PDT 24
Peak memory 201440 kb
Host smart-0dd8218b-6efc-4c75-a2e6-49814d5dee39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685769358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.1685769358
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2816465339
Short name T162
Test name
Test status
Simulation time 2622991769 ps
CPU time 2.79 seconds
Started Jul 02 07:50:09 AM PDT 24
Finished Jul 02 07:50:14 AM PDT 24
Peak memory 201512 kb
Host smart-7ddf4faf-d0f4-4172-9b5e-be661bc7cb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816465339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2816465339
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.604120308
Short name T144
Test name
Test status
Simulation time 2456887812 ps
CPU time 3.41 seconds
Started Jul 02 07:50:04 AM PDT 24
Finished Jul 02 07:50:11 AM PDT 24
Peak memory 201244 kb
Host smart-bdd68b62-1c8b-4d7c-a37c-dbe0d46570f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604120308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.604120308
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1286284979
Short name T611
Test name
Test status
Simulation time 2228528957 ps
CPU time 1.89 seconds
Started Jul 02 07:50:08 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201540 kb
Host smart-3643f7af-1e40-431c-9545-795ca2591265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286284979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1286284979
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.482834685
Short name T630
Test name
Test status
Simulation time 2532110255 ps
CPU time 2.2 seconds
Started Jul 02 07:50:04 AM PDT 24
Finished Jul 02 07:50:10 AM PDT 24
Peak memory 201844 kb
Host smart-87f97d11-ee13-4ece-975d-62d446b04846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482834685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.482834685
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.279444767
Short name T238
Test name
Test status
Simulation time 22073078600 ps
CPU time 15.62 seconds
Started Jul 02 07:50:05 AM PDT 24
Finished Jul 02 07:50:24 AM PDT 24
Peak memory 220836 kb
Host smart-d5c92fd3-7f57-42ad-9b6a-36e6330aaf84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279444767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.279444767
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.4118655976
Short name T527
Test name
Test status
Simulation time 2140544861 ps
CPU time 1.78 seconds
Started Jul 02 07:50:00 AM PDT 24
Finished Jul 02 07:50:07 AM PDT 24
Peak memory 201448 kb
Host smart-0ed703ca-feb2-4d9d-9c7b-3b57225f8fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118655976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.4118655976
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.2506174809
Short name T757
Test name
Test status
Simulation time 14806457988 ps
CPU time 36.67 seconds
Started Jul 02 07:50:08 AM PDT 24
Finished Jul 02 07:50:47 AM PDT 24
Peak memory 201644 kb
Host smart-9dd1a940-2310-442b-b5e2-22143eaa5e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506174809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.2506174809
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3602776435
Short name T782
Test name
Test status
Simulation time 611428539601 ps
CPU time 40.58 seconds
Started Jul 02 07:50:12 AM PDT 24
Finished Jul 02 07:50:54 AM PDT 24
Peak memory 201528 kb
Host smart-43df10d6-ede5-4276-b770-254fb3c24169
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602776435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.3602776435
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.2069012584
Short name T710
Test name
Test status
Simulation time 2030063001 ps
CPU time 2.19 seconds
Started Jul 02 07:51:37 AM PDT 24
Finished Jul 02 07:51:43 AM PDT 24
Peak memory 201532 kb
Host smart-bdeb53aa-397b-409d-a7bf-32e32bf6572d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069012584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.2069012584
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3112069664
Short name T435
Test name
Test status
Simulation time 3348042134 ps
CPU time 4.13 seconds
Started Jul 02 07:51:44 AM PDT 24
Finished Jul 02 07:51:50 AM PDT 24
Peak memory 201588 kb
Host smart-266989d7-99d2-46af-9449-22b240dd61a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112069664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
112069664
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.826378484
Short name T766
Test name
Test status
Simulation time 182323405489 ps
CPU time 475.98 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:59:35 AM PDT 24
Peak memory 201764 kb
Host smart-c2310295-7e41-423a-8acf-24e5a0436bb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826378484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_combo_detect.826378484
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2916400613
Short name T111
Test name
Test status
Simulation time 4227068442 ps
CPU time 2.28 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:42 AM PDT 24
Peak memory 201508 kb
Host smart-59b45186-b419-423d-94c4-fd07b6161031
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916400613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.2916400613
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.2154135933
Short name T196
Test name
Test status
Simulation time 3460289112 ps
CPU time 2.18 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:51:38 AM PDT 24
Peak memory 201504 kb
Host smart-39b13611-395c-405d-9d39-3a939bf0ffe2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154135933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.2154135933
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1987393550
Short name T69
Test name
Test status
Simulation time 2646768873 ps
CPU time 1.88 seconds
Started Jul 02 07:51:27 AM PDT 24
Finished Jul 02 07:51:30 AM PDT 24
Peak memory 201544 kb
Host smart-172ca400-dd38-4ee7-a63f-57ca1b4d19a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987393550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1987393550
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2242336602
Short name T763
Test name
Test status
Simulation time 2472458583 ps
CPU time 2.22 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201620 kb
Host smart-cc0799cc-efaa-4ef7-824d-bfed4e0b9e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242336602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2242336602
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.539497257
Short name T427
Test name
Test status
Simulation time 2235849630 ps
CPU time 1.83 seconds
Started Jul 02 07:51:32 AM PDT 24
Finished Jul 02 07:51:37 AM PDT 24
Peak memory 201464 kb
Host smart-b644fd8f-631b-4bfd-9d03-cf9d6d6e99d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539497257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.539497257
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2537871889
Short name T779
Test name
Test status
Simulation time 2511906659 ps
CPU time 7.07 seconds
Started Jul 02 07:51:32 AM PDT 24
Finished Jul 02 07:51:42 AM PDT 24
Peak memory 201532 kb
Host smart-d279bdf1-3682-42d1-b8ba-db7400c95e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537871889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2537871889
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.1739275082
Short name T185
Test name
Test status
Simulation time 2120931383 ps
CPU time 2.27 seconds
Started Jul 02 07:51:30 AM PDT 24
Finished Jul 02 07:51:36 AM PDT 24
Peak memory 201440 kb
Host smart-94681cae-0be2-40ab-a277-960ab6dbc9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739275082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.1739275082
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2144058145
Short name T1
Test name
Test status
Simulation time 5607068326 ps
CPU time 3.35 seconds
Started Jul 02 07:51:40 AM PDT 24
Finished Jul 02 07:51:47 AM PDT 24
Peak memory 201504 kb
Host smart-93e0e767-8724-4c93-b07d-df6eea72435a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144058145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.2144058145
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.3734585010
Short name T226
Test name
Test status
Simulation time 2090442801 ps
CPU time 0.98 seconds
Started Jul 02 07:51:42 AM PDT 24
Finished Jul 02 07:51:46 AM PDT 24
Peak memory 201512 kb
Host smart-4883979e-22d8-4c4c-ad03-6c95abba37a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734585010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.3734585010
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3312573185
Short name T444
Test name
Test status
Simulation time 3080763843 ps
CPU time 8.84 seconds
Started Jul 02 07:51:31 AM PDT 24
Finished Jul 02 07:51:44 AM PDT 24
Peak memory 201688 kb
Host smart-f27adbb8-0467-45f8-846b-e36450b2ab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312573185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3
312573185
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1596111493
Short name T462
Test name
Test status
Simulation time 184846022657 ps
CPU time 231.51 seconds
Started Jul 02 07:51:27 AM PDT 24
Finished Jul 02 07:55:20 AM PDT 24
Peak memory 201792 kb
Host smart-625d8b50-2876-4982-8a64-241b55e95a29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596111493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.1596111493
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2408705351
Short name T79
Test name
Test status
Simulation time 37168900641 ps
CPU time 25.55 seconds
Started Jul 02 07:51:34 AM PDT 24
Finished Jul 02 07:52:03 AM PDT 24
Peak memory 201776 kb
Host smart-438edeae-1fe8-40af-bc54-cc8e8aa0502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408705351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.2408705351
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3268225801
Short name T432
Test name
Test status
Simulation time 4345702759 ps
CPU time 12.22 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201524 kb
Host smart-58031b6f-5d7e-4136-a713-23f43b247f4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268225801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.3268225801
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3215491244
Short name T264
Test name
Test status
Simulation time 3380608958 ps
CPU time 2.75 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:51:56 AM PDT 24
Peak memory 201504 kb
Host smart-7f7a370c-2608-4bb2-b20b-7f820c426572
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215491244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.3215491244
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3420874767
Short name T158
Test name
Test status
Simulation time 2611500857 ps
CPU time 7.05 seconds
Started Jul 02 07:51:36 AM PDT 24
Finished Jul 02 07:51:48 AM PDT 24
Peak memory 201540 kb
Host smart-0817a458-09a1-498e-ba3f-397b902c4456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420874767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.3420874767
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2652299085
Short name T501
Test name
Test status
Simulation time 2474568578 ps
CPU time 3.77 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:46 AM PDT 24
Peak memory 201464 kb
Host smart-8ff148a6-34dc-46d3-8e15-c196c41e8070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652299085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2652299085
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3916062383
Short name T15
Test name
Test status
Simulation time 2044705923 ps
CPU time 6.01 seconds
Started Jul 02 07:51:33 AM PDT 24
Finished Jul 02 07:51:43 AM PDT 24
Peak memory 201488 kb
Host smart-47245a25-2fad-42d3-b719-1e7a9a20f831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916062383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.3916062383
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1637033639
Short name T678
Test name
Test status
Simulation time 2536076681 ps
CPU time 2.28 seconds
Started Jul 02 07:51:31 AM PDT 24
Finished Jul 02 07:51:37 AM PDT 24
Peak memory 201592 kb
Host smart-beefbaaa-2bb1-4622-8d78-2a494105d4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637033639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.1637033639
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1606886012
Short name T139
Test name
Test status
Simulation time 2137259369 ps
CPU time 2.04 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201528 kb
Host smart-448106f9-8b08-4380-998e-b0f81513e0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606886012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1606886012
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.782433146
Short name T632
Test name
Test status
Simulation time 11837479845 ps
CPU time 7.53 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:38 AM PDT 24
Peak memory 201776 kb
Host smart-3a086999-470a-4636-9055-2fb41d2526a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782433146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.782433146
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1542219493
Short name T27
Test name
Test status
Simulation time 2861227419 ps
CPU time 5.63 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:51:59 AM PDT 24
Peak memory 201504 kb
Host smart-3a40569d-d1e4-48ab-a468-ad61bff67908
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542219493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1542219493
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.1761077568
Short name T709
Test name
Test status
Simulation time 2081561284 ps
CPU time 1.23 seconds
Started Jul 02 07:51:36 AM PDT 24
Finished Jul 02 07:51:42 AM PDT 24
Peak memory 201568 kb
Host smart-b87d1456-c9ec-413d-a69d-4e6bae92d263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761077568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.1761077568
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1876847577
Short name T557
Test name
Test status
Simulation time 93568583168 ps
CPU time 228.49 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:55:32 AM PDT 24
Peak memory 201712 kb
Host smart-22b11b0e-ac2f-42b9-8b2b-fdf59edf645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876847577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.1
876847577
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.113187343
Short name T387
Test name
Test status
Simulation time 120428253796 ps
CPU time 87.99 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 201624 kb
Host smart-0355a19c-fda9-4a1d-b5d6-f59ed0809b77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113187343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_combo_detect.113187343
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2493172541
Short name T388
Test name
Test status
Simulation time 25580441876 ps
CPU time 63.87 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:52:53 AM PDT 24
Peak memory 201788 kb
Host smart-636a822b-4714-4974-a70a-9083bbc36458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493172541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2493172541
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1638409208
Short name T262
Test name
Test status
Simulation time 3201234727 ps
CPU time 8.6 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201592 kb
Host smart-4fe70a3a-f59e-48f0-992a-c3b3807e15b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638409208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.1638409208
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.554893899
Short name T87
Test name
Test status
Simulation time 3001526955 ps
CPU time 4.22 seconds
Started Jul 02 07:51:28 AM PDT 24
Finished Jul 02 07:51:33 AM PDT 24
Peak memory 201500 kb
Host smart-fb898be0-bf82-4d39-9933-1375a75b436c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554893899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctr
l_edge_detect.554893899
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3522586426
Short name T655
Test name
Test status
Simulation time 2652766174 ps
CPU time 1.68 seconds
Started Jul 02 07:51:30 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 201592 kb
Host smart-901b7003-05c2-47dd-9a7e-91d4266eb168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522586426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.3522586426
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1908533501
Short name T562
Test name
Test status
Simulation time 2485099812 ps
CPU time 1.7 seconds
Started Jul 02 07:51:42 AM PDT 24
Finished Jul 02 07:51:47 AM PDT 24
Peak memory 201524 kb
Host smart-c3a91fdc-ab2c-47e0-b899-466ce2c90e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908533501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1908533501
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1936085068
Short name T711
Test name
Test status
Simulation time 2116977024 ps
CPU time 2 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:45 AM PDT 24
Peak memory 201488 kb
Host smart-ef33a2ab-24ac-45f4-b19e-a09e74daeb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936085068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1936085068
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2790921464
Short name T237
Test name
Test status
Simulation time 2523695288 ps
CPU time 2.45 seconds
Started Jul 02 07:51:30 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 201500 kb
Host smart-365f6207-8b18-4db5-992d-d65bf444e324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790921464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2790921464
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.4146611782
Short name T94
Test name
Test status
Simulation time 2116151837 ps
CPU time 3.12 seconds
Started Jul 02 07:51:40 AM PDT 24
Finished Jul 02 07:51:47 AM PDT 24
Peak memory 201480 kb
Host smart-a337d23e-0eb0-4eb5-b128-18a8c7b5c524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146611782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.4146611782
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1970160244
Short name T651
Test name
Test status
Simulation time 12706638660 ps
CPU time 34.38 seconds
Started Jul 02 07:51:43 AM PDT 24
Finished Jul 02 07:52:20 AM PDT 24
Peak memory 201560 kb
Host smart-241642f1-637e-4ad9-a7b5-16f3399ef60e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970160244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1970160244
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3054691984
Short name T235
Test name
Test status
Simulation time 69573804723 ps
CPU time 44.36 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:52:15 AM PDT 24
Peak memory 210192 kb
Host smart-21bb0264-a051-489d-b847-e8d153a87dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054691984 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.3054691984
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2262147692
Short name T706
Test name
Test status
Simulation time 3358730069 ps
CPU time 6.44 seconds
Started Jul 02 07:51:44 AM PDT 24
Finished Jul 02 07:51:53 AM PDT 24
Peak memory 201544 kb
Host smart-b18304b6-53f7-411b-b5cd-0c629fc09d24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262147692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.2262147692
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.203469776
Short name T475
Test name
Test status
Simulation time 2041727027 ps
CPU time 1.59 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:51:53 AM PDT 24
Peak memory 201608 kb
Host smart-40419baa-4230-4860-850d-2a6851912c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203469776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_tes
t.203469776
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3330193614
Short name T92
Test name
Test status
Simulation time 520528633196 ps
CPU time 1418.65 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 08:15:19 AM PDT 24
Peak memory 201676 kb
Host smart-52e2c79c-d57c-4635-a838-5348f55d0d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330193614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3
330193614
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1109506749
Short name T260
Test name
Test status
Simulation time 96049099766 ps
CPU time 58.52 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:52:47 AM PDT 24
Peak memory 201816 kb
Host smart-be01285d-f23c-44aa-b147-203a92e20311
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109506749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1109506749
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.934974272
Short name T675
Test name
Test status
Simulation time 39600885448 ps
CPU time 27.18 seconds
Started Jul 02 07:51:41 AM PDT 24
Finished Jul 02 07:52:11 AM PDT 24
Peak memory 201792 kb
Host smart-b60269cc-970b-4ea0-b2df-582e900a38c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934974272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.934974272
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2646145607
Short name T401
Test name
Test status
Simulation time 3194048286 ps
CPU time 0.98 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:51:50 AM PDT 24
Peak memory 201500 kb
Host smart-36ea3c59-8aa3-406b-8a67-5fa3636eaa42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646145607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.2646145607
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.123042586
Short name T200
Test name
Test status
Simulation time 2446038743 ps
CPU time 6.65 seconds
Started Jul 02 07:51:38 AM PDT 24
Finished Jul 02 07:51:49 AM PDT 24
Peak memory 201612 kb
Host smart-e3af2606-1faa-4f59-9bf9-5d586ca649b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123042586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctr
l_edge_detect.123042586
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3312839629
Short name T251
Test name
Test status
Simulation time 2612997135 ps
CPU time 7.09 seconds
Started Jul 02 07:51:41 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201512 kb
Host smart-da7e20c4-4dba-4cdc-9742-d653923ae98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312839629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.3312839629
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3684753896
Short name T601
Test name
Test status
Simulation time 2603463611 ps
CPU time 1 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201564 kb
Host smart-376421c5-ac21-4882-b97c-1197c4798c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684753896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3684753896
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.706674848
Short name T123
Test name
Test status
Simulation time 2076663489 ps
CPU time 3.12 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:43 AM PDT 24
Peak memory 201492 kb
Host smart-12afd725-daf0-41ea-bcf3-a8a915d4c6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706674848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.706674848
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1575010046
Short name T666
Test name
Test status
Simulation time 2514542035 ps
CPU time 3.8 seconds
Started Jul 02 07:51:42 AM PDT 24
Finished Jul 02 07:51:49 AM PDT 24
Peak memory 201532 kb
Host smart-db5ebc8a-111e-4fca-9705-a6c5f69ae870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575010046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1575010046
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.327726601
Short name T523
Test name
Test status
Simulation time 2171580949 ps
CPU time 1.31 seconds
Started Jul 02 07:51:29 AM PDT 24
Finished Jul 02 07:51:32 AM PDT 24
Peak memory 201532 kb
Host smart-bbaa9d5d-99d2-4241-8232-375a74e469f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327726601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.327726601
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.836671324
Short name T249
Test name
Test status
Simulation time 54673843716 ps
CPU time 128.28 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:54:00 AM PDT 24
Peak memory 209708 kb
Host smart-38b90c0f-0aa6-4990-8c1b-b49b59ce3872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836671324 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.836671324
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4247261436
Short name T631
Test name
Test status
Simulation time 8894347719 ps
CPU time 1.91 seconds
Started Jul 02 07:51:36 AM PDT 24
Finished Jul 02 07:51:42 AM PDT 24
Peak memory 201596 kb
Host smart-bbc5868b-d417-4869-9917-9c1ded967044
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247261436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.4247261436
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.1988442772
Short name T422
Test name
Test status
Simulation time 2012836062 ps
CPU time 5.68 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:51:56 AM PDT 24
Peak memory 201536 kb
Host smart-02b5b804-4623-42c6-820d-b6b86cb8e423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988442772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.1988442772
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3256349259
Short name T538
Test name
Test status
Simulation time 3097269823 ps
CPU time 5.45 seconds
Started Jul 02 07:51:41 AM PDT 24
Finished Jul 02 07:51:50 AM PDT 24
Peak memory 201616 kb
Host smart-7c5f040e-0fee-48ef-9c84-b1107b275f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256349259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3
256349259
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.908091451
Short name T228
Test name
Test status
Simulation time 176978173054 ps
CPU time 122.99 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:53:52 AM PDT 24
Peak memory 201780 kb
Host smart-3df1c9ec-c435-4ed9-aff9-01f4d3762cca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908091451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_combo_detect.908091451
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.814869459
Short name T554
Test name
Test status
Simulation time 38669166811 ps
CPU time 18.27 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:13 AM PDT 24
Peak memory 201836 kb
Host smart-efc7d6e4-c7ae-47ff-961d-b4ec7759c7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814869459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_wi
th_pre_cond.814869459
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1105626113
Short name T52
Test name
Test status
Simulation time 3209509567 ps
CPU time 4.9 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:51:44 AM PDT 24
Peak memory 201604 kb
Host smart-308476fc-d5b4-4119-bc47-c5a8d291a8e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105626113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1105626113
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3759391279
Short name T36
Test name
Test status
Simulation time 4331903136 ps
CPU time 2.45 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:51:52 AM PDT 24
Peak memory 201544 kb
Host smart-47de1656-244f-4e3d-9723-3aee05957909
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759391279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3759391279
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1329854220
Short name T719
Test name
Test status
Simulation time 2625496806 ps
CPU time 3.51 seconds
Started Jul 02 07:51:45 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201520 kb
Host smart-3deff5be-77c4-4159-926c-1b0de88b3c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329854220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1329854220
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.4018513433
Short name T522
Test name
Test status
Simulation time 2455055152 ps
CPU time 6.91 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:51:55 AM PDT 24
Peak memory 201588 kb
Host smart-7b6b30d6-289c-421c-b1e7-0002172d1f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018513433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.4018513433
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4003085180
Short name T552
Test name
Test status
Simulation time 2150842178 ps
CPU time 5.91 seconds
Started Jul 02 07:51:45 AM PDT 24
Finished Jul 02 07:51:54 AM PDT 24
Peak memory 201464 kb
Host smart-541404df-98e9-4ec0-9629-b627d52c8576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003085180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.4003085180
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1421098463
Short name T638
Test name
Test status
Simulation time 2508935507 ps
CPU time 7.35 seconds
Started Jul 02 07:51:39 AM PDT 24
Finished Jul 02 07:51:50 AM PDT 24
Peak memory 201576 kb
Host smart-92756a72-14a2-431a-931c-845f08beb1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421098463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.1421098463
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.2112066094
Short name T615
Test name
Test status
Simulation time 2117262111 ps
CPU time 3.29 seconds
Started Jul 02 07:51:43 AM PDT 24
Finished Jul 02 07:51:49 AM PDT 24
Peak memory 201460 kb
Host smart-784b1a54-6c6e-4fc0-90dc-081b4a48c14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112066094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2112066094
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1625079992
Short name T106
Test name
Test status
Simulation time 73067429242 ps
CPU time 84.68 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:53:13 AM PDT 24
Peak memory 210204 kb
Host smart-8c24e6a6-dcec-4979-a599-5615ea12270b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625079992 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1625079992
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.2316746712
Short name T608
Test name
Test status
Simulation time 2017035319 ps
CPU time 5.56 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:51:57 AM PDT 24
Peak memory 201524 kb
Host smart-e037c5d0-87b7-479e-afed-b7a063e32f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316746712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.2316746712
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3735568548
Short name T728
Test name
Test status
Simulation time 190989328092 ps
CPU time 478.83 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:59:53 AM PDT 24
Peak memory 201684 kb
Host smart-d5f8ad0b-a8b1-40d8-844e-2c4ade9822f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735568548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.3
735568548
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3467210652
Short name T108
Test name
Test status
Simulation time 115354536668 ps
CPU time 77.38 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:53:13 AM PDT 24
Peak memory 201768 kb
Host smart-2e0fbc83-ad0d-4ab1-8d9a-9dd47bad6dfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467210652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3467210652
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3374764802
Short name T194
Test name
Test status
Simulation time 4085655275 ps
CPU time 5.94 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:01 AM PDT 24
Peak memory 201472 kb
Host smart-d073719f-ab45-4acb-9c47-4ea5a474a285
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374764802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.3374764802
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.1732870026
Short name T652
Test name
Test status
Simulation time 4080828232 ps
CPU time 7.44 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:52:05 AM PDT 24
Peak memory 201528 kb
Host smart-cfa51a69-abaf-4b5f-81ce-065cd7d8a5fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732870026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.1732870026
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3587962472
Short name T120
Test name
Test status
Simulation time 2613771745 ps
CPU time 7.1 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:51:59 AM PDT 24
Peak memory 201552 kb
Host smart-c50a4917-0fa5-4c04-816c-b9b55ed188a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587962472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3587962472
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3591858310
Short name T705
Test name
Test status
Simulation time 2473218924 ps
CPU time 7.19 seconds
Started Jul 02 07:51:37 AM PDT 24
Finished Jul 02 07:51:48 AM PDT 24
Peak memory 201516 kb
Host smart-cbf1f04a-a899-4d10-ac5f-2dfdbdacfd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591858310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3591858310
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.56725139
Short name T403
Test name
Test status
Simulation time 2241214326 ps
CPU time 2.09 seconds
Started Jul 02 07:51:41 AM PDT 24
Finished Jul 02 07:51:46 AM PDT 24
Peak memory 201572 kb
Host smart-3b06ea12-63b4-40f7-9ed1-a50998ad7914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56725139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.56725139
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.141962559
Short name T784
Test name
Test status
Simulation time 2521342447 ps
CPU time 4.32 seconds
Started Jul 02 07:51:47 AM PDT 24
Finished Jul 02 07:51:54 AM PDT 24
Peak memory 201612 kb
Host smart-57a25061-0069-4352-92f0-ada0ea534d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141962559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.141962559
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.2640011333
Short name T703
Test name
Test status
Simulation time 2115023884 ps
CPU time 4.97 seconds
Started Jul 02 07:51:42 AM PDT 24
Finished Jul 02 07:51:50 AM PDT 24
Peak memory 201396 kb
Host smart-fec1ccc4-3d56-473e-bd82-c396ed18d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640011333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2640011333
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.1308358906
Short name T664
Test name
Test status
Simulation time 16090613325 ps
CPU time 38.96 seconds
Started Jul 02 07:51:41 AM PDT 24
Finished Jul 02 07:52:23 AM PDT 24
Peak memory 201624 kb
Host smart-1213cccd-a11d-4b3f-bcbc-90dc12008f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308358906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.1308358906
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4190377414
Short name T216
Test name
Test status
Simulation time 28559629013 ps
CPU time 72.72 seconds
Started Jul 02 07:51:35 AM PDT 24
Finished Jul 02 07:52:52 AM PDT 24
Peak memory 212384 kb
Host smart-8dfcb3db-3399-49de-960e-32ef9ad10e3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190377414 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.4190377414
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1503045738
Short name T75
Test name
Test status
Simulation time 4614538222 ps
CPU time 1.79 seconds
Started Jul 02 07:51:52 AM PDT 24
Finished Jul 02 07:51:59 AM PDT 24
Peak memory 201512 kb
Host smart-e01bc703-104d-4ac7-a71c-8a80cfb21ecf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503045738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.1503045738
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.1815305210
Short name T190
Test name
Test status
Simulation time 2009959088 ps
CPU time 5.66 seconds
Started Jul 02 07:51:45 AM PDT 24
Finished Jul 02 07:51:53 AM PDT 24
Peak memory 201496 kb
Host smart-a785608c-ad53-42ec-9dfc-e768b27d92c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815305210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.1815305210
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3951002307
Short name T731
Test name
Test status
Simulation time 3043017701 ps
CPU time 2.51 seconds
Started Jul 02 07:51:38 AM PDT 24
Finished Jul 02 07:51:44 AM PDT 24
Peak memory 201944 kb
Host smart-3cc7ea0e-e699-4a86-ab95-65d66c647df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951002307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3
951002307
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.3394163132
Short name T155
Test name
Test status
Simulation time 60285613892 ps
CPU time 164.25 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:54:38 AM PDT 24
Peak memory 201800 kb
Host smart-2a42afe0-b290-44d4-9ca3-385c05d32089
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394163132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.3394163132
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1096068038
Short name T592
Test name
Test status
Simulation time 82968152619 ps
CPU time 55.66 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:52:49 AM PDT 24
Peak memory 201928 kb
Host smart-1f83cc51-4da3-45af-91dd-ecdda74efa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096068038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.1096068038
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1767685284
Short name T183
Test name
Test status
Simulation time 548535889857 ps
CPU time 356.78 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:57:50 AM PDT 24
Peak memory 201500 kb
Host smart-41d67f8e-3ba6-4ddb-b395-067bc509e1fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767685284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.1767685284
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.1113555547
Short name T761
Test name
Test status
Simulation time 3011056767 ps
CPU time 2.54 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:51:56 AM PDT 24
Peak memory 201504 kb
Host smart-4055f996-8ac3-47a3-9045-7886ad88dac6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113555547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.1113555547
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1705341979
Short name T621
Test name
Test status
Simulation time 2610989132 ps
CPU time 7.03 seconds
Started Jul 02 07:51:36 AM PDT 24
Finished Jul 02 07:51:48 AM PDT 24
Peak memory 201432 kb
Host smart-eab349c7-b0fd-4f5e-8b14-878e2d259c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705341979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1705341979
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1481973404
Short name T119
Test name
Test status
Simulation time 2466548352 ps
CPU time 7.64 seconds
Started Jul 02 07:51:40 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201524 kb
Host smart-26c30bbd-ab1b-4c80-96d2-b8285e153ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481973404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1481973404
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2588599602
Short name T415
Test name
Test status
Simulation time 2132486140 ps
CPU time 2 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:51:55 AM PDT 24
Peak memory 201556 kb
Host smart-a200a6b2-cd00-4ecd-8b04-fcfe2165ed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588599602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2588599602
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1228554042
Short name T22
Test name
Test status
Simulation time 2520465534 ps
CPU time 3.56 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:51:57 AM PDT 24
Peak memory 201588 kb
Host smart-63a856af-9f67-407b-83f7-c7584a07c1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228554042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.1228554042
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.3664103212
Short name T151
Test name
Test status
Simulation time 2174965566 ps
CPU time 1.24 seconds
Started Jul 02 07:51:36 AM PDT 24
Finished Jul 02 07:51:41 AM PDT 24
Peak memory 201548 kb
Host smart-30bdd43d-31a3-4d3a-af13-f07544973755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664103212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.3664103212
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.2078849480
Short name T760
Test name
Test status
Simulation time 18477100480 ps
CPU time 38.38 seconds
Started Jul 02 07:51:42 AM PDT 24
Finished Jul 02 07:52:24 AM PDT 24
Peak memory 201604 kb
Host smart-92b210a6-df58-40f3-9497-75c83be0b99a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078849480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.2078849480
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1550620422
Short name T290
Test name
Test status
Simulation time 44844264302 ps
CPU time 30.75 seconds
Started Jul 02 07:51:58 AM PDT 24
Finished Jul 02 07:52:31 AM PDT 24
Peak memory 210192 kb
Host smart-eb04ccfd-85dc-47e1-8b19-9a7c3d9794f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550620422 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1550620422
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.187974619
Short name T395
Test name
Test status
Simulation time 565975054610 ps
CPU time 84.87 seconds
Started Jul 02 07:51:43 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 201508 kb
Host smart-60145376-d20a-41b1-b07a-1444d496e590
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187974619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ultra_low_pwr.187974619
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.2977775312
Short name T625
Test name
Test status
Simulation time 2024064514 ps
CPU time 1.88 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201588 kb
Host smart-3ccd927a-bc12-4953-aaf4-ad022ab2295f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977775312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.2977775312
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1464441845
Short name T317
Test name
Test status
Simulation time 3037071115 ps
CPU time 2.53 seconds
Started Jul 02 07:52:02 AM PDT 24
Finished Jul 02 07:52:06 AM PDT 24
Peak memory 201584 kb
Host smart-21a24e78-413c-418d-9867-066fb55daa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464441845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1
464441845
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3719531944
Short name T278
Test name
Test status
Simulation time 115446864861 ps
CPU time 149.53 seconds
Started Jul 02 07:52:03 AM PDT 24
Finished Jul 02 07:54:34 AM PDT 24
Peak memory 201768 kb
Host smart-ce137083-176a-410f-90fc-1879f5112d3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719531944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.3719531944
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1684569704
Short name T380
Test name
Test status
Simulation time 47416281513 ps
CPU time 32.08 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:52:23 AM PDT 24
Peak memory 201724 kb
Host smart-aa729eed-8212-4d15-8046-92dbaafcd71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684569704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.1684569704
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1611615642
Short name T531
Test name
Test status
Simulation time 3123481445 ps
CPU time 4.45 seconds
Started Jul 02 07:51:53 AM PDT 24
Finished Jul 02 07:52:02 AM PDT 24
Peak memory 201508 kb
Host smart-403ab15d-9393-432a-bdd1-70e08d8165e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611615642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.1611615642
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.3770604161
Short name T265
Test name
Test status
Simulation time 4357974642 ps
CPU time 8.94 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:04 AM PDT 24
Peak memory 201588 kb
Host smart-976ba581-1ca3-42ed-9803-4d52c39a9b5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770604161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.3770604161
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.310738297
Short name T650
Test name
Test status
Simulation time 2626349566 ps
CPU time 2.49 seconds
Started Jul 02 07:51:42 AM PDT 24
Finished Jul 02 07:51:48 AM PDT 24
Peak memory 201508 kb
Host smart-4e5c4f99-91ef-4688-b70d-8f89479faa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310738297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.310738297
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1178929786
Short name T616
Test name
Test status
Simulation time 2479556962 ps
CPU time 7 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:01 AM PDT 24
Peak memory 201548 kb
Host smart-716f1544-aa98-4715-a9c3-37795067399c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178929786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.1178929786
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2745314602
Short name T137
Test name
Test status
Simulation time 2082204381 ps
CPU time 1.38 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:51:56 AM PDT 24
Peak memory 201436 kb
Host smart-876426f9-3768-49d1-b255-92f1aa136582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745314602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2745314602
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3345509841
Short name T410
Test name
Test status
Simulation time 2520959763 ps
CPU time 3.88 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:51:56 AM PDT 24
Peak memory 201568 kb
Host smart-4b8f3016-9825-4329-8bf0-f24afca371a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345509841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.3345509841
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.2147382163
Short name T750
Test name
Test status
Simulation time 2122331063 ps
CPU time 2.48 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:51:54 AM PDT 24
Peak memory 201424 kb
Host smart-4bff5517-0eff-4379-862f-4fa4fdc36edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147382163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2147382163
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.952413965
Short name T460
Test name
Test status
Simulation time 11798340992 ps
CPU time 31.02 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:52:27 AM PDT 24
Peak memory 201660 kb
Host smart-089b4b76-583c-44ec-822c-a9be967b54a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952413965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_st
ress_all.952413965
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.4068009545
Short name T261
Test name
Test status
Simulation time 23283864057 ps
CPU time 56.91 seconds
Started Jul 02 07:51:54 AM PDT 24
Finished Jul 02 07:52:55 AM PDT 24
Peak memory 218060 kb
Host smart-01f83231-7273-4c99-b60f-685613db9459
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068009545 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.4068009545
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1838724027
Short name T702
Test name
Test status
Simulation time 8412568310 ps
CPU time 3.39 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:51:56 AM PDT 24
Peak memory 201632 kb
Host smart-0927c01c-d149-44c0-8de1-c6bc16cb1440
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838724027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.1838724027
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3424420095
Short name T406
Test name
Test status
Simulation time 2019263918 ps
CPU time 2.9 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:51:59 AM PDT 24
Peak memory 201612 kb
Host smart-d4812caa-50ec-45e7-b575-ea5093e753ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424420095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3424420095
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2561225453
Short name T44
Test name
Test status
Simulation time 3330997664 ps
CPU time 2.65 seconds
Started Jul 02 07:51:57 AM PDT 24
Finished Jul 02 07:52:02 AM PDT 24
Peak memory 201584 kb
Host smart-1f6b9a08-8482-4c30-9b3b-886f8560a781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561225453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.2
561225453
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3259938452
Short name T174
Test name
Test status
Simulation time 69468520903 ps
CPU time 41.66 seconds
Started Jul 02 07:51:42 AM PDT 24
Finished Jul 02 07:52:27 AM PDT 24
Peak memory 201768 kb
Host smart-2eafc3c8-87c2-488f-a25a-e2e3f24d810a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259938452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.3259938452
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1902699725
Short name T389
Test name
Test status
Simulation time 105223313086 ps
CPU time 28.32 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:22 AM PDT 24
Peak memory 201736 kb
Host smart-e13c00c5-ac0b-4173-97d3-2a0dedf564f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902699725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.1902699725
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3251588705
Short name T513
Test name
Test status
Simulation time 3140392528 ps
CPU time 8.7 seconds
Started Jul 02 07:51:40 AM PDT 24
Finished Jul 02 07:51:52 AM PDT 24
Peak memory 201492 kb
Host smart-552739f2-bc0a-4692-b100-5cd18929ed89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251588705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.3251588705
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1203779451
Short name T35
Test name
Test status
Simulation time 2714624284 ps
CPU time 7.42 seconds
Started Jul 02 07:51:55 AM PDT 24
Finished Jul 02 07:52:06 AM PDT 24
Peak memory 201596 kb
Host smart-55c5a771-a219-4064-bdb8-edd26bb9a87a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203779451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1203779451
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2943836408
Short name T489
Test name
Test status
Simulation time 2609422690 ps
CPU time 7.31 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:52:00 AM PDT 24
Peak memory 201500 kb
Host smart-e41ac955-abe5-44b9-a4ae-29faf99836b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943836408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.2943836408
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1636516813
Short name T176
Test name
Test status
Simulation time 2492652538 ps
CPU time 1.72 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:51:55 AM PDT 24
Peak memory 201552 kb
Host smart-0d6d12bd-5a02-4821-840b-864a9087be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636516813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1636516813
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3282634224
Short name T150
Test name
Test status
Simulation time 2140668131 ps
CPU time 2.02 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:51:57 AM PDT 24
Peak memory 201552 kb
Host smart-ad0399c7-1c2e-49f0-b86f-52f3103108c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282634224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.3282634224
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.341161980
Short name T227
Test name
Test status
Simulation time 2529854441 ps
CPU time 2.45 seconds
Started Jul 02 07:51:58 AM PDT 24
Finished Jul 02 07:52:03 AM PDT 24
Peak memory 201520 kb
Host smart-f1c4a2e1-3d56-4077-83fc-2be9fa649077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341161980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.341161980
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.2981783825
Short name T436
Test name
Test status
Simulation time 2109303547 ps
CPU time 5.98 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:00 AM PDT 24
Peak memory 201368 kb
Host smart-e6866be4-3c72-4369-b3b2-962efa07b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981783825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2981783825
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.840305386
Short name T590
Test name
Test status
Simulation time 10996183960 ps
CPU time 3.43 seconds
Started Jul 02 07:51:48 AM PDT 24
Finished Jul 02 07:51:55 AM PDT 24
Peak memory 201664 kb
Host smart-1039a84a-b9dd-4bb3-9851-aa29f0f82797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840305386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_st
ress_all.840305386
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1045752821
Short name T88
Test name
Test status
Simulation time 3960004700 ps
CPU time 2.16 seconds
Started Jul 02 07:51:46 AM PDT 24
Finished Jul 02 07:51:51 AM PDT 24
Peak memory 201404 kb
Host smart-2a51f53c-9970-44cb-a665-ac4ff8ea8c1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045752821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1045752821
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.17663370
Short name T623
Test name
Test status
Simulation time 2014721261 ps
CPU time 5.51 seconds
Started Jul 02 07:51:52 AM PDT 24
Finished Jul 02 07:52:06 AM PDT 24
Peak memory 201488 kb
Host smart-357c25e6-346d-4124-9e08-268072bda94e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17663370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test
.17663370
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2306060744
Short name T468
Test name
Test status
Simulation time 3550244244 ps
CPU time 9.72 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:04 AM PDT 24
Peak memory 201616 kb
Host smart-a3109e9a-0496-4404-b72f-d09e09e037b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306060744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.2
306060744
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.446544662
Short name T105
Test name
Test status
Simulation time 136643027581 ps
CPU time 30.09 seconds
Started Jul 02 07:51:56 AM PDT 24
Finished Jul 02 07:52:29 AM PDT 24
Peak memory 201872 kb
Host smart-1131f4bf-e396-4970-be33-2c9bf79308b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446544662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_combo_detect.446544662
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.539532839
Short name T371
Test name
Test status
Simulation time 127462604560 ps
CPU time 168.23 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 201820 kb
Host smart-437d1ba9-8b37-48a1-92a4-f093090767d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539532839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_wi
th_pre_cond.539532839
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3154859634
Short name T654
Test name
Test status
Simulation time 4314336851 ps
CPU time 1.89 seconds
Started Jul 02 07:51:59 AM PDT 24
Finished Jul 02 07:52:03 AM PDT 24
Peak memory 201604 kb
Host smart-28493baa-28fc-4858-ad92-998288984a94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154859634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.3154859634
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2767798235
Short name T9
Test name
Test status
Simulation time 3041057704 ps
CPU time 7.11 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:52:03 AM PDT 24
Peak memory 201552 kb
Host smart-debde8a0-75fb-4230-a595-edacecd4536f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767798235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2767798235
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.760565818
Short name T724
Test name
Test status
Simulation time 2616386064 ps
CPU time 4.23 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:51:57 AM PDT 24
Peak memory 201500 kb
Host smart-e45033ac-af0d-4416-89c5-3a2bf2cb166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760565818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.760565818
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3461520883
Short name T60
Test name
Test status
Simulation time 2470545224 ps
CPU time 7.65 seconds
Started Jul 02 07:51:53 AM PDT 24
Finished Jul 02 07:52:05 AM PDT 24
Peak memory 201516 kb
Host smart-91ca4e31-044e-42b4-b1ed-20056584b6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461520883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3461520883
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1248127368
Short name T458
Test name
Test status
Simulation time 2260736555 ps
CPU time 3.46 seconds
Started Jul 02 07:51:42 AM PDT 24
Finished Jul 02 07:51:49 AM PDT 24
Peak memory 201516 kb
Host smart-aa8cfe7f-b8bb-4786-8186-28e01abc90f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248127368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1248127368
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2059608611
Short name T414
Test name
Test status
Simulation time 2516998522 ps
CPU time 3.78 seconds
Started Jul 02 07:51:57 AM PDT 24
Finished Jul 02 07:52:04 AM PDT 24
Peak memory 201516 kb
Host smart-4456ba22-7a6e-488a-af75-a6c298a23022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059608611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2059608611
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.1942711231
Short name T425
Test name
Test status
Simulation time 2129718465 ps
CPU time 1.88 seconds
Started Jul 02 07:51:58 AM PDT 24
Finished Jul 02 07:52:03 AM PDT 24
Peak memory 201448 kb
Host smart-da0a8a49-172e-4306-9bcf-11c7e4fac618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942711231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1942711231
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.784927972
Short name T424
Test name
Test status
Simulation time 9552209904 ps
CPU time 2.89 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:51:59 AM PDT 24
Peak memory 201472 kb
Host smart-7d39cea5-9006-403c-96e5-69d7cdf33063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784927972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_st
ress_all.784927972
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.401429088
Short name T149
Test name
Test status
Simulation time 5988389142 ps
CPU time 7.7 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:02 AM PDT 24
Peak memory 201500 kb
Host smart-861799f9-1b96-4127-9955-fa76cbd86bd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401429088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ultra_low_pwr.401429088
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.765926787
Short name T545
Test name
Test status
Simulation time 2011343571 ps
CPU time 5.73 seconds
Started Jul 02 07:50:11 AM PDT 24
Finished Jul 02 07:50:19 AM PDT 24
Peak memory 201612 kb
Host smart-801892e0-6f2a-4aeb-818d-e557d2eca643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765926787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test
.765926787
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.4035150508
Short name T514
Test name
Test status
Simulation time 3341317330 ps
CPU time 8.7 seconds
Started Jul 02 07:50:21 AM PDT 24
Finished Jul 02 07:50:31 AM PDT 24
Peak memory 201940 kb
Host smart-47923f70-d16d-4b09-8320-c6b4ad1453e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035150508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.4035150508
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3655304910
Short name T269
Test name
Test status
Simulation time 71355585492 ps
CPU time 186.91 seconds
Started Jul 02 07:50:14 AM PDT 24
Finished Jul 02 07:53:22 AM PDT 24
Peak memory 201788 kb
Host smart-ebac42ca-654f-4021-91cb-83d055aa47df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655304910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3655304910
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.720206108
Short name T541
Test name
Test status
Simulation time 4827082990 ps
CPU time 7.27 seconds
Started Jul 02 07:50:12 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 201588 kb
Host smart-714172c4-9ebd-4941-afe5-e46805f2f692
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720206108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ec_pwr_on_rst.720206108
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1010405413
Short name T220
Test name
Test status
Simulation time 1218508337637 ps
CPU time 533.17 seconds
Started Jul 02 07:50:18 AM PDT 24
Finished Jul 02 07:59:11 AM PDT 24
Peak memory 201628 kb
Host smart-f785d346-6ef2-4aa4-95d4-f6840c599f86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010405413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.1010405413
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.551172007
Short name T627
Test name
Test status
Simulation time 2608931202 ps
CPU time 7.3 seconds
Started Jul 02 07:50:12 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 201516 kb
Host smart-6e09af26-c421-4b63-bb16-e46254c6ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551172007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.551172007
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.19119748
Short name T749
Test name
Test status
Simulation time 2456726509 ps
CPU time 6.82 seconds
Started Jul 02 07:50:07 AM PDT 24
Finished Jul 02 07:50:16 AM PDT 24
Peak memory 201616 kb
Host smart-c17583c6-cc34-48a6-b2cb-90c3fdb836af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19119748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.19119748
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1448881097
Short name T546
Test name
Test status
Simulation time 2166676828 ps
CPU time 0.92 seconds
Started Jul 02 07:50:07 AM PDT 24
Finished Jul 02 07:50:11 AM PDT 24
Peak memory 201532 kb
Host smart-f4c57946-e8ef-40ed-8672-413dc31578f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448881097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.1448881097
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1686239514
Short name T670
Test name
Test status
Simulation time 2507242959 ps
CPU time 6.8 seconds
Started Jul 02 07:50:11 AM PDT 24
Finished Jul 02 07:50:20 AM PDT 24
Peak memory 201504 kb
Host smart-e984c092-2a06-4eed-bda1-4501e3d59d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686239514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1686239514
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.3487228035
Short name T662
Test name
Test status
Simulation time 2127806598 ps
CPU time 2.59 seconds
Started Jul 02 07:50:06 AM PDT 24
Finished Jul 02 07:50:12 AM PDT 24
Peak memory 201220 kb
Host smart-692143cf-dfb4-4d28-91e7-f1b70c3685db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487228035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.3487228035
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.2169224971
Short name T198
Test name
Test status
Simulation time 20420820145 ps
CPU time 42.58 seconds
Started Jul 02 07:50:20 AM PDT 24
Finished Jul 02 07:51:04 AM PDT 24
Peak memory 201504 kb
Host smart-72b88e6a-d6d3-4858-b51d-0533e6e4ef01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169224971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.2169224971
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3706350025
Short name T396
Test name
Test status
Simulation time 38376721606 ps
CPU time 27.36 seconds
Started Jul 02 07:50:07 AM PDT 24
Finished Jul 02 07:50:37 AM PDT 24
Peak memory 218248 kb
Host smart-e0f99fcd-0ab0-49a7-985a-d6705b20728c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706350025 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3706350025
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2909048118
Short name T272
Test name
Test status
Simulation time 70623965805 ps
CPU time 175.24 seconds
Started Jul 02 07:51:55 AM PDT 24
Finished Jul 02 07:54:54 AM PDT 24
Peak memory 201900 kb
Host smart-5551eebf-be72-426f-aaac-a1d00d29f5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909048118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.2909048118
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3205581156
Short name T38
Test name
Test status
Simulation time 41151920084 ps
CPU time 29.88 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:25 AM PDT 24
Peak memory 201844 kb
Host smart-0bbb566e-7fec-4efb-a636-765a87623471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205581156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.3205581156
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.114252662
Short name T232
Test name
Test status
Simulation time 28577480019 ps
CPU time 68.7 seconds
Started Jul 02 07:51:55 AM PDT 24
Finished Jul 02 07:53:07 AM PDT 24
Peak memory 201832 kb
Host smart-f666951e-fa57-4017-8ba4-18b3748a5ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114252662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_wi
th_pre_cond.114252662
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.163059385
Short name T268
Test name
Test status
Simulation time 31377496604 ps
CPU time 22.2 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:52:18 AM PDT 24
Peak memory 201808 kb
Host smart-ab75b1fb-e698-4792-b807-8a218f4d6105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163059385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_wi
th_pre_cond.163059385
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.876167317
Short name T660
Test name
Test status
Simulation time 33745714845 ps
CPU time 91.08 seconds
Started Jul 02 07:51:57 AM PDT 24
Finished Jul 02 07:53:31 AM PDT 24
Peak memory 201752 kb
Host smart-d08b2ff2-46a3-460b-8b8b-bf316a5d67a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876167317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_wi
th_pre_cond.876167317
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4015007670
Short name T721
Test name
Test status
Simulation time 25598844773 ps
CPU time 21.53 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:52:17 AM PDT 24
Peak memory 201780 kb
Host smart-d895623c-e7d1-4758-9b4f-4c25bda595e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015007670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.4015007670
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2288658210
Short name T128
Test name
Test status
Simulation time 69814435986 ps
CPU time 88.06 seconds
Started Jul 02 07:51:47 AM PDT 24
Finished Jul 02 07:53:18 AM PDT 24
Peak memory 201824 kb
Host smart-c0192f75-0e81-451f-b23c-2581779dc2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288658210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.2288658210
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.2756588555
Short name T689
Test name
Test status
Simulation time 2046473071 ps
CPU time 1.79 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:25 AM PDT 24
Peak memory 201624 kb
Host smart-2268b466-7bcd-48a7-845c-67b780e62ae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756588555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.2756588555
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1473251076
Short name T603
Test name
Test status
Simulation time 3557465881 ps
CPU time 4.15 seconds
Started Jul 02 07:50:11 AM PDT 24
Finished Jul 02 07:50:17 AM PDT 24
Peak memory 201632 kb
Host smart-eab6750a-3b36-41e7-9173-728112f3a26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473251076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1473251076
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1557194883
Short name T143
Test name
Test status
Simulation time 103792211288 ps
CPU time 131.37 seconds
Started Jul 02 07:50:13 AM PDT 24
Finished Jul 02 07:52:26 AM PDT 24
Peak memory 201880 kb
Host smart-c19a421a-e5f6-4f03-a0d8-162765f7de13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557194883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.1557194883
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1380732183
Short name T566
Test name
Test status
Simulation time 24098586667 ps
CPU time 19.95 seconds
Started Jul 02 07:50:16 AM PDT 24
Finished Jul 02 07:50:37 AM PDT 24
Peak memory 201796 kb
Host smart-e1855c3b-d3b9-4b87-a54b-e2cd86341c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380732183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.1380732183
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3178283320
Short name T236
Test name
Test status
Simulation time 2741261106 ps
CPU time 2.57 seconds
Started Jul 02 07:50:18 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 201516 kb
Host smart-a6d503b7-cae5-489c-b4a6-25af54ea9f30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178283320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.3178283320
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.787596266
Short name T80
Test name
Test status
Simulation time 193507507905 ps
CPU time 162.24 seconds
Started Jul 02 07:50:17 AM PDT 24
Finished Jul 02 07:53:00 AM PDT 24
Peak memory 201584 kb
Host smart-b485cf6b-063f-4a58-a33b-2d233d7a00d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787596266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl
_edge_detect.787596266
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1041062220
Short name T411
Test name
Test status
Simulation time 2609055726 ps
CPU time 7 seconds
Started Jul 02 07:50:12 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 201620 kb
Host smart-dc19f86f-4c94-46ff-9da0-397e34bc75a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041062220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1041062220
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1394563945
Short name T647
Test name
Test status
Simulation time 2463320218 ps
CPU time 7.48 seconds
Started Jul 02 07:50:09 AM PDT 24
Finished Jul 02 07:50:19 AM PDT 24
Peak memory 201512 kb
Host smart-dac235d9-6988-4e39-b885-650bb1479c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394563945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1394563945
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1493776478
Short name T478
Test name
Test status
Simulation time 2064957799 ps
CPU time 5.45 seconds
Started Jul 02 07:50:16 AM PDT 24
Finished Jul 02 07:50:22 AM PDT 24
Peak memory 201408 kb
Host smart-26fd37f8-6f65-43a5-9d50-593e63e26a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493776478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.1493776478
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3698389694
Short name T596
Test name
Test status
Simulation time 2517146630 ps
CPU time 3.94 seconds
Started Jul 02 07:50:19 AM PDT 24
Finished Jul 02 07:50:24 AM PDT 24
Peak memory 201512 kb
Host smart-92039a06-763d-49a6-8240-aa69cda09cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698389694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.3698389694
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.1474304906
Short name T473
Test name
Test status
Simulation time 2157833225 ps
CPU time 1.32 seconds
Started Jul 02 07:50:13 AM PDT 24
Finished Jul 02 07:50:16 AM PDT 24
Peak memory 201452 kb
Host smart-1c0d64d7-2b60-4206-a976-2dd084c5dcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474304906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.1474304906
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1392921449
Short name T43
Test name
Test status
Simulation time 9981893504 ps
CPU time 27.23 seconds
Started Jul 02 07:50:21 AM PDT 24
Finished Jul 02 07:50:50 AM PDT 24
Peak memory 201564 kb
Host smart-7c3f81e2-8f78-4415-a991-d4f935ead22d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392921449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1392921449
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2699930701
Short name T131
Test name
Test status
Simulation time 6506826431 ps
CPU time 3.84 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 201516 kb
Host smart-c6461e53-db00-4971-b1c8-6800f93ad3bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699930701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.2699930701
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4027581147
Short name T332
Test name
Test status
Simulation time 107820086751 ps
CPU time 68.32 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:53:04 AM PDT 24
Peak memory 201852 kb
Host smart-cdc05a51-896c-4418-a84e-53d62abd5d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027581147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.4027581147
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2319623087
Short name T82
Test name
Test status
Simulation time 60212836569 ps
CPU time 145.91 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:54:21 AM PDT 24
Peak memory 201900 kb
Host smart-ec7b6820-f481-426d-a79a-da8e929249ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319623087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2319623087
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2300582509
Short name T211
Test name
Test status
Simulation time 71054805110 ps
CPU time 30.21 seconds
Started Jul 02 07:51:54 AM PDT 24
Finished Jul 02 07:52:28 AM PDT 24
Peak memory 201852 kb
Host smart-3399b224-104d-492e-98ae-9263faadd107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300582509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.2300582509
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1905086103
Short name T393
Test name
Test status
Simulation time 112477022858 ps
CPU time 75.52 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 201864 kb
Host smart-3872710e-8825-4fa9-918c-06b5e27b53bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905086103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.1905086103
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.737908538
Short name T587
Test name
Test status
Simulation time 84348919207 ps
CPU time 37.83 seconds
Started Jul 02 07:51:44 AM PDT 24
Finished Jul 02 07:52:24 AM PDT 24
Peak memory 201820 kb
Host smart-e968e1ed-efbb-4155-a311-acc51ff40c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737908538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_wi
th_pre_cond.737908538
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1344531282
Short name T329
Test name
Test status
Simulation time 130934233296 ps
CPU time 346.03 seconds
Started Jul 02 07:51:58 AM PDT 24
Finished Jul 02 07:57:47 AM PDT 24
Peak memory 201792 kb
Host smart-1a975bd4-48cc-4506-bf96-fe661c96f0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344531282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.1344531282
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1494329444
Short name T525
Test name
Test status
Simulation time 67159830477 ps
CPU time 166.67 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:54:43 AM PDT 24
Peak memory 201784 kb
Host smart-0ac746bf-672f-44f1-a859-7494978f3dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494329444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.1494329444
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1779059517
Short name T685
Test name
Test status
Simulation time 25598130824 ps
CPU time 17.31 seconds
Started Jul 02 07:51:45 AM PDT 24
Finished Jul 02 07:52:05 AM PDT 24
Peak memory 201812 kb
Host smart-9f3da3b8-7310-4d74-91c2-365f29972b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779059517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.1779059517
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.543618965
Short name T521
Test name
Test status
Simulation time 2065316143 ps
CPU time 1.18 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 201592 kb
Host smart-145f4292-1fe4-4c10-86f7-90b229197c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543618965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test
.543618965
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.250169132
Short name T297
Test name
Test status
Simulation time 3515835956 ps
CPU time 5.05 seconds
Started Jul 02 07:50:22 AM PDT 24
Finished Jul 02 07:50:29 AM PDT 24
Peak memory 201616 kb
Host smart-e26a78bb-2ba4-4ec0-b648-f80e73c39516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250169132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.250169132
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.2648932196
Short name T103
Test name
Test status
Simulation time 53111011097 ps
CPU time 141.34 seconds
Started Jul 02 07:50:20 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 201788 kb
Host smart-1f1a59e4-35f8-465e-abbf-a12d05dcbed2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648932196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.2648932196
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1339989978
Short name T421
Test name
Test status
Simulation time 87030573856 ps
CPU time 52.34 seconds
Started Jul 02 07:50:19 AM PDT 24
Finished Jul 02 07:51:12 AM PDT 24
Peak memory 201868 kb
Host smart-b22e9e88-9b1f-4d7c-b480-940188c0e8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339989978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.1339989978
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.148075963
Short name T53
Test name
Test status
Simulation time 2910967874 ps
CPU time 2.22 seconds
Started Jul 02 07:50:18 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 201476 kb
Host smart-efc964b0-2496-4858-95f7-fadf5d88be6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148075963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ec_pwr_on_rst.148075963
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2083965941
Short name T114
Test name
Test status
Simulation time 2456236000 ps
CPU time 7.17 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:33 AM PDT 24
Peak memory 201508 kb
Host smart-fd15eca4-7b7e-4dc2-9d6a-fb69092c6b0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083965941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2083965941
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.406674544
Short name T121
Test name
Test status
Simulation time 2636826897 ps
CPU time 2.34 seconds
Started Jul 02 07:50:24 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 201520 kb
Host smart-80b0b8d3-01dd-4966-a380-01c60f321488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406674544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.406674544
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.816352973
Short name T193
Test name
Test status
Simulation time 2499532786 ps
CPU time 1.27 seconds
Started Jul 02 07:50:17 AM PDT 24
Finished Jul 02 07:50:19 AM PDT 24
Peak memory 201528 kb
Host smart-5d0a4c4e-82ba-4f27-be2a-559ba41c5db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816352973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.816352973
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2925395305
Short name T456
Test name
Test status
Simulation time 2030095878 ps
CPU time 4.58 seconds
Started Jul 02 07:50:16 AM PDT 24
Finished Jul 02 07:50:21 AM PDT 24
Peak memory 201424 kb
Host smart-fdeb59d1-d9db-482f-bbe4-c8042739b6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925395305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.2925395305
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2972823516
Short name T453
Test name
Test status
Simulation time 2525126087 ps
CPU time 2.44 seconds
Started Jul 02 07:50:13 AM PDT 24
Finished Jul 02 07:50:17 AM PDT 24
Peak memory 201556 kb
Host smart-5c8a73f2-30d3-4b61-b0b9-6d2f4f9765a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972823516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2972823516
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.2078573174
Short name T774
Test name
Test status
Simulation time 2150308461 ps
CPU time 1.66 seconds
Started Jul 02 07:50:17 AM PDT 24
Finished Jul 02 07:50:19 AM PDT 24
Peak memory 201492 kb
Host smart-7b582d5b-dea3-46ac-b996-a4f807c293d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078573174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2078573174
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3350615128
Short name T74
Test name
Test status
Simulation time 29052692338 ps
CPU time 66.74 seconds
Started Jul 02 07:50:27 AM PDT 24
Finished Jul 02 07:51:35 AM PDT 24
Peak memory 201960 kb
Host smart-9ac516b1-ad37-496b-ace9-1342024f0b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350615128 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.3350615128
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4145034052
Short name T274
Test name
Test status
Simulation time 3340916924 ps
CPU time 2.18 seconds
Started Jul 02 07:50:19 AM PDT 24
Finished Jul 02 07:50:22 AM PDT 24
Peak memory 201628 kb
Host smart-6aa163bf-c8bb-4f86-8d5d-d901522c8aa9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145034052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.4145034052
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2686413420
Short name T751
Test name
Test status
Simulation time 187234753065 ps
CPU time 224.42 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:55:39 AM PDT 24
Peak memory 201820 kb
Host smart-69264b47-6a23-4906-a2bc-88d2cb9cb280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686413420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2686413420
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2827896587
Short name T373
Test name
Test status
Simulation time 70802066881 ps
CPU time 181.3 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:54:57 AM PDT 24
Peak memory 201852 kb
Host smart-425ce0b9-7ad5-4775-b1ae-9d2011937f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827896587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.2827896587
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2994897804
Short name T140
Test name
Test status
Simulation time 82687099537 ps
CPU time 38.74 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:52:42 AM PDT 24
Peak memory 201804 kb
Host smart-809b6447-4b69-495a-a298-2d2e492d4f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994897804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2994897804
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2451678340
Short name T752
Test name
Test status
Simulation time 58373812876 ps
CPU time 38.57 seconds
Started Jul 02 07:51:52 AM PDT 24
Finished Jul 02 07:52:39 AM PDT 24
Peak memory 201720 kb
Host smart-9c380239-280f-49b7-b968-4328e4b7de62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451678340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.2451678340
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1764850908
Short name T756
Test name
Test status
Simulation time 48941403097 ps
CPU time 32.05 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:52:25 AM PDT 24
Peak memory 201752 kb
Host smart-3db49daf-8501-4b78-933e-2501a71b03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764850908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.1764850908
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1901583507
Short name T202
Test name
Test status
Simulation time 25880814470 ps
CPU time 10.97 seconds
Started Jul 02 07:51:57 AM PDT 24
Finished Jul 02 07:52:11 AM PDT 24
Peak memory 201820 kb
Host smart-5a80195e-2d05-4ab9-a6d1-d8dffdaecbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901583507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.1901583507
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3487497343
Short name T381
Test name
Test status
Simulation time 71242723462 ps
CPU time 44.42 seconds
Started Jul 02 07:51:55 AM PDT 24
Finished Jul 02 07:52:43 AM PDT 24
Peak memory 201940 kb
Host smart-c3c3d44d-0408-4c27-af45-1ceb6de0d288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487497343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.3487497343
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1765026418
Short name T95
Test name
Test status
Simulation time 42667901429 ps
CPU time 104.81 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:53:41 AM PDT 24
Peak memory 201904 kb
Host smart-715d4654-aa31-4d4b-a986-58d70d7041ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765026418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.1765026418
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2479405647
Short name T247
Test name
Test status
Simulation time 25857326398 ps
CPU time 17.4 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:12 AM PDT 24
Peak memory 201932 kb
Host smart-7f1fbbb1-84f0-47fe-9380-85a3bc73c856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479405647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.2479405647
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.1448201737
Short name T573
Test name
Test status
Simulation time 2049209101 ps
CPU time 1.49 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:26 AM PDT 24
Peak memory 201560 kb
Host smart-2ff25466-38ef-44cd-a350-c3181b897e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448201737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.1448201737
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2099768329
Short name T520
Test name
Test status
Simulation time 3477478855 ps
CPU time 2.63 seconds
Started Jul 02 07:50:21 AM PDT 24
Finished Jul 02 07:50:25 AM PDT 24
Peak memory 201568 kb
Host smart-d60b18b0-d45a-4a5a-b72a-661088d5557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099768329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2099768329
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.2172865741
Short name T364
Test name
Test status
Simulation time 156015318888 ps
CPU time 109.95 seconds
Started Jul 02 07:50:25 AM PDT 24
Finished Jul 02 07:52:17 AM PDT 24
Peak memory 201676 kb
Host smart-0da85ffe-93c1-4b47-bcca-d7c25ce27606
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172865741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.2172865741
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2970932389
Short name T451
Test name
Test status
Simulation time 94576485662 ps
CPU time 237.64 seconds
Started Jul 02 07:50:27 AM PDT 24
Finished Jul 02 07:54:26 AM PDT 24
Peak memory 201792 kb
Host smart-e57e75f7-6216-4aa5-8d19-0c844ecdd645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970932389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.2970932389
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1933808691
Short name T294
Test name
Test status
Simulation time 3350934951 ps
CPU time 1.24 seconds
Started Jul 02 07:50:24 AM PDT 24
Finished Jul 02 07:50:27 AM PDT 24
Peak memory 201492 kb
Host smart-9e07f5cb-1e2e-4231-a044-642dcd261708
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933808691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1933808691
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3357758187
Short name T254
Test name
Test status
Simulation time 2690184372 ps
CPU time 3.64 seconds
Started Jul 02 07:50:25 AM PDT 24
Finished Jul 02 07:50:31 AM PDT 24
Peak memory 201552 kb
Host smart-6adfbd0b-db69-4e70-a253-288eb4962f54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357758187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.3357758187
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.746413620
Short name T409
Test name
Test status
Simulation time 2616493455 ps
CPU time 4.22 seconds
Started Jul 02 07:50:25 AM PDT 24
Finished Jul 02 07:50:31 AM PDT 24
Peak memory 201184 kb
Host smart-2c2d3763-ad3c-45f7-89b5-5211c5e411dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746413620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.746413620
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.991807884
Short name T607
Test name
Test status
Simulation time 2466116220 ps
CPU time 2.72 seconds
Started Jul 02 07:50:25 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 201140 kb
Host smart-6a2e550e-6ffe-43c6-b145-ffc1ec5515b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991807884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.991807884
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.940056666
Short name T208
Test name
Test status
Simulation time 2258620751 ps
CPU time 2.03 seconds
Started Jul 02 07:50:25 AM PDT 24
Finished Jul 02 07:50:29 AM PDT 24
Peak memory 201532 kb
Host smart-cc85bbca-6da7-48ea-a5df-828729bc065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940056666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.940056666
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2164494124
Short name T600
Test name
Test status
Simulation time 2509203302 ps
CPU time 7.33 seconds
Started Jul 02 07:50:19 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 201600 kb
Host smart-4c44ea40-a7a2-48a8-a6e5-1899a3f3d5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164494124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2164494124
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.3178752625
Short name T502
Test name
Test status
Simulation time 2129970888 ps
CPU time 2.05 seconds
Started Jul 02 07:50:20 AM PDT 24
Finished Jul 02 07:50:23 AM PDT 24
Peak memory 201424 kb
Host smart-f81aeb99-0d9e-41a3-91c9-a3cf766e0cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178752625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.3178752625
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.3603602723
Short name T548
Test name
Test status
Simulation time 13489917935 ps
CPU time 32.93 seconds
Started Jul 02 07:50:25 AM PDT 24
Finished Jul 02 07:51:00 AM PDT 24
Peak memory 201504 kb
Host smart-20fbda33-ecb2-442e-9910-ead7605136b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603602723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.3603602723
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4176374063
Short name T178
Test name
Test status
Simulation time 84485774272 ps
CPU time 50.42 seconds
Started Jul 02 07:50:24 AM PDT 24
Finished Jul 02 07:51:17 AM PDT 24
Peak memory 210032 kb
Host smart-caccb28b-91a7-4f66-8aaa-154b8f1cc18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176374063 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.4176374063
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2129422796
Short name T89
Test name
Test status
Simulation time 6684693208 ps
CPU time 2.26 seconds
Started Jul 02 07:50:17 AM PDT 24
Finished Jul 02 07:50:20 AM PDT 24
Peak memory 201504 kb
Host smart-00351dc3-51fb-4b2a-81fc-c17e32d53e13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129422796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.2129422796
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.751491142
Short name T519
Test name
Test status
Simulation time 74416146830 ps
CPU time 183.66 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:55:07 AM PDT 24
Peak memory 201808 kb
Host smart-0b12acf5-c0c9-4299-8b16-94179c1631d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751491142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_wi
th_pre_cond.751491142
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1892063649
Short name T745
Test name
Test status
Simulation time 102527069083 ps
CPU time 78.77 seconds
Started Jul 02 07:51:49 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 201796 kb
Host smart-7d5711ac-61ff-40c0-8fb3-6bdd0ba2340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892063649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.1892063649
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1531710210
Short name T110
Test name
Test status
Simulation time 106740679936 ps
CPU time 59.39 seconds
Started Jul 02 07:51:50 AM PDT 24
Finished Jul 02 07:52:55 AM PDT 24
Peak memory 201860 kb
Host smart-2ec5c079-42f5-4b11-b27d-ba1fd7194ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531710210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1531710210
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1138748585
Short name T334
Test name
Test status
Simulation time 73275125273 ps
CPU time 23.32 seconds
Started Jul 02 07:51:52 AM PDT 24
Finished Jul 02 07:52:20 AM PDT 24
Peak memory 201944 kb
Host smart-0fb9ef31-e2e2-4d96-80fd-13e0252efb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138748585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.1138748585
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2772830318
Short name T28
Test name
Test status
Simulation time 61417122579 ps
CPU time 14.41 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:52:17 AM PDT 24
Peak memory 202084 kb
Host smart-e51e9f53-60e4-41e0-82a6-6a6b15db39a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772830318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.2772830318
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.564227984
Short name T560
Test name
Test status
Simulation time 27602145028 ps
CPU time 20.91 seconds
Started Jul 02 07:51:52 AM PDT 24
Finished Jul 02 07:52:17 AM PDT 24
Peak memory 201792 kb
Host smart-85d40d48-6fe6-4ebe-8cd5-65cc799091ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564227984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_wi
th_pre_cond.564227984
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.228572272
Short name T394
Test name
Test status
Simulation time 35801866161 ps
CPU time 26.93 seconds
Started Jul 02 07:52:00 AM PDT 24
Finished Jul 02 07:52:29 AM PDT 24
Peak memory 201832 kb
Host smart-cd271814-3679-4d0c-a2dd-0956afac6245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228572272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_wi
th_pre_cond.228572272
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.500813548
Short name T494
Test name
Test status
Simulation time 2012058361 ps
CPU time 5.82 seconds
Started Jul 02 07:50:29 AM PDT 24
Finished Jul 02 07:50:37 AM PDT 24
Peak memory 201536 kb
Host smart-45820602-8658-4ea2-b656-a1fa2b2ba132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500813548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test
.500813548
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1198520248
Short name T225
Test name
Test status
Simulation time 3665414378 ps
CPU time 8.58 seconds
Started Jul 02 07:50:25 AM PDT 24
Finished Jul 02 07:50:36 AM PDT 24
Peak memory 201480 kb
Host smart-48efb1da-bd11-4040-94d5-2691206dbb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198520248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.1198520248
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.1554278569
Short name T708
Test name
Test status
Simulation time 168504677879 ps
CPU time 395.07 seconds
Started Jul 02 07:50:29 AM PDT 24
Finished Jul 02 07:57:06 AM PDT 24
Peak memory 201700 kb
Host smart-d143bb87-fda0-4a3f-a8fa-edc394b325ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554278569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.1554278569
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.4017192656
Short name T581
Test name
Test status
Simulation time 96609335320 ps
CPU time 129.92 seconds
Started Jul 02 07:50:29 AM PDT 24
Finished Jul 02 07:52:41 AM PDT 24
Peak memory 201892 kb
Host smart-6bc4751c-1a47-4f3c-8708-3c2a80b73bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017192656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.4017192656
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3228825739
Short name T656
Test name
Test status
Simulation time 4843862493 ps
CPU time 9.84 seconds
Started Jul 02 07:50:34 AM PDT 24
Finished Jul 02 07:50:46 AM PDT 24
Peak memory 201500 kb
Host smart-afe108bb-5874-4747-b1cf-f1d97eb0565a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228825739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3228825739
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.53910208
Short name T629
Test name
Test status
Simulation time 2631151984 ps
CPU time 2.51 seconds
Started Jul 02 07:50:26 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 201876 kb
Host smart-79a89102-8ff4-476e-a019-53ee770b9c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53910208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.53910208
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2988533018
Short name T695
Test name
Test status
Simulation time 2509514879 ps
CPU time 1.2 seconds
Started Jul 02 07:50:25 AM PDT 24
Finished Jul 02 07:50:28 AM PDT 24
Peak memory 201528 kb
Host smart-51d3baf5-3793-4946-b625-bc0d5109e9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988533018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.2988533018
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.798689719
Short name T450
Test name
Test status
Simulation time 2093782038 ps
CPU time 2.59 seconds
Started Jul 02 07:50:27 AM PDT 24
Finished Jul 02 07:50:31 AM PDT 24
Peak memory 201516 kb
Host smart-196f411c-73c4-46ba-b832-c871ca442a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798689719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.798689719
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3625182519
Short name T65
Test name
Test status
Simulation time 2513562770 ps
CPU time 7.27 seconds
Started Jul 02 07:50:23 AM PDT 24
Finished Jul 02 07:50:32 AM PDT 24
Peak memory 201616 kb
Host smart-6b62f0be-035d-4429-b7fb-5f42cd5d570b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625182519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3625182519
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.122709080
Short name T780
Test name
Test status
Simulation time 2198959440 ps
CPU time 1.09 seconds
Started Jul 02 07:50:28 AM PDT 24
Finished Jul 02 07:50:30 AM PDT 24
Peak memory 201460 kb
Host smart-32634db8-d61f-4b10-ad65-04ddf4291d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122709080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.122709080
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.886144170
Short name T292
Test name
Test status
Simulation time 14316806490 ps
CPU time 10.11 seconds
Started Jul 02 07:50:28 AM PDT 24
Finished Jul 02 07:50:40 AM PDT 24
Peak memory 201640 kb
Host smart-717f4a77-a20f-4f14-a562-bf8a033f91f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886144170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_str
ess_all.886144170
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2555172691
Short name T113
Test name
Test status
Simulation time 66872803342 ps
CPU time 175.18 seconds
Started Jul 02 07:52:00 AM PDT 24
Finished Jul 02 07:54:57 AM PDT 24
Peak memory 201916 kb
Host smart-a9d29982-243c-4660-a987-593fa157bda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555172691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.2555172691
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2253178689
Short name T267
Test name
Test status
Simulation time 23081012932 ps
CPU time 61.42 seconds
Started Jul 02 07:52:10 AM PDT 24
Finished Jul 02 07:53:12 AM PDT 24
Peak memory 201820 kb
Host smart-b14bb184-0eac-4b8f-9f90-aa3ddd4945cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253178689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.2253178689
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2945610293
Short name T377
Test name
Test status
Simulation time 64701219420 ps
CPU time 172.52 seconds
Started Jul 02 07:51:54 AM PDT 24
Finished Jul 02 07:54:51 AM PDT 24
Peak memory 201772 kb
Host smart-9d3b9f52-5ba4-421a-89a7-398cca33f397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945610293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.2945610293
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3821095454
Short name T477
Test name
Test status
Simulation time 31891370712 ps
CPU time 85.99 seconds
Started Jul 02 07:51:53 AM PDT 24
Finished Jul 02 07:53:23 AM PDT 24
Peak memory 201884 kb
Host smart-3414da50-5ea9-4d91-87c6-d42dff4904e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821095454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3821095454
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3018420730
Short name T42
Test name
Test status
Simulation time 35245698676 ps
CPU time 89.06 seconds
Started Jul 02 07:51:58 AM PDT 24
Finished Jul 02 07:53:29 AM PDT 24
Peak memory 201800 kb
Host smart-e23fb483-6721-435e-bc54-7c35ab0ea5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018420730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.3018420730
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3044587550
Short name T161
Test name
Test status
Simulation time 78404858963 ps
CPU time 55.54 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:52:58 AM PDT 24
Peak memory 201880 kb
Host smart-d3ebc405-22c1-44cc-a321-8b4681906ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044587550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.3044587550
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.280446617
Short name T83
Test name
Test status
Simulation time 30131063528 ps
CPU time 74.16 seconds
Started Jul 02 07:51:51 AM PDT 24
Finished Jul 02 07:53:10 AM PDT 24
Peak memory 201860 kb
Host smart-8c9a830a-d3d9-49a2-98ec-e735e311b607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280446617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_wi
th_pre_cond.280446617
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1369313966
Short name T288
Test name
Test status
Simulation time 47569300154 ps
CPU time 125.61 seconds
Started Jul 02 07:52:01 AM PDT 24
Finished Jul 02 07:54:08 AM PDT 24
Peak memory 201900 kb
Host smart-3e18bffc-7fa8-4b5f-8e12-07f6176d162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369313966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.1369313966
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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