Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T310 |
1 |
|
T131 |
2 |
auto[1] |
3 |
1 |
|
|
T310 |
2 |
|
T131 |
1 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2 |
1 |
|
|
T310 |
1 |
|
T131 |
1 |
auto[1] |
4 |
1 |
|
|
T310 |
2 |
|
T131 |
2 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3 |
1 |
|
|
T310 |
2 |
|
T131 |
1 |
auto[1] |
3 |
1 |
|
|
T310 |
1 |
|
T131 |
2 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4 |
1 |
|
|
T310 |
3 |
|
T131 |
1 |
auto[1] |
2 |
1 |
|
|
T131 |
2 |
|
- |
- |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4 |
1 |
|
|
T310 |
2 |
|
T131 |
2 |
auto[1] |
2 |
1 |
|
|
T310 |
1 |
|
T131 |
1 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1 |
1 |
|
|
T310 |
1 |
|
- |
- |
auto[1] |
5 |
1 |
|
|
T310 |
2 |
|
T131 |
3 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cross_key0_out_sel_value
Uncovered bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[1] |
2 |
1 |
|
|
T310 |
1 |
|
T131 |
1 |
auto[1] |
auto[0] |
3 |
1 |
|
|
T310 |
1 |
|
T131 |
2 |
auto[1] |
auto[1] |
1 |
1 |
|
|
T310 |
1 |
|
- |
- |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2 |
1 |
|
|
T310 |
2 |
|
- |
- |
auto[0] |
auto[1] |
2 |
1 |
|
|
T310 |
1 |
|
T131 |
1 |
auto[1] |
auto[0] |
1 |
1 |
|
|
T131 |
1 |
|
- |
- |
auto[1] |
auto[1] |
1 |
1 |
|
|
T131 |
1 |
|
- |
- |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cross_key2_out_sel_value
Uncovered bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | NUMBER | STATUS |
[auto[0]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
1 |
1 |
|
|
T310 |
1 |
|
- |
- |
auto[1] |
auto[0] |
3 |
1 |
|
|
T310 |
1 |
|
T131 |
2 |
auto[1] |
auto[1] |
2 |
1 |
|
|
T310 |
1 |
|
T131 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
120 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T8 |
2 |
auto[1] |
111 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T8 |
1 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
105 |
1 |
|
|
T3 |
2 |
|
T8 |
1 |
|
T9 |
2 |
auto[1] |
126 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T8 |
2 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
112 |
1 |
|
|
T1 |
3 |
|
T3 |
2 |
|
T35 |
3 |
auto[1] |
119 |
1 |
|
|
T3 |
1 |
|
T8 |
3 |
|
T9 |
3 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
135 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T8 |
2 |
auto[1] |
96 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T8 |
1 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
119 |
1 |
|
|
T1 |
2 |
|
T3 |
3 |
|
T8 |
2 |
auto[1] |
112 |
1 |
|
|
T1 |
1 |
|
T8 |
1 |
|
T9 |
1 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
116 |
1 |
|
|
T1 |
1 |
|
T3 |
3 |
|
T8 |
1 |
auto[1] |
115 |
1 |
|
|
T1 |
2 |
|
T8 |
2 |
|
T9 |
3 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
53 |
1 |
|
|
T3 |
1 |
|
T35 |
1 |
|
T37 |
1 |
auto[0] |
auto[1] |
52 |
1 |
|
|
T3 |
1 |
|
T8 |
1 |
|
T9 |
2 |
auto[1] |
auto[0] |
67 |
1 |
|
|
T1 |
2 |
|
T8 |
2 |
|
T9 |
1 |
auto[1] |
auto[1] |
59 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T35 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
63 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T35 |
1 |
auto[0] |
auto[1] |
72 |
1 |
|
|
T3 |
1 |
|
T8 |
2 |
|
T9 |
2 |
auto[1] |
auto[0] |
49 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T35 |
2 |
auto[1] |
auto[1] |
47 |
1 |
|
|
T8 |
1 |
|
T9 |
1 |
|
T36 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
61 |
1 |
|
|
T3 |
3 |
|
T8 |
1 |
|
T35 |
2 |
auto[0] |
auto[1] |
55 |
1 |
|
|
T1 |
1 |
|
T36 |
1 |
|
T40 |
1 |
auto[1] |
auto[0] |
58 |
1 |
|
|
T1 |
2 |
|
T8 |
1 |
|
T9 |
2 |
auto[1] |
auto[1] |
57 |
1 |
|
|
T8 |
1 |
|
T9 |
1 |
|
T35 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14 |
1 |
|
|
T307 |
2 |
|
T72 |
1 |
|
T386 |
1 |
auto[1] |
19 |
1 |
|
|
T9 |
3 |
|
T307 |
1 |
|
T386 |
2 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20 |
1 |
|
|
T9 |
2 |
|
T72 |
1 |
|
T386 |
2 |
auto[1] |
13 |
1 |
|
|
T9 |
1 |
|
T307 |
3 |
|
T386 |
1 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16 |
1 |
|
|
T307 |
1 |
|
T72 |
1 |
|
T386 |
2 |
auto[1] |
17 |
1 |
|
|
T9 |
3 |
|
T307 |
2 |
|
T386 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
15 |
1 |
|
|
T9 |
3 |
|
T307 |
1 |
|
T164 |
1 |
auto[1] |
18 |
1 |
|
|
T307 |
2 |
|
T72 |
1 |
|
T386 |
3 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16 |
1 |
|
|
T9 |
2 |
|
T307 |
1 |
|
T386 |
1 |
auto[1] |
17 |
1 |
|
|
T9 |
1 |
|
T307 |
2 |
|
T72 |
1 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
19 |
1 |
|
|
T9 |
2 |
|
T307 |
2 |
|
T72 |
1 |
auto[1] |
14 |
1 |
|
|
T9 |
1 |
|
T307 |
1 |
|
T386 |
1 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
9 |
1 |
|
|
T72 |
1 |
|
T308 |
2 |
|
T310 |
1 |
auto[0] |
auto[1] |
11 |
1 |
|
|
T9 |
2 |
|
T386 |
2 |
|
T164 |
2 |
auto[1] |
auto[0] |
5 |
1 |
|
|
T307 |
2 |
|
T386 |
1 |
|
T308 |
1 |
auto[1] |
auto[1] |
8 |
1 |
|
|
T9 |
1 |
|
T307 |
1 |
|
T164 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
7 |
1 |
|
|
T307 |
1 |
|
T308 |
1 |
|
T310 |
2 |
auto[0] |
auto[1] |
8 |
1 |
|
|
T9 |
3 |
|
T164 |
1 |
|
T137 |
1 |
auto[1] |
auto[0] |
9 |
1 |
|
|
T72 |
1 |
|
T386 |
2 |
|
T164 |
2 |
auto[1] |
auto[1] |
9 |
1 |
|
|
T307 |
2 |
|
T386 |
1 |
|
T308 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
12 |
1 |
|
|
T9 |
1 |
|
T307 |
1 |
|
T386 |
1 |
auto[0] |
auto[1] |
7 |
1 |
|
|
T9 |
1 |
|
T307 |
1 |
|
T72 |
1 |
auto[1] |
auto[0] |
4 |
1 |
|
|
T9 |
1 |
|
T164 |
1 |
|
T308 |
1 |
auto[1] |
auto[1] |
10 |
1 |
|
|
T307 |
1 |
|
T386 |
1 |
|
T164 |
1 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7 |
1 |
|
|
T9 |
1 |
|
T322 |
2 |
|
T131 |
2 |
auto[1] |
7 |
1 |
|
|
T9 |
2 |
|
T72 |
3 |
|
T322 |
1 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7 |
1 |
|
|
T9 |
1 |
|
T72 |
1 |
|
T322 |
2 |
auto[1] |
7 |
1 |
|
|
T9 |
2 |
|
T72 |
2 |
|
T322 |
1 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7 |
1 |
|
|
T9 |
2 |
|
T72 |
1 |
|
T322 |
2 |
auto[1] |
7 |
1 |
|
|
T9 |
1 |
|
T72 |
2 |
|
T322 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7 |
1 |
|
|
T72 |
2 |
|
T322 |
2 |
|
T131 |
2 |
auto[1] |
7 |
1 |
|
|
T9 |
3 |
|
T72 |
1 |
|
T322 |
1 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6 |
1 |
|
|
T72 |
1 |
|
T322 |
1 |
|
T131 |
2 |
auto[1] |
8 |
1 |
|
|
T9 |
3 |
|
T72 |
2 |
|
T322 |
2 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8 |
1 |
|
|
T9 |
2 |
|
T72 |
2 |
|
T322 |
1 |
auto[1] |
6 |
1 |
|
|
T9 |
1 |
|
T72 |
1 |
|
T322 |
2 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
3 |
1 |
|
|
T322 |
1 |
|
T131 |
1 |
|
T197 |
1 |
auto[0] |
auto[1] |
4 |
1 |
|
|
T9 |
1 |
|
T72 |
1 |
|
T322 |
1 |
auto[1] |
auto[0] |
4 |
1 |
|
|
T9 |
1 |
|
T322 |
1 |
|
T131 |
1 |
auto[1] |
auto[1] |
3 |
1 |
|
|
T9 |
1 |
|
T72 |
2 |
|
- |
- |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
3 |
1 |
|
|
T322 |
2 |
|
T131 |
1 |
|
- |
- |
auto[0] |
auto[1] |
4 |
1 |
|
|
T72 |
2 |
|
T131 |
1 |
|
T197 |
1 |
auto[1] |
auto[0] |
4 |
1 |
|
|
T9 |
2 |
|
T72 |
1 |
|
T197 |
1 |
auto[1] |
auto[1] |
3 |
1 |
|
|
T9 |
1 |
|
T322 |
1 |
|
T197 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2 |
1 |
|
|
T131 |
1 |
|
T197 |
1 |
|
- |
- |
auto[0] |
auto[1] |
6 |
1 |
|
|
T9 |
2 |
|
T72 |
2 |
|
T322 |
1 |
auto[1] |
auto[0] |
4 |
1 |
|
|
T72 |
1 |
|
T322 |
1 |
|
T131 |
1 |
auto[1] |
auto[1] |
2 |
1 |
|
|
T9 |
1 |
|
T322 |
1 |
|
- |
- |