SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_combo_detect_action_cg_0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_1 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_2 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_detect_action_cg_3 | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_bat_disable | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_interrupt | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_ac_present_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key0_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key1_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_key2_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_precondition_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_in_sel | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_rst_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 509 | 1 | T1 | 14 | T16 | 5 | T4 | 7 | ||||
auto[1] | 176 | 1 | T1 | 4 | T16 | 5 | T42 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 350 | 1 | T1 | 9 | T16 | 10 | T4 | 6 | ||||
auto[1] | 335 | 1 | T1 | 9 | T4 | 1 | T42 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 306 | 1 | T1 | 4 | T16 | 10 | T4 | 6 | ||||
auto[1] | 379 | 1 | T1 | 14 | T4 | 1 | T10 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 323 | 1 | T1 | 9 | T16 | 10 | T4 | 1 | ||||
auto[1] | 362 | 1 | T1 | 9 | T4 | 6 | T11 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 538 | 1 | T1 | 18 | T16 | 10 | T4 | 7 | ||||
auto[1] | 147 | 1 | T10 | 6 | T39 | 10 | T33 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 502 | 1 | T1 | 9 | T16 | 10 | T4 | 7 | ||||
auto[1] | 183 | 1 | T1 | 9 | T11 | 2 | T39 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 530 | 1 | T1 | 13 | T16 | 10 | T4 | 5 | ||||
auto[1] | 155 | 1 | T1 | 5 | T4 | 2 | T10 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 656 | 1 | T1 | 18 | T16 | 10 | T4 | 5 | ||||
auto[1] | 29 | 1 | T4 | 2 | T11 | 2 | T236 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 614 | 1 | T1 | 18 | T16 | 10 | T4 | 5 | ||||
auto[1] | 71 | 1 | T4 | 2 | T11 | 2 | T236 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 637 | 1 | T1 | 18 | T16 | 10 | T4 | 5 | ||||
auto[1] | 48 | 1 | T4 | 2 | T42 | 7 | T113 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 607 | 1 | T1 | 18 | T16 | 5 | T4 | 7 | ||||
auto[1] | 78 | 1 | T16 | 5 | T11 | 2 | T39 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 613 | 1 | T1 | 18 | T16 | 10 | T4 | 7 | ||||
auto[1] | 72 | 1 | T39 | 10 | T236 | 1 | T267 | 14 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 522 | 1 | T1 | 9 | T16 | 10 | T4 | 7 | ||||
auto[1] | 163 | 1 | T1 | 9 | T11 | 2 | T21 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 316 | 1 | T1 | 14 | T16 | 4 | T4 | 5 | ||||
auto[1] | 369 | 1 | T1 | 4 | T16 | 6 | T4 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 543 | 1 | T1 | 2 | T16 | 10 | T4 | 7 | ||||
auto[1] | 149 | 1 | T1 | 4 | T39 | 6 | T21 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 391 | 1 | T1 | 4 | T16 | 10 | T4 | 6 | ||||
auto[1] | 301 | 1 | T1 | 2 | T4 | 1 | T37 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 348 | 1 | T1 | 2 | T16 | 10 | T4 | 6 | ||||
auto[1] | 344 | 1 | T1 | 4 | T4 | 1 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 330 | 1 | T1 | 4 | T16 | 10 | T4 | 1 | ||||
auto[1] | 362 | 1 | T1 | 2 | T4 | 6 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 533 | 1 | T1 | 4 | T16 | 10 | T4 | 4 | ||||
auto[1] | 159 | 1 | T1 | 2 | T4 | 3 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 528 | 1 | T1 | 2 | T16 | 10 | T4 | 4 | ||||
auto[1] | 164 | 1 | T1 | 4 | T4 | 3 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 503 | 1 | T1 | 4 | T16 | 10 | T4 | 7 | ||||
auto[1] | 189 | 1 | T1 | 2 | T10 | 1 | T42 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 653 | 1 | T1 | 6 | T16 | 9 | T4 | 4 | ||||
auto[1] | 39 | 1 | T16 | 1 | T4 | 3 | T38 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 609 | 1 | T1 | 6 | T16 | 9 | T4 | 7 | ||||
auto[1] | 83 | 1 | T16 | 1 | T39 | 6 | T42 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 614 | 1 | T1 | 6 | T16 | 10 | T4 | 7 | ||||
auto[1] | 78 | 1 | T38 | 1 | T42 | 4 | T113 | 11 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 644 | 1 | T1 | 6 | T16 | 9 | T4 | 4 | ||||
auto[1] | 48 | 1 | T16 | 1 | T4 | 3 | T38 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 614 | 1 | T1 | 6 | T16 | 10 | T4 | 7 | ||||
auto[1] | 78 | 1 | T39 | 6 | T235 | 1 | T85 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 550 | 1 | T1 | 4 | T16 | 9 | T4 | 7 | ||||
auto[1] | 142 | 1 | T1 | 2 | T16 | 1 | T10 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 296 | 1 | T1 | 2 | T16 | 4 | T4 | 5 | ||||
auto[1] | 396 | 1 | T1 | 4 | T16 | 6 | T4 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 609 | 1 | T1 | 8 | T16 | 10 | T4 | 7 | ||||
auto[1] | 121 | 1 | T1 | 2 | T42 | 7 | T73 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 401 | 1 | T16 | 10 | T4 | 6 | T25 | 3 | ||||
auto[1] | 329 | 1 | T1 | 10 | T4 | 1 | T10 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 393 | 1 | T1 | 10 | T16 | 10 | T4 | 6 | ||||
auto[1] | 337 | 1 | T4 | 1 | T9 | 2 | T10 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 392 | 1 | T1 | 2 | T16 | 10 | T4 | 1 | ||||
auto[1] | 338 | 1 | T1 | 8 | T4 | 6 | T9 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 548 | 1 | T1 | 8 | T16 | 10 | T25 | 3 | ||||
auto[1] | 182 | 1 | T1 | 2 | T4 | 7 | T42 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 551 | 1 | T1 | 2 | T16 | 2 | T4 | 7 | ||||
auto[1] | 179 | 1 | T1 | 8 | T16 | 8 | T37 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 475 | 1 | T1 | 8 | T16 | 10 | T10 | 8 | ||||
auto[1] | 255 | 1 | T1 | 2 | T4 | 7 | T25 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 669 | 1 | T1 | 10 | T16 | 10 | T9 | 2 | ||||
auto[1] | 61 | 1 | T4 | 7 | T25 | 3 | T267 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 631 | 1 | T1 | 10 | T16 | 2 | T4 | 7 | ||||
auto[1] | 99 | 1 | T16 | 8 | T73 | 1 | T74 | 15 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 676 | 1 | T1 | 10 | T16 | 10 | T25 | 3 | ||||
auto[1] | 54 | 1 | T4 | 7 | T85 | 2 | T267 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 681 | 1 | T1 | 10 | T16 | 10 | T4 | 7 | ||||
auto[1] | 49 | 1 | T42 | 7 | T85 | 2 | T370 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 665 | 1 | T1 | 10 | T16 | 10 | T4 | 7 | ||||
auto[1] | 65 | 1 | T43 | 1 | T85 | 2 | T74 | 15 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 565 | 1 | T1 | 10 | T16 | 2 | T25 | 3 | ||||
auto[1] | 165 | 1 | T16 | 8 | T4 | 7 | T9 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 341 | 1 | T1 | 8 | T16 | 4 | T4 | 5 | ||||
auto[1] | 389 | 1 | T1 | 2 | T16 | 6 | T4 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 538 | 1 | T1 | 5 | T16 | 10 | T4 | 7 | ||||
auto[1] | 169 | 1 | T1 | 4 | T10 | 3 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 389 | 1 | T1 | 9 | T16 | 10 | T4 | 6 | ||||
auto[1] | 318 | 1 | T4 | 1 | T42 | 4 | T21 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 365 | 1 | T1 | 7 | T16 | 10 | T4 | 6 | ||||
auto[1] | 342 | 1 | T1 | 2 | T4 | 1 | T9 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 379 | 1 | T1 | 2 | T16 | 10 | T4 | 1 | ||||
auto[1] | 328 | 1 | T1 | 7 | T4 | 6 | T11 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 553 | 1 | T1 | 7 | T16 | 10 | T4 | 4 | ||||
auto[1] | 154 | 1 | T1 | 2 | T4 | 3 | T37 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 579 | 1 | T1 | 4 | T16 | 7 | T4 | 7 | ||||
auto[1] | 128 | 1 | T1 | 5 | T16 | 3 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 513 | 1 | T16 | 7 | T4 | 7 | T25 | 3 | ||||
auto[1] | 194 | 1 | T1 | 9 | T16 | 3 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 641 | 1 | T1 | 9 | T16 | 7 | T4 | 4 | ||||
auto[1] | 66 | 1 | T16 | 3 | T4 | 3 | T39 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 651 | 1 | T1 | 9 | T16 | 7 | T4 | 7 | ||||
auto[1] | 56 | 1 | T16 | 3 | T12 | 1 | T42 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 656 | 1 | T1 | 9 | T16 | 10 | T4 | 7 | ||||
auto[1] | 51 | 1 | T11 | 1 | T113 | 6 | T235 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 633 | 1 | T1 | 9 | T16 | 10 | T4 | 4 | ||||
auto[1] | 74 | 1 | T4 | 3 | T39 | 7 | T113 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 665 | 1 | T1 | 9 | T16 | 10 | T4 | 4 | ||||
auto[1] | 42 | 1 | T4 | 3 | T113 | 6 | T85 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 552 | 1 | T1 | 4 | T16 | 10 | T4 | 7 | ||||
auto[1] | 155 | 1 | T1 | 5 | T9 | 2 | T11 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 311 | 1 | T1 | 5 | T16 | 4 | T4 | 5 | ||||
auto[1] | 396 | 1 | T1 | 4 | T16 | 6 | T4 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |