Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2199

1

T1

29

T16

35

T4

28

auto[1]

615

1

T1

14

T16

5

T10

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2172

1

T1

37

T16

40

T4

15

auto[1]

642

1

T1

6

T4

13

T10

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2160

1

T1

17

T16

29

T4

25

auto[1]

654

1

T1

26

T16

11

T4

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2021

1

T1

25

T16

37

T4

19

auto[1]

793

1

T1

18

T16

3

T4

9

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2619

1

T1

43

T16

36

T4

13

auto[1]

195

1

T16

4

T4

15

T25

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2505

1

T1

43

T16

28

T4

26

auto[1]

309

1

T16

12

T4

2

T11

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2583

1

T1

43

T16

40

T4

19

auto[1]

231

1

T4

9

T11

1

T38

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2565

1

T1

43

T16

34

T4

22

auto[1]

249

1

T16

6

T4

6

T11

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2557

1

T1

43

T16

40

T4

25

auto[1]

257

1

T4

3

T39

16

T43

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2189

1

T1

27

T16

31

T4

21

auto[1]

625

1

T1

16

T16

9

T4

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1015	1			T1	43		T9	4		T10	18
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	29	1			T370	4		T371	6		T362	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	37	1			T43	1		T350	12		T234	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	35	1			T235	1		T87	8		T370	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	54	1			T16	5		T42	3		T236	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	37	1			T4	3		T39	7		T358	9
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	31	1			T39	10		T85	8		T370	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T4	3		T109	3		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	44	1			T11	1		T42	3		T113	10
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	11	1			T4	7		T372	1		T109	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	33	1			T267	28		T373	5		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	28	1			T113	10		T128	3		T75	7
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T38	1		T108	1		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	14	1			T113	5		T85	2		T358	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	3	1			T360	3		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	99	1			T16	4		T12	1		T43	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	11	1			T16	2		T247	2		T374	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	32	1			T74	15		T237	1		T128	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	13	1			T88	4		T248	4		T355	5
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	24	1			T237	3		T371	8		T345	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T16	1		T11	2		T375	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	11	1			T39	6		T85	2		T376	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T266	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	49	1			T128	2		T233	3		T358	26
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	16	1			T4	2		T377	2		T153	5
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T375	1		T345	2		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T267	6		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	1	1			T375	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

108

1

T16

5

T21

2

T33

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

125

1

T1

9

T16

1

T9

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

58

1

T21

1

T33

4

T59

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

148

1

T4

2

T33

3

T100

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

70

1

T1

2

T42

3

T113

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

101

1

T9

2

T11

1

T33

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T269

2

T144

4

T378

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

102

1

T1

8

T39

7

T85

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

75

1

T1

8

T39

6

T247

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T16

4

T11

2

T37

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T33

5

T240

4

T73

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

131

1

T1

5

T16

2

T37

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

25

1

T10

3

T12

1

T376

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T1

5

T191

7

T89

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T33

3

T344

2

T290

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

168

1

T4

3

T113

10

T85

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T42

3

T113

5

T191

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T21

1

T59

9

T131

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T37

2

T100

1

T240

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T10

6

T33

4

T235

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T1

4

T235

2

T347

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T1

2

T4

7

T349

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T191

2

T270

1

T246

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

69

1

T4

3

T39

10

T33

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T347

2

T144

1

T126

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T237

3

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T346

1

T245

3

T109

9

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T33

1

T68

4

T126

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T100

1

T167

1

T357

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T10

1

T33

1

T100

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T21

1

T245

1

T95

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded