Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1148

1

T6

10

T9

28

T47

14

auto[1]

1212

1

T6

10

T9

32

T47

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

548

1

T6

3

T9

12

T47

4

from_0to1

554

1

T6

4

T9

13

T47

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1185

1

T6

11

T9

31

T47

12

auto[1]

1175

1

T6

9

T9

29

T47

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1182

1

T6

11

T9

37

T47

17

auto[1]

1178

1

T6

9

T9

23

T47

3

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T9

2

T47

2

T37

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T6

1

T9

1

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T9

3

T60

1

T23

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T6

1

T9

1

T101

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T9

2

T47

2

T60

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T6

1

T9

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T6

2

T9

2

T37

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T9

2

T37

1

T101

1

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T9

2

T47

1

T33

3

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T9

2

T37

2

T60

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T6

1

T9

1

T47

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T60

2

T23

1

T33

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T9

1

T60

3

T23

2

auto[1]

from_0to1

auto[0]

auto[1]

83

1

T9

4

T47

1

T37

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T6

1

T9

1

T47

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T23

1

T251

1

T303

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T6

14

T9

28

T47

10

auto[1]

1164

1

T6

6

T9

32

T47

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

572

1

T6

4

T9

15

T47

5

from_0to1

576

1

T6

5

T9

16

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T6

10

T9

30

T47

8

auto[1]

1230

1

T6

10

T9

30

T47

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1207

1

T6

12

T9

32

T47

12

auto[1]

1153

1

T6

8

T9

28

T47

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T9

1

T23

1

T33

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T6

1

T9

2

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T6

1

T9

2

T47

2

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T9

3

T47

1

T60

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T6

3

T9

3

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T6

1

T9

2

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T47

1

T37

1

T60

2

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T9

2

T37

2

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T9

3

T23

1

T33

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T6

1

T9

1

T60

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T6

1

T9

1

T37

2

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T9

2

T47

1

T37

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T9

3

T47

1

T23

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T9

1

T47

1

T23

2

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T6

1

T9

2

T47

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T9

3

T102

2

T251

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1214

1

T6

8

T9

26

T47

8

auto[1]

1146

1

T6

12

T9

34

T47

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

579

1

T6

5

T9

14

T47

6

from_0to1

571

1

T6

4

T9

14

T47

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1204

1

T6

10

T9

31

T47

10

auto[1]

1156

1

T6

10

T9

29

T47

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1169

1

T6

7

T9

30

T47

6

auto[1]

1191

1

T6

13

T9

30

T47

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

85

1

T6

1

T9

2

T47

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T9

2

T37

1

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T9

1

T37

1

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T9

2

T47

2

T33

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T9

4

T47

1

T37

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T47

1

T60

1

T33

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T60

1

T23

2

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

93

1

T6

2

T9

1

T47

1

auto[1]

from_1to0

auto[0]

auto[0]

81

1

T6

2

T60

1

T23

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T9

2

T37

1

T101

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T6

2

T9

3

T47

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T9

2

T47

2

T23

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T9

2

T37

1

T23

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T9

1

T47

3

T37

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T9

2

T37

2

T23

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T6

2

T9

4

T33

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1184

1

T6

7

T9

31

T47

12

auto[1]

1176

1

T6

13

T9

29

T47

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

557

1

T6

6

T9

17

T47

4

from_0to1

563

1

T6

5

T9

17

T47

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T6

10

T9

25

T47

10

auto[1]

1207

1

T6

10

T9

35

T47

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T6

11

T9

25

T47

12

auto[1]

1202

1

T6

9

T9

35

T47

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T9

1

T60

3

T23

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T9

2

T47

1

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T47

1

T37

1

T33

2

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T6

1

T9

1

T33

3

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T6

2

T9

1

T60

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T9

2

T47

2

T23

3

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T6

1

T9

3

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

79

1

T9

4

T60

2

T23

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T9

2

T47

1

T60

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T6

1

T9

2

T37

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T9

3

T47

1

T23

1

auto[1]

from_1to0

auto[1]

auto[1]

85

1

T6

4

T9

6

T37

1

auto[1]

from_0to1

auto[0]

auto[0]

47

1

T6

1

T9

2

T47

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T6

1

T9

2

T37

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T9

3

T47

1

T37

2

auto[1]

from_0to1

auto[1]

auto[1]

85

1

T60

2

T23

1

T303

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1222

1

T6

10

T9

31

T47

6

auto[1]

1138

1

T6

10

T9

29

T47

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

559

1

T6

5

T9

15

T47

6

from_0to1

560

1

T6

5

T9

15

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T6

10

T9

24

T47

9

auto[1]

1160

1

T6

10

T9

36

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T6

11

T9

38

T47

10

auto[1]

1184

1

T6

9

T9

22

T47

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T9

2

T37

2

T23

2

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T6

2

T9

1

T37

1

auto[0]

from_1to0

auto[1]

auto[0]

84

1

T6

1

T9

4

T37

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T9

1

T60

1

T101

2

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T6

2

T9

2

T47

2

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T9

1

T37

2

T33

2

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T9

2

T47

1

T37

1

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T47

1

T60

1

T33

3

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T9

3

T47

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T9

3

T47

1

T37

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T6

1

T47

2

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T6

1

T9

1

T47

2

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T6

2

T37

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T9

3

T37

1

T23

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T9

4

T47

1

T23

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T6

1

T9

3

T37

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1167

1

T6

9

T9

31

T47

9

auto[1]

1193

1

T6

11

T9

29

T47

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T6

2

T9

16

T47

4

from_0to1

550

1

T6

3

T9

16

T47

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T6

13

T9

30

T47

9

auto[1]

1180

1

T6

7

T9

30

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1188

1

T6

10

T9

25

T47

8

auto[1]

1172

1

T6

10

T9

35

T47

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T6

1

T9

3

T47

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T9

2

T60

1

T23

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T60

1

T33

2

T303

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T9

4

T47

1

T37

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T6

2

T9

1

T60

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T6

1

T9

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T9

3

T60

1

T33

3

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T9

4

T47

2

T37

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T47

1

T37

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

80

1

T6

1

T9

2

T33

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T9

2

T37

2

T60

2

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T9

3

T47

1

T23

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T9

2

T37

1

T33

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T9

4

T47

1

T37

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T9

1

T47

1

T102

2

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T47

1

T37

1

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1093

1

T6

8

T9

28

T47

11

auto[1]

1267

1

T6

12

T9

32

T47

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

577

1

T6

4

T9

14

T47

4

from_0to1

574

1

T6

5

T9

14

T47

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1177

1

T6

10

T9

26

T47

9

auto[1]

1183

1

T6

10

T9

34

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1188

1

T6

11

T9

36

T47

12

auto[1]

1172

1

T6

9

T9

24

T47

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T60

3

T226

2

T115

2

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T6

1

T9

2

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T9

2

T37

2

T23

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T9

3

T33

1

T102

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T6

2

T9

4

T37

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T9

1

T47

1

T33

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T6

1

T9

1

T47

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T9

1

T37

1

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

87

1

T9

2

T33

2

T102

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T6

2

T9

2

T47

1

auto[1]

from_1to0

auto[1]

auto[0]

85

1

T6

1

T9

2

T47

2

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T9

1

T47

1

T37

1

auto[1]

from_0to1

auto[0]

auto[0]

82

1

T9

1

T47

1

T37

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T9

2

T37

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

89

1

T6

1

T9

4

T60

2

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T6

1

T47

1

T33

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203

1

T6

9

T9

30

T47

7

auto[1]

1157

1

T6

11

T9

30

T47

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T6

3

T9

11

T47

6

from_0to1

554

1

T6

3

T9

11

T47

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1177

1

T6

11

T9

31

T47

9

auto[1]

1183

1

T6

9

T9

29

T47

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T6

10

T9

28

T47

13

auto[1]

1199

1

T6

10

T9

32

T47

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T9

1

T47

1

T37

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T9

2

T37

2

T33

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T6

1

T9

1

T47

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T9

3

T60

1

T23

1

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T9

1

T47

1

T60

2

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T6

1

T9

2

T47

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T9

2

T33

1

T101

3

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T6

1

T9

3

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T6

1

T9

2

T47

2

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T6

1

T9

2

T47

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T33

2

T101

2

T115

4

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T47

1

T60

2

T23

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T47

1

T60

1

T101

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T9

1

T37

2

T23

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T6

1

T47

2

T37

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T9

2

T47

2

T37

1