Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	161210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124902

1

T5

4

T1

817

T6

44

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146548	1			T5	2		T1	1250		T6	62
values[0x0]	69345	1			T5	6		T1	214		T6	27
values[0x1]	70219	1			T5	12		T1	221		T6	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130994	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155118

1

T5

5

T1

984

T6

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	937	1			T2	1		T4	2		T24	2
valid_sources[0x01]	890	1			T15	3		T4	3		T25	3
valid_sources[0x02]	1495	1			T15	1		T4	7		T24	2
valid_sources[0x03]	1002	1			T14	5		T4	3		T25	9
valid_sources[0x04]	2647	1			T15	8		T4	2		T25	2
valid_sources[0x05]	838	1			T4	4		T8	1		T9	9
valid_sources[0x06]	1053	1			T15	10		T4	2		T8	4
valid_sources[0x07]	1508	1			T4	2		T25	3		T8	1
valid_sources[0x08]	894	1			T4	3		T24	1		T25	2
valid_sources[0x09]	944	1			T3	3		T4	4		T9	33
valid_sources[0x0a]	1004	1			T15	4		T4	6		T25	8
valid_sources[0x0b]	1203	1			T14	3		T4	3		T25	3
valid_sources[0x0c]	890	1			T5	1		T15	2		T4	2
valid_sources[0x0d]	1237	1			T4	2		T25	1		T8	1
valid_sources[0x0e]	1184	1			T5	1		T4	1		T25	3
valid_sources[0x0f]	823	1			T15	5		T4	5		T25	1
valid_sources[0x10]	818	1			T15	1		T4	1		T24	1
valid_sources[0x11]	1038	1			T4	4		T25	16		T9	35
valid_sources[0x12]	1003	1			T5	1		T15	1		T4	7
valid_sources[0x13]	1100	1			T15	5		T4	3		T24	1
valid_sources[0x14]	903	1			T4	1		T25	2		T8	2
valid_sources[0x15]	1333	1			T4	5		T25	17		T46	1
valid_sources[0x16]	986	1			T15	3		T4	3		T25	4
valid_sources[0x17]	791	1			T15	1		T4	3		T11	23
valid_sources[0x18]	930	1			T4	4		T25	2		T8	1
valid_sources[0x19]	1101	1			T14	2		T4	2		T25	6
valid_sources[0x1a]	1060	1			T15	3		T4	5		T25	4
valid_sources[0x1b]	759	1			T15	9		T4	5		T24	1
valid_sources[0x1c]	859	1			T4	5		T25	4		T8	3
valid_sources[0x1d]	1174	1			T15	2		T4	3		T22	1
valid_sources[0x1e]	918	1			T2	1		T4	4		T25	2
valid_sources[0x1f]	919	1			T4	4		T25	3		T22	1
valid_sources[0x20]	1039	1			T4	3		T25	3		T8	3
valid_sources[0x21]	1251	1			T15	7		T4	6		T25	11
valid_sources[0x22]	876	1			T15	5		T4	4		T38	2
valid_sources[0x23]	1200	1			T15	5		T4	3		T25	2
valid_sources[0x24]	759	1			T15	1		T4	1		T25	3
valid_sources[0x25]	1230	1			T4	1		T24	1		T25	6
valid_sources[0x26]	1211	1			T4	9		T24	1		T25	11
valid_sources[0x27]	1016	1			T15	1		T3	8		T4	1
valid_sources[0x28]	1144	1			T15	3		T4	5		T25	1
valid_sources[0x29]	1057	1			T15	8		T4	11		T25	1
valid_sources[0x2a]	1035	1			T4	4		T25	10		T8	3
valid_sources[0x2b]	981	1			T4	6		T8	2		T9	12
valid_sources[0x2c]	1599	1			T15	2		T3	2		T4	2
valid_sources[0x2d]	1033	1			T4	4		T25	5		T8	1
valid_sources[0x2e]	1058	1			T15	6		T4	3		T25	2
valid_sources[0x2f]	928	1			T4	2		T24	1		T25	7
valid_sources[0x30]	865	1			T4	3		T25	2		T8	1
valid_sources[0x31]	1159	1			T15	3		T4	2		T25	2
valid_sources[0x32]	803	1			T5	1		T4	3		T8	2
valid_sources[0x33]	890	1			T15	8		T4	3		T8	1
valid_sources[0x34]	945	1			T15	2		T25	2		T8	1
valid_sources[0x35]	1108	1			T15	11		T25	1		T8	3
valid_sources[0x36]	1688	1			T4	5		T25	2		T8	2
valid_sources[0x37]	1249	1			T14	2		T4	2		T25	2
valid_sources[0x38]	915	1			T15	3		T4	5		T24	1
valid_sources[0x39]	791	1			T4	2		T24	1		T8	3
valid_sources[0x3a]	909	1			T4	9		T25	5		T8	1
valid_sources[0x3b]	873	1			T4	2		T8	1		T11	24
valid_sources[0x3c]	1157	1			T15	5		T4	4		T25	6
valid_sources[0x3d]	1051	1			T14	4		T15	10		T4	3
valid_sources[0x3e]	1285	1			T15	4		T4	2		T24	1
valid_sources[0x3f]	889	1			T15	5		T4	3		T25	5
valid_sources[0x40]	931	1			T4	3		T25	1		T8	4
valid_sources[0x41]	1003	1			T4	4		T24	1		T25	4
valid_sources[0x42]	1136	1			T15	6		T4	4		T25	3
valid_sources[0x43]	1267	1			T4	1		T25	3		T8	3
valid_sources[0x44]	884	1			T15	3		T3	15		T4	1
valid_sources[0x45]	1132	1			T25	1		T8	1		T47	2
valid_sources[0x46]	1811	1			T15	5		T4	8		T25	7
valid_sources[0x47]	807	1			T4	4		T25	1		T8	2
valid_sources[0x48]	909	1			T15	4		T118	6		T38	2
valid_sources[0x49]	1096	1			T15	5		T4	1		T25	1
valid_sources[0x4a]	1044	1			T4	3		T8	3		T36	1
valid_sources[0x4b]	1028	1			T4	4		T25	1		T8	1
valid_sources[0x4c]	1376	1			T4	2		T25	10		T8	1
valid_sources[0x4d]	1874	1			T15	7		T4	2		T25	3
valid_sources[0x4e]	843	1			T15	3		T4	5		T25	4
valid_sources[0x4f]	976	1			T4	4		T25	6		T389	1
valid_sources[0x50]	922	1			T15	1		T2	2		T4	1
valid_sources[0x51]	2334	1			T15	1		T4	4		T25	1
valid_sources[0x52]	1273	1			T6	123		T15	1		T4	7
valid_sources[0x53]	1781	1			T4	4		T25	2		T8	1
valid_sources[0x54]	1099	1			T15	1		T4	1		T25	2
valid_sources[0x55]	1138	1			T15	2		T4	4		T25	3
valid_sources[0x56]	782	1			T15	3		T4	5		T25	8
valid_sources[0x57]	1806	1			T5	1		T4	1		T8	3
valid_sources[0x58]	1187	1			T15	3		T4	4		T25	2
valid_sources[0x59]	991	1			T15	2		T4	2		T24	1
valid_sources[0x5a]	961	1			T5	1		T4	2		T25	1
valid_sources[0x5b]	868	1			T14	2		T4	1		T25	4
valid_sources[0x5c]	1057	1			T15	6		T4	2		T24	1
valid_sources[0x5d]	993	1			T4	2		T24	1		T25	7
valid_sources[0x5e]	1303	1			T13	4		T4	2		T24	1
valid_sources[0x5f]	805	1			T4	3		T25	12		T8	1
valid_sources[0x60]	1075	1			T15	3		T4	4		T38	1
valid_sources[0x61]	1151	1			T15	4		T4	5		T25	2
valid_sources[0x62]	788	1			T15	5		T4	3		T9	19
valid_sources[0x63]	1141	1			T4	6		T25	1		T8	1
valid_sources[0x64]	1307	1			T15	3		T4	3		T24	2
valid_sources[0x65]	1251	1			T15	1		T2	1		T4	2
valid_sources[0x66]	866	1			T4	4		T8	3		T10	13
valid_sources[0x67]	951	1			T15	3		T4	3		T24	1
valid_sources[0x68]	921	1			T15	6		T4	2		T25	10
valid_sources[0x69]	972	1			T4	3		T25	15		T8	2
valid_sources[0x6a]	1058	1			T15	2		T3	6		T4	5
valid_sources[0x6b]	1025	1			T5	1		T4	5		T24	1
valid_sources[0x6c]	710	1			T15	5		T4	4		T8	4
valid_sources[0x6d]	901	1			T5	1		T4	5		T25	6
valid_sources[0x6e]	809	1			T2	1		T4	1		T25	6
valid_sources[0x6f]	2184	1			T4	4		T24	1		T25	1
valid_sources[0x70]	2387	1			T4	2		T25	14		T8	3
valid_sources[0x71]	1933	1			T5	1		T4	1		T25	4
valid_sources[0x72]	1384	1			T4	4		T25	3		T8	2
valid_sources[0x73]	1236	1			T15	1		T2	1		T4	6
valid_sources[0x74]	1720	1			T2	1		T24	1		T25	3
valid_sources[0x75]	956	1			T4	5		T24	1		T25	4
valid_sources[0x76]	938	1			T15	1		T4	5		T25	6
valid_sources[0x77]	900	1			T15	6		T4	3		T25	1
valid_sources[0x78]	855	1			T15	1		T4	1		T25	5
valid_sources[0x79]	1177	1			T4	2		T25	1		T8	2
valid_sources[0x7a]	879	1			T4	2		T25	6		T8	3
valid_sources[0x7b]	1072	1			T4	9		T25	5		T11	1
valid_sources[0x7c]	1832	1			T3	17		T4	2		T8	2
valid_sources[0x7d]	1453	1			T4	4		T25	3		T47	5
valid_sources[0x7e]	888	1			T15	2		T2	2		T4	3
valid_sources[0x7f]	817	1			T17	10		T4	4		T25	11
valid_sources[0x80]	1000	1			T2	1		T4	2		T25	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

66756

1

T5

2

T1

616

T6

27

values[0x0]

all_enables

biggest_size

33975

1

T5

1

T1

102

T6

11

values[0x1]

all_enables

biggest_size

24171

1

T5

1

T1

99

T6

6