Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1220955365	10066	0	0
auto_block_debounce_ctl_rd_A	1220955365	1574	0	0
auto_block_out_ctl_rd_A	1220955365	2249	0	0
com_det_ctl_0_rd_A	1220955365	3887	0	0
com_det_ctl_1_rd_A	1220955365	3830	0	0
com_det_ctl_2_rd_A	1220955365	4168	0	0
com_det_ctl_3_rd_A	1220955365	3953	0	0
com_out_ctl_0_rd_A	1220955365	4417	0	0
com_out_ctl_1_rd_A	1220955365	4426	0	0
com_out_ctl_2_rd_A	1220955365	4588	0	0
com_out_ctl_3_rd_A	1220955365	4523	0	0
com_pre_det_ctl_0_rd_A	1220955365	1200	0	0
com_pre_det_ctl_1_rd_A	1220955365	1287	0	0
com_pre_det_ctl_2_rd_A	1220955365	1290	0	0
com_pre_det_ctl_3_rd_A	1220955365	1321	0	0
com_pre_sel_ctl_0_rd_A	1220955365	4597	0	0
com_pre_sel_ctl_1_rd_A	1220955365	4462	0	0
com_pre_sel_ctl_2_rd_A	1220955365	4386	0	0
com_pre_sel_ctl_3_rd_A	1220955365	4607	0	0
com_sel_ctl_0_rd_A	1220955365	4620	0	0
com_sel_ctl_1_rd_A	1220955365	4530	0	0
com_sel_ctl_2_rd_A	1220955365	4603	0	0
com_sel_ctl_3_rd_A	1220955365	4747	0	0
ec_rst_ctl_rd_A	1220955365	2533	0	0
intr_enable_rd_A	1220955365	2192	0	0
key_intr_ctl_rd_A	1220955365	3576	0	0
key_intr_debounce_ctl_rd_A	1220955365	1375	0	0
key_invert_ctl_rd_A	1220955365	4305	0	0
pin_allowed_ctl_rd_A	1220955365	6216	0	0
pin_out_ctl_rd_A	1220955365	4462	0	0
pin_out_value_rd_A	1220955365	4397	0	0
regwen_rd_A	1220955365	1646	0	0
ulp_ac_debounce_ctl_rd_A	1220955365	1568	0	0
ulp_ctl_rd_A	1220955365	1549	0	0
ulp_lid_debounce_ctl_rd_A	1220955365	1420	0	0
ulp_pwrb_debounce_ctl_rd_A	1220955365	1501	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	10066	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T8	0	4	0	0
T9	0	24	0	0
T15	209797	8	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T21	0	5	0	0
T23	0	25	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	14	0	0
T45	108419	0	0	0
T57	0	1	0	0
T115	0	19	0	0
T294	0	10	0	0
T295	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1574	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	33	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	36	0	0
T44	0	12	0	0
T45	108419	0	0	0
T57	0	7	0	0
T72	0	26	0	0
T114	0	7	0	0
T130	0	45	0	0
T139	0	10	0	0
T152	0	19	0	0
T296	0	12	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	2249	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	23	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	30	0	0
T44	0	8	0	0
T45	108419	0	0	0
T72	0	14	0	0
T114	0	8	0	0
T130	0	28	0	0
T139	0	3	0	0
T152	0	18	0	0
T296	0	9	0	0
T297	0	13	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	3887	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	38	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	5	0	0
T33	0	294	0	0
T38	0	15	0	0
T39	0	80	0	0
T45	108419	0	0	0
T57	0	4	0	0
T68	0	67	0	0
T152	0	17	0	0
T236	0	32	0	0
T240	0	28	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	3830	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	34	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	11	0	0
T33	0	264	0	0
T38	0	7	0	0
T39	0	77	0	0
T45	108419	0	0	0
T68	0	73	0	0
T72	0	2	0	0
T152	0	22	0	0
T236	0	27	0	0
T240	0	45	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4168	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	28	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	20	0	0
T33	0	298	0	0
T38	0	1	0	0
T39	0	55	0	0
T45	108419	0	0	0
T68	0	86	0	0
T87	0	50	0	0
T152	0	28	0	0
T236	0	44	0	0
T240	0	37	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	3953	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	39	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	22	0	0
T33	0	310	0	0
T38	0	12	0	0
T39	0	68	0	0
T45	108419	0	0	0
T57	0	2	0	0
T68	0	68	0	0
T152	0	12	0	0
T236	0	48	0	0
T240	0	9	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4417	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	46	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	40	0	0
T33	0	237	0	0
T38	0	6	0	0
T39	0	62	0	0
T45	108419	0	0	0
T57	0	4	0	0
T68	0	69	0	0
T152	0	18	0	0
T236	0	52	0	0
T240	0	53	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4426	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	24	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	9	0	0
T33	0	307	0	0
T38	0	9	0	0
T39	0	80	0	0
T45	108419	0	0	0
T57	0	6	0	0
T68	0	47	0	0
T152	0	20	0	0
T236	0	44	0	0
T240	0	63	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4588	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	35	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	18	0	0
T33	0	289	0	0
T38	0	24	0	0
T39	0	90	0	0
T45	108419	0	0	0
T68	0	84	0	0
T72	0	4	0	0
T152	0	18	0	0
T236	0	48	0	0
T240	0	48	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4523	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	48	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	27	0	0
T33	0	259	0	0
T39	0	72	0	0
T45	108419	0	0	0
T57	0	5	0	0
T68	0	82	0	0
T72	0	4	0	0
T152	0	10	0	0
T236	0	43	0	0
T240	0	46	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1200	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	63	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	20	0	0
T45	108419	0	0	0
T57	0	1	0	0
T72	0	11	0	0
T130	0	29	0	0
T152	0	12	0	0
T160	0	22	0	0
T163	0	20	0	0
T298	0	20	0	0
T299	0	29	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1287	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	46	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	33	0	0
T45	108419	0	0	0
T57	0	7	0	0
T72	0	8	0	0
T130	0	30	0	0
T152	0	20	0	0
T160	0	31	0	0
T163	0	31	0	0
T298	0	21	0	0
T299	0	26	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1290	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	33	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	17	0	0
T45	108419	0	0	0
T72	0	2	0	0
T80	0	12	0	0
T130	0	25	0	0
T152	0	15	0	0
T160	0	17	0	0
T163	0	14	0	0
T298	0	19	0	0
T299	0	29	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1321	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	32	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	30	0	0
T45	108419	0	0	0
T57	0	7	0	0
T72	0	9	0	0
T130	0	36	0	0
T152	0	12	0	0
T160	0	29	0	0
T163	0	17	0	0
T298	0	10	0	0
T299	0	25	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4597	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	30	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	32	0	0
T33	0	263	0	0
T38	0	6	0	0
T39	0	82	0	0
T45	108419	0	0	0
T57	0	3	0	0
T68	0	47	0	0
T152	0	8	0	0
T236	0	36	0	0
T240	0	32	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4462	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	49	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	17	0	0
T33	0	296	0	0
T39	0	73	0	0
T45	108419	0	0	0
T68	0	60	0	0
T72	0	6	0	0
T87	0	79	0	0
T152	0	17	0	0
T236	0	52	0	0
T240	0	27	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4386	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	44	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	24	0	0
T33	0	240	0	0
T38	0	14	0	0
T39	0	83	0	0
T45	108419	0	0	0
T57	0	1	0	0
T68	0	67	0	0
T152	0	15	0	0
T236	0	42	0	0
T240	0	20	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4607	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	24	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	29	0	0
T33	0	271	0	0
T38	0	8	0	0
T39	0	75	0	0
T45	108419	0	0	0
T57	0	6	0	0
T68	0	72	0	0
T152	0	15	0	0
T236	0	41	0	0
T240	0	36	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4620	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	41	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	35	0	0
T33	0	278	0	0
T38	0	2	0	0
T39	0	76	0	0
T45	108419	0	0	0
T57	0	3	0	0
T68	0	53	0	0
T152	0	6	0	0
T236	0	68	0	0
T240	0	37	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4530	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	53	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	17	0	0
T33	0	300	0	0
T38	0	5	0	0
T39	0	54	0	0
T45	108419	0	0	0
T68	0	55	0	0
T72	0	1	0	0
T152	0	20	0	0
T236	0	56	0	0
T240	0	31	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4603	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	49	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	15	0	0
T33	0	278	0	0
T38	0	10	0	0
T39	0	76	0	0
T45	108419	0	0	0
T57	0	2	0	0
T68	0	90	0	0
T152	0	27	0	0
T236	0	52	0	0
T240	0	50	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4747	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	21	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	25	0	0
T33	0	269	0	0
T38	0	13	0	0
T39	0	63	0	0
T45	108419	0	0	0
T57	0	5	0	0
T68	0	87	0	0
T152	0	20	0	0
T236	0	52	0	0
T240	0	40	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	2533	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	59	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	169	0	0
T38	0	3	0	0
T39	0	15	0	0
T45	108419	0	0	0
T57	0	5	0	0
T68	0	44	0	0
T118	0	3	0	0
T119	0	2	0	0
T236	0	12	0	0
T240	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	2192	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	40	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T28	0	3	0	0
T33	0	76	0	0
T45	108419	0	0	0
T57	0	7	0	0
T72	0	45	0	0
T114	0	16	0	0
T130	0	81	0	0
T152	0	25	0	0
T163	0	24	0	0
T298	0	38	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	3576	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	2	0	0
T15	209797	46	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T28	0	2	0	0
T31	0	2	0	0
T33	0	29	0	0
T45	108419	0	0	0
T57	0	1	0	0
T72	0	16	0	0
T130	0	29	0	0
T150	0	3	0	0
T152	0	25	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1375	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	43	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	36	0	0
T45	108419	0	0	0
T57	0	10	0	0
T72	0	15	0	0
T130	0	35	0	0
T152	0	14	0	0
T160	0	20	0	0
T163	0	24	0	0
T298	0	17	0	0
T299	0	23	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4305	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	15	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T28	0	71	0	0
T33	0	19	0	0
T45	108419	0	0	0
T57	0	144	0	0
T72	0	45	0	0
T152	0	35	0	0
T215	0	55	0	0
T300	0	65	0	0
T301	0	59	0	0
T302	0	49	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	6216	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	42	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	165	0	0
T45	108419	0	0	0
T57	0	6	0	0
T60	0	27	0	0
T72	0	77	0	0
T102	0	88	0	0
T152	0	14	0	0
T187	0	56	0	0
T303	0	95	0	0
T304	0	64	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4462	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	48	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	167	0	0
T45	108419	0	0	0
T57	0	3	0	0
T60	0	32	0	0
T72	0	72	0	0
T102	0	55	0	0
T152	0	21	0	0
T187	0	68	0	0
T303	0	71	0	0
T304	0	75	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	4397	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	40	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	198	0	0
T45	108419	0	0	0
T57	0	2	0	0
T60	0	44	0	0
T72	0	80	0	0
T102	0	62	0	0
T152	0	16	0	0
T187	0	65	0	0
T303	0	70	0	0
T304	0	68	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1646	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	41	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	32	0	0
T45	108419	0	0	0
T57	0	5	0	0
T80	0	11	0	0
T130	0	30	0	0
T152	0	14	0	0
T160	0	14	0	0
T163	0	23	0	0
T298	0	17	0	0
T299	0	11	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1568	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	43	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	43	0	0
T45	108419	0	0	0
T65	0	8	0	0
T72	0	18	0	0
T76	0	8	0	0
T77	0	9	0	0
T129	0	9	0	0
T130	0	41	0	0
T152	0	11	0	0
T305	0	8	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1549	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	41	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	41	0	0
T45	108419	0	0	0
T57	0	2	0	0
T65	0	3	0	0
T72	0	5	0	0
T76	0	1	0	0
T77	0	14	0	0
T130	0	47	0	0
T152	0	20	0	0
T306	0	5	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1420	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	41	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	60	0	0
T45	108419	0	0	0
T57	0	5	0	0
T65	0	2	0	0
T72	0	6	0	0
T76	0	1	0	0
T77	0	22	0	0
T129	0	7	0	0
T130	0	33	0	0
T152	0	16	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1220955365	1501	0	0
T2	125625	0	0	0
T3	178235	0	0	0
T4	152051	0	0	0
T7	500009	0	0	0
T15	209797	57	0	0
T16	272564	0	0	0
T17	49906	0	0	0
T24	130601	0	0	0
T25	389888	0	0	0
T33	0	68	0	0
T45	108419	0	0	0
T65	0	10	0	0
T72	0	8	0	0
T76	0	10	0	0
T77	0	11	0	0
T129	0	6	0	0
T130	0	15	0	0
T152	0	14	0	0
T305	0	1	0	0