Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T2 |
1 | 0 | Covered | T1,T15,T2 |
1 | 1 | Covered | T2,T50,T65 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T2 |
1 | 0 | Covered | T2,T50,T65 |
1 | 1 | Covered | T1,T15,T2 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
239774 |
0 |
0 |
T1 |
4356075 |
402 |
0 |
0 |
T2 |
1912845 |
0 |
0 |
0 |
T3 |
4179514 |
20 |
0 |
0 |
T4 |
3788606 |
51 |
0 |
0 |
T6 |
3778335 |
0 |
0 |
0 |
T7 |
4508241 |
0 |
0 |
0 |
T8 |
1699663 |
16 |
0 |
0 |
T9 |
140303 |
90 |
0 |
0 |
T10 |
0 |
256 |
0 |
0 |
T11 |
0 |
68 |
0 |
0 |
T12 |
0 |
17 |
0 |
0 |
T13 |
2272950 |
0 |
0 |
0 |
T14 |
1647645 |
0 |
0 |
0 |
T15 |
3210525 |
10 |
0 |
0 |
T16 |
6791371 |
119 |
0 |
0 |
T17 |
1157383 |
0 |
0 |
0 |
T24 |
1048984 |
0 |
0 |
0 |
T25 |
3571376 |
17 |
0 |
0 |
T35 |
175562 |
16 |
0 |
0 |
T36 |
348110 |
18 |
0 |
0 |
T37 |
0 |
112 |
0 |
0 |
T38 |
0 |
13 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
16 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T44 |
0 |
16 |
0 |
0 |
T45 |
870888 |
0 |
0 |
0 |
T46 |
2343183 |
0 |
0 |
0 |
T47 |
120669 |
0 |
0 |
0 |
T48 |
201979 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
241813 |
0 |
0 |
T1 |
4356075 |
402 |
0 |
0 |
T2 |
1912845 |
0 |
0 |
0 |
T3 |
4179514 |
20 |
0 |
0 |
T4 |
3788606 |
51 |
0 |
0 |
T6 |
3778335 |
0 |
0 |
0 |
T7 |
4009252 |
0 |
0 |
0 |
T8 |
1518182 |
16 |
0 |
0 |
T9 |
23434 |
90 |
0 |
0 |
T10 |
0 |
256 |
0 |
0 |
T11 |
0 |
68 |
0 |
0 |
T12 |
0 |
17 |
0 |
0 |
T13 |
2272950 |
0 |
0 |
0 |
T14 |
1647645 |
0 |
0 |
0 |
T15 |
3210525 |
10 |
0 |
0 |
T16 |
6791371 |
119 |
0 |
0 |
T17 |
1157383 |
0 |
0 |
0 |
T24 |
1048984 |
0 |
0 |
0 |
T25 |
3189286 |
17 |
0 |
0 |
T35 |
701 |
16 |
0 |
0 |
T36 |
732 |
18 |
0 |
0 |
T37 |
0 |
112 |
0 |
0 |
T38 |
0 |
13 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T40 |
0 |
16 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T44 |
0 |
16 |
0 |
0 |
T45 |
870888 |
0 |
0 |
0 |
T46 |
2084025 |
0 |
0 |
0 |
T47 |
503 |
0 |
0 |
0 |
T48 |
403 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T18,T19,T323 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T18,T19,T323 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2171 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
3 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2232 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
3 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T18,T19,T323 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T18,T19,T323 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2225 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
3 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2225 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
3 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T3,T9 |
1 | 1 | Covered | T2,T50,T65 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T50,T65 |
1 | 1 | Covered | T2,T3,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1093 |
0 |
0 |
T2 |
1898 |
2 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1150 |
0 |
0 |
T2 |
125625 |
2 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T3,T9 |
1 | 1 | Covered | T2,T50,T65 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T50,T65 |
1 | 1 | Covered | T2,T3,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1147 |
0 |
0 |
T2 |
125625 |
2 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1147 |
0 |
0 |
T2 |
1898 |
2 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T3,T9 |
1 | 1 | Covered | T2,T50,T65 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T50,T65 |
1 | 1 | Covered | T2,T3,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1066 |
0 |
0 |
T2 |
1898 |
2 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1126 |
0 |
0 |
T2 |
125625 |
2 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T3,T9 |
1 | 1 | Covered | T2,T50,T65 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T50,T65 |
1 | 1 | Covered | T2,T3,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1122 |
0 |
0 |
T2 |
125625 |
2 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1122 |
0 |
0 |
T2 |
1898 |
2 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T3,T9 |
1 | 1 | Covered | T2,T50,T65 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T50,T65 |
1 | 1 | Covered | T2,T3,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1104 |
0 |
0 |
T2 |
1898 |
2 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1163 |
0 |
0 |
T2 |
125625 |
2 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T3,T9 |
1 | 1 | Covered | T2,T50,T65 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T3,T9 |
1 | 0 | Covered | T2,T50,T65 |
1 | 1 | Covered | T2,T3,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1158 |
0 |
0 |
T2 |
125625 |
2 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1158 |
0 |
0 |
T2 |
1898 |
2 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T50 |
0 |
2 |
0 |
0 |
T51 |
0 |
1 |
0 |
0 |
T52 |
0 |
1 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T9,T21 |
1 | 0 | Covered | T2,T9,T21 |
1 | 1 | Covered | T2,T9,T21 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T9,T21 |
1 | 0 | Covered | T2,T9,T21 |
1 | 1 | Covered | T2,T9,T21 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1099 |
0 |
0 |
T2 |
1898 |
4 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T50 |
0 |
4 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |
T66 |
0 |
6 |
0 |
0 |
T67 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1157 |
0 |
0 |
T2 |
125625 |
4 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T50 |
0 |
4 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |
T66 |
0 |
6 |
0 |
0 |
T67 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T9,T21 |
1 | 0 | Covered | T2,T9,T21 |
1 | 1 | Covered | T2,T9,T21 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T2,T9,T21 |
1 | 0 | Covered | T2,T9,T21 |
1 | 1 | Covered | T2,T9,T21 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1154 |
0 |
0 |
T2 |
125625 |
4 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T50 |
0 |
4 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |
T66 |
0 |
6 |
0 |
0 |
T67 |
0 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1154 |
0 |
0 |
T2 |
1898 |
4 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T50 |
0 |
4 |
0 |
0 |
T51 |
0 |
2 |
0 |
0 |
T53 |
0 |
2 |
0 |
0 |
T65 |
0 |
4 |
0 |
0 |
T66 |
0 |
6 |
0 |
0 |
T67 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1126 |
0 |
0 |
T1 |
64534 |
21 |
0 |
0 |
T2 |
1898 |
2 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
4 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T37 |
0 |
9 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
7 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1190 |
0 |
0 |
T1 |
225871 |
21 |
0 |
0 |
T2 |
125625 |
2 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
4 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T37 |
0 |
9 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
7 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T22,T21,T23 |
1 | 0 | Covered | T22,T21,T23 |
1 | 1 | Covered | T22,T21,T23 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T22,T21,T23 |
1 | 0 | Covered | T22,T21,T23 |
1 | 1 | Covered | T22,T21,T23 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2705 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T22 |
495 |
20 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T28 |
0 |
20 |
0 |
0 |
T32 |
646 |
0 |
0 |
0 |
T37 |
23501 |
0 |
0 |
0 |
T38 |
6087 |
0 |
0 |
0 |
T39 |
11193 |
0 |
0 |
0 |
T40 |
640 |
0 |
0 |
0 |
T54 |
0 |
20 |
0 |
0 |
T55 |
0 |
20 |
0 |
0 |
T56 |
0 |
20 |
0 |
0 |
T57 |
0 |
40 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T60 |
502 |
0 |
0 |
0 |
T61 |
522 |
0 |
0 |
0 |
T62 |
427 |
0 |
0 |
0 |
T63 |
848 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2762 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T22 |
121433 |
20 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T28 |
0 |
20 |
0 |
0 |
T32 |
143344 |
0 |
0 |
0 |
T37 |
258516 |
0 |
0 |
0 |
T38 |
292203 |
0 |
0 |
0 |
T39 |
223867 |
0 |
0 |
0 |
T40 |
320388 |
0 |
0 |
0 |
T54 |
0 |
20 |
0 |
0 |
T55 |
0 |
20 |
0 |
0 |
T56 |
0 |
20 |
0 |
0 |
T57 |
0 |
40 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T60 |
251242 |
0 |
0 |
0 |
T61 |
248122 |
0 |
0 |
0 |
T62 |
46986 |
0 |
0 |
0 |
T63 |
208053 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T22,T21,T23 |
1 | 0 | Covered | T22,T21,T23 |
1 | 1 | Covered | T22,T21,T23 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T22,T21,T23 |
1 | 0 | Covered | T22,T21,T23 |
1 | 1 | Covered | T22,T21,T23 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2759 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T22 |
121433 |
20 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T28 |
0 |
20 |
0 |
0 |
T32 |
143344 |
0 |
0 |
0 |
T37 |
258516 |
0 |
0 |
0 |
T38 |
292203 |
0 |
0 |
0 |
T39 |
223867 |
0 |
0 |
0 |
T40 |
320388 |
0 |
0 |
0 |
T54 |
0 |
20 |
0 |
0 |
T55 |
0 |
20 |
0 |
0 |
T56 |
0 |
20 |
0 |
0 |
T57 |
0 |
40 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T60 |
251242 |
0 |
0 |
0 |
T61 |
248122 |
0 |
0 |
0 |
T62 |
46986 |
0 |
0 |
0 |
T63 |
208053 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2759 |
0 |
0 |
T21 |
0 |
20 |
0 |
0 |
T22 |
495 |
20 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T28 |
0 |
20 |
0 |
0 |
T32 |
646 |
0 |
0 |
0 |
T37 |
23501 |
0 |
0 |
0 |
T38 |
6087 |
0 |
0 |
0 |
T39 |
11193 |
0 |
0 |
0 |
T40 |
640 |
0 |
0 |
0 |
T54 |
0 |
20 |
0 |
0 |
T55 |
0 |
20 |
0 |
0 |
T56 |
0 |
20 |
0 |
0 |
T57 |
0 |
40 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T60 |
502 |
0 |
0 |
0 |
T61 |
522 |
0 |
0 |
0 |
T62 |
427 |
0 |
0 |
0 |
T63 |
848 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T6,T3,T24 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T6,T3,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T6,T3,T24 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T6,T3,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
6760 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
20 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T6 |
502 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T47 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
6821 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
20 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T6 |
251387 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T47 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T6,T3,T24 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T6,T3,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T6,T3,T24 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T6,T3,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
6817 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
20 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T6 |
251387 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T47 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
6817 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
20 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T6 |
502 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T22 |
0 |
1 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T47 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T6,T15 |
1 | 0 | Covered | T1,T6,T15 |
1 | 1 | Covered | T6,T3,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T6,T15 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T1,T6,T15 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7980 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
21 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
4 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
8043 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
21 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
4 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T6,T15 |
1 | 0 | Covered | T1,T6,T15 |
1 | 1 | Covered | T6,T3,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T6,T15 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T1,T6,T15 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
8037 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
21 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
4 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
8037 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
21 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
4 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T6,T3,T24 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T6,T3,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T6,T3,T24 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T6,T3,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
6666 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
20 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T6 |
502 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T47 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
6727 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
20 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T6 |
251387 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T47 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T6,T3,T24 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T6,T3,T24 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T6,T3,T24 |
1 | 0 | Covered | T6,T3,T24 |
1 | 1 | Covered | T6,T3,T24 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
6723 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
20 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T6 |
251387 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T47 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
6723 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
20 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T6 |
502 |
20 |
0 |
0 |
T8 |
0 |
20 |
0 |
0 |
T9 |
0 |
60 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T23 |
0 |
40 |
0 |
0 |
T24 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T47 |
0 |
20 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T61 |
0 |
20 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1086 |
0 |
0 |
T7 |
1020 |
1 |
0 |
0 |
T8 |
3902 |
1 |
0 |
0 |
T9 |
23434 |
2 |
0 |
0 |
T10 |
36864 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
701 |
0 |
0 |
0 |
T36 |
732 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T47 |
503 |
0 |
0 |
0 |
T48 |
403 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1146 |
0 |
0 |
T7 |
500009 |
1 |
0 |
0 |
T8 |
185383 |
1 |
0 |
0 |
T9 |
140303 |
2 |
0 |
0 |
T10 |
460798 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
175562 |
0 |
0 |
0 |
T36 |
348110 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T47 |
120669 |
0 |
0 |
0 |
T48 |
201979 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T7,T8,T9 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T7,T8,T9 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T7,T8,T9 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1142 |
0 |
0 |
T7 |
500009 |
1 |
0 |
0 |
T8 |
185383 |
1 |
0 |
0 |
T9 |
140303 |
2 |
0 |
0 |
T10 |
460798 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T25 |
389888 |
0 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
175562 |
0 |
0 |
0 |
T36 |
348110 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T47 |
120669 |
0 |
0 |
0 |
T48 |
201979 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1142 |
0 |
0 |
T7 |
1020 |
1 |
0 |
0 |
T8 |
3902 |
1 |
0 |
0 |
T9 |
23434 |
2 |
0 |
0 |
T10 |
36864 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T23 |
0 |
2 |
0 |
0 |
T25 |
7798 |
0 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
701 |
0 |
0 |
0 |
T36 |
732 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T47 |
503 |
0 |
0 |
0 |
T48 |
403 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2131 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T7 |
0 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
6 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2191 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T7 |
0 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
6 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2185 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T7 |
0 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
6 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2185 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T7 |
0 |
1 |
0 |
0 |
T8 |
0 |
1 |
0 |
0 |
T9 |
0 |
6 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T3 |
1 | 0 | Covered | T1,T15,T3 |
1 | 1 | Covered | T1,T15,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T3 |
1 | 0 | Covered | T1,T15,T3 |
1 | 1 | Covered | T1,T15,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1376 |
0 |
0 |
T1 |
64534 |
6 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
5 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T9 |
0 |
16 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
2 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T35 |
0 |
5 |
0 |
0 |
T36 |
0 |
6 |
0 |
0 |
T37 |
0 |
5 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1434 |
0 |
0 |
T1 |
225871 |
6 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
5 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T9 |
0 |
16 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
2 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T35 |
0 |
5 |
0 |
0 |
T36 |
0 |
6 |
0 |
0 |
T37 |
0 |
5 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T3 |
1 | 0 | Covered | T1,T15,T3 |
1 | 1 | Covered | T1,T15,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T3 |
1 | 0 | Covered | T1,T15,T3 |
1 | 1 | Covered | T1,T15,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1431 |
0 |
0 |
T1 |
225871 |
6 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
5 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T9 |
0 |
16 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
2 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T35 |
0 |
5 |
0 |
0 |
T36 |
0 |
6 |
0 |
0 |
T37 |
0 |
5 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1431 |
0 |
0 |
T1 |
64534 |
6 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
5 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T9 |
0 |
16 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
2 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T35 |
0 |
5 |
0 |
0 |
T36 |
0 |
6 |
0 |
0 |
T37 |
0 |
5 |
0 |
0 |
T40 |
0 |
5 |
0 |
0 |
T44 |
0 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T3 |
1 | 0 | Covered | T1,T15,T3 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T15,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1229 |
0 |
0 |
T1 |
64534 |
3 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
3 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
9 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
3 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1287 |
0 |
0 |
T1 |
225871 |
3 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
3 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
9 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
3 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T3 |
1 | 0 | Covered | T1,T15,T3 |
1 | 1 | Covered | T1,T3,T8 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T3 |
1 | 0 | Covered | T1,T3,T8 |
1 | 1 | Covered | T1,T15,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1284 |
0 |
0 |
T1 |
225871 |
3 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
3 |
0 |
0 |
T4 |
152051 |
0 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
9 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
0 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
3 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1284 |
0 |
0 |
T1 |
64534 |
3 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
3 |
0 |
0 |
T4 |
12671 |
0 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T8 |
0 |
3 |
0 |
0 |
T9 |
0 |
9 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
0 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T35 |
0 |
3 |
0 |
0 |
T36 |
0 |
3 |
0 |
0 |
T37 |
0 |
3 |
0 |
0 |
T40 |
0 |
3 |
0 |
0 |
T44 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7295 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
65 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
73 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T16 |
22713 |
64 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
77 |
0 |
0 |
T38 |
0 |
54 |
0 |
0 |
T39 |
0 |
70 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
75 |
0 |
0 |
T43 |
0 |
77 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7354 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
65 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
73 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T16 |
272564 |
64 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
77 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
T39 |
0 |
70 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
75 |
0 |
0 |
T43 |
0 |
77 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7350 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
65 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
73 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T16 |
272564 |
64 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
77 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
T39 |
0 |
70 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
75 |
0 |
0 |
T43 |
0 |
77 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7350 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
65 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
73 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T16 |
22713 |
64 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
77 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
T39 |
0 |
70 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
75 |
0 |
0 |
T43 |
0 |
77 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7229 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
60 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
85 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T16 |
22713 |
85 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
77 |
0 |
0 |
T38 |
0 |
50 |
0 |
0 |
T39 |
0 |
77 |
0 |
0 |
T42 |
0 |
86 |
0 |
0 |
T43 |
0 |
68 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7289 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
60 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
85 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T16 |
272564 |
85 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
77 |
0 |
0 |
T38 |
0 |
51 |
0 |
0 |
T39 |
0 |
77 |
0 |
0 |
T42 |
0 |
86 |
0 |
0 |
T43 |
0 |
68 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7286 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
60 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
85 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T16 |
272564 |
85 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
77 |
0 |
0 |
T38 |
0 |
51 |
0 |
0 |
T39 |
0 |
77 |
0 |
0 |
T42 |
0 |
86 |
0 |
0 |
T43 |
0 |
68 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7286 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
60 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
85 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T16 |
22713 |
85 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
77 |
0 |
0 |
T38 |
0 |
51 |
0 |
0 |
T39 |
0 |
77 |
0 |
0 |
T42 |
0 |
86 |
0 |
0 |
T43 |
0 |
68 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7187 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
59 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
81 |
0 |
0 |
T12 |
0 |
81 |
0 |
0 |
T16 |
22713 |
72 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
51 |
0 |
0 |
T38 |
0 |
52 |
0 |
0 |
T39 |
0 |
68 |
0 |
0 |
T42 |
0 |
63 |
0 |
0 |
T43 |
0 |
73 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7245 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
59 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
81 |
0 |
0 |
T12 |
0 |
81 |
0 |
0 |
T16 |
272564 |
72 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
51 |
0 |
0 |
T38 |
0 |
53 |
0 |
0 |
T39 |
0 |
68 |
0 |
0 |
T42 |
0 |
63 |
0 |
0 |
T43 |
0 |
73 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7241 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
59 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
81 |
0 |
0 |
T12 |
0 |
81 |
0 |
0 |
T16 |
272564 |
72 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
51 |
0 |
0 |
T38 |
0 |
53 |
0 |
0 |
T39 |
0 |
68 |
0 |
0 |
T42 |
0 |
63 |
0 |
0 |
T43 |
0 |
73 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7241 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
59 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
81 |
0 |
0 |
T12 |
0 |
81 |
0 |
0 |
T16 |
22713 |
72 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
51 |
0 |
0 |
T38 |
0 |
53 |
0 |
0 |
T39 |
0 |
68 |
0 |
0 |
T42 |
0 |
63 |
0 |
0 |
T43 |
0 |
73 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7240 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
63 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
63 |
0 |
0 |
T12 |
0 |
60 |
0 |
0 |
T16 |
22713 |
80 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
62 |
0 |
0 |
T38 |
0 |
54 |
0 |
0 |
T39 |
0 |
66 |
0 |
0 |
T42 |
0 |
78 |
0 |
0 |
T43 |
0 |
95 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7301 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
63 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
63 |
0 |
0 |
T12 |
0 |
60 |
0 |
0 |
T16 |
272564 |
80 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
62 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
T39 |
0 |
66 |
0 |
0 |
T42 |
0 |
78 |
0 |
0 |
T43 |
0 |
95 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7298 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
63 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
63 |
0 |
0 |
T12 |
0 |
60 |
0 |
0 |
T16 |
272564 |
80 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
62 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
T39 |
0 |
66 |
0 |
0 |
T42 |
0 |
78 |
0 |
0 |
T43 |
0 |
95 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7298 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
63 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
63 |
0 |
0 |
T12 |
0 |
60 |
0 |
0 |
T16 |
22713 |
80 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
62 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
T39 |
0 |
66 |
0 |
0 |
T42 |
0 |
78 |
0 |
0 |
T43 |
0 |
95 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1288 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1349 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1345 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1345 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1322 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1382 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1379 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1379 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1309 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1367 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1363 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1363 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1316 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1375 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T16,T4,T25 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T16,T4,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
1372 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T7 |
500009 |
0 |
0 |
0 |
T8 |
185383 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T24 |
130601 |
0 |
0 |
0 |
T25 |
389888 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
108419 |
0 |
0 |
0 |
T46 |
259791 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1372 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T7 |
1020 |
0 |
0 |
0 |
T8 |
3902 |
0 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T24 |
522 |
0 |
0 |
0 |
T25 |
7798 |
1 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T39 |
0 |
3 |
0 |
0 |
T42 |
0 |
5 |
0 |
0 |
T43 |
0 |
2 |
0 |
0 |
T45 |
442 |
0 |
0 |
0 |
T46 |
633 |
0 |
0 |
0 |
T64 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
8022 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
65 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
73 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
64 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
77 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
8083 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
65 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
73 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
64 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
77 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
8078 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
65 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
73 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
64 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
77 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
8078 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
65 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
73 |
0 |
0 |
T12 |
0 |
78 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
64 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
77 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7927 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
60 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
85 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
85 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
77 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
50 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7988 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
60 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
85 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
85 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
77 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7985 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
60 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
85 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
85 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
77 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
51 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7985 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
60 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
85 |
0 |
0 |
T12 |
0 |
68 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
85 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
77 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7864 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
59 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
81 |
0 |
0 |
T12 |
0 |
81 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
72 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
51 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
52 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7926 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
59 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
81 |
0 |
0 |
T12 |
0 |
81 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
72 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
51 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
53 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
7921 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
59 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
81 |
0 |
0 |
T12 |
0 |
81 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
72 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
51 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
53 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7921 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
59 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
81 |
0 |
0 |
T12 |
0 |
81 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
72 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
51 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
53 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
7962 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
63 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
63 |
0 |
0 |
T12 |
0 |
60 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
80 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
62 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
54 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
8022 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
63 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
63 |
0 |
0 |
T12 |
0 |
60 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
80 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
62 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T16,T4,T25 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T16,T4,T25 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
8018 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
63 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
63 |
0 |
0 |
T12 |
0 |
60 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
80 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
62 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
8018 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
63 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
63 |
0 |
0 |
T12 |
0 |
60 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
80 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
62 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
55 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2078 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2142 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2137 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2137 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1944 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2007 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2003 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2003 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1963 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2020 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2017 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2017 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2000 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2058 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2055 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2055 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2035 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2096 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T1,T15,T16 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T15,T16 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T15,T16 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2090 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
1 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
1 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2090 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
1 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
1 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1978 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2039 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2037 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2037 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
1976 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2036 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2033 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2033 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2000 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2058 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T1,T16,T4 |
1 | 1 | Covered | T69,T70,T18 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T1,T6 |
0 | 1 | Covered | T1,T16,T4 |
1 | 0 | Covered | T69,T70,T18 |
1 | 1 | Covered | T1,T16,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T1,T6 |
0 |
Covered |
T5,T1,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1220955365 |
2055 |
0 |
0 |
T1 |
225871 |
24 |
0 |
0 |
T2 |
125625 |
0 |
0 |
0 |
T3 |
178235 |
0 |
0 |
0 |
T4 |
152051 |
3 |
0 |
0 |
T6 |
251387 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
151128 |
0 |
0 |
0 |
T14 |
109406 |
0 |
0 |
0 |
T15 |
209797 |
0 |
0 |
0 |
T16 |
272564 |
7 |
0 |
0 |
T17 |
49906 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7477497 |
2055 |
0 |
0 |
T1 |
64534 |
24 |
0 |
0 |
T2 |
1898 |
0 |
0 |
0 |
T3 |
3483 |
0 |
0 |
0 |
T4 |
12671 |
3 |
0 |
0 |
T6 |
502 |
0 |
0 |
0 |
T9 |
0 |
2 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T11 |
0 |
4 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
T13 |
402 |
0 |
0 |
0 |
T14 |
437 |
0 |
0 |
0 |
T15 |
4238 |
0 |
0 |
0 |
T16 |
22713 |
7 |
0 |
0 |
T17 |
415 |
0 |
0 |
0 |
T25 |
0 |
1 |
0 |
0 |
T37 |
0 |
8 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |