Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1565

1

T2

19

T3

18

T26

5

auto[1]

546

1

T2

5

T3

2

T26

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1579

1

T2

24

T3

16

T26

7

auto[1]

532

1

T3

4

T26

5

T7

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1558

1

T2

24

T3

20

T26

9

auto[1]

553

1

T26

3

T7

5

T10

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1572

1

T2

24

T3

18

T26

7

auto[1]

539

1

T3

2

T26

5

T7

11

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1951

1

T2

21

T3

20

T26

12

auto[1]

160

1

T2

3

T30

1

T81

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1930

1

T2

16

T3

18

T26

12

auto[1]

181

1

T2

8

T3

2

T46

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1917

1

T2

16

T3

18

T26

12

auto[1]

194

1

T2

8

T3

2

T238

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1953

1

T2

11

T3

14

T26

12

auto[1]

158

1

T2

13

T3

6

T238

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1962

1

T2

24

T3

18

T26

12

auto[1]

149

1

T3

2

T33

4

T343

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1511

1

T2

11

T3

14

T26

3

auto[1]

600

1

T2

13

T3

6

T26

9

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	837	1			T26	12		T7	9		T10	12
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	49	1			T30	1		T247	4		T218	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	61	1			T213	3		T218	4		T333	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	4	1			T344	4		-	-		-	-
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	42	1			T3	4		T240	5		T249	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T33	2		-	-		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	18	1			T345	1		T228	5		T346	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T228	2		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	51	1			T33	3		T240	5		T249	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	18	1			T238	1		T333	1		T210	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	11	1			T333	1		T71	4		T347	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	17	1			T249	2		T228	2		T210	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	27	1			T2	5		T3	2		T348	4
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T343	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	32	1			T46	2		T238	3		T249	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	35	1			T81	2		T349	32		T350	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	12	1			T3	2		T33	3		T213	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T351	1		T349	2		T331	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	29	1			T2	5		T240	1		T213	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T238	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T352	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	36	1			T353	6		T71	4		T346	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T354	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T355	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T348	4		T344	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T2	3		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

94

1

T83

3

T34

12

T343

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

132

1

T2

8

T249

2

T213

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

64

1

T2

5

T3

2

T26

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

143

1

T3

2

T10

10

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T242

6

T240

5

T333

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T31

5

T32

1

T247

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T108

2

T46

2

T238

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

89

1

T31

9

T82

12

T238

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T26

3

T145

4

T205

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

59

1

T240

1

T87

1

T356

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T291

1

T116

2

T87

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T33

3

T116

1

T249

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T357

2

T358

6

T184

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T53

1

T31

3

T81

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T359

3

T360

1

T344

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T53

13

T213

3

T326

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

54

1

T250

1

T32

4

T33

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T3

4

T31

12

T105

11

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T87

1

T348

4

T361

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T238

1

T254

8

T88

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T7

4

T53

1

T242

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T26

5

T243

3

T362

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T105

1

T346

5

T363

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

76

1

T31

4

T33

2

T240

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

34

1

T10

1

T83

1

T34

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T10

1

T30

1

T145

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T7

3

T34

2

T87

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

19

1

T183

1

T225

3

T251

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T7

2

T108

3

T362

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T253

1

T364

1

T184

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T145

1

T87

1

T253

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded