Summary for Variable cp_en_override
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_en_override
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1243 |
1 |
|
|
T17 |
13 |
|
T47 |
10 |
|
T63 |
9 |
auto[1] |
1187 |
1 |
|
|
T17 |
7 |
|
T47 |
10 |
|
T63 |
11 |
Summary for Variable cp_override_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_override_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
from_1to0 |
581 |
1 |
|
|
T17 |
3 |
|
T47 |
4 |
|
T63 |
5 |
from_0to1 |
570 |
1 |
|
|
T17 |
3 |
|
T47 |
4 |
|
T63 |
5 |
Summary for Variable cp_pin_allowed_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_0
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1213 |
1 |
|
|
T17 |
11 |
|
T47 |
12 |
|
T63 |
8 |
auto[1] |
1217 |
1 |
|
|
T17 |
9 |
|
T47 |
8 |
|
T63 |
12 |
Summary for Variable cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1235 |
1 |
|
|
T17 |
10 |
|
T47 |
9 |
|
T63 |
9 |
auto[1] |
1195 |
1 |
|
|
T17 |
10 |
|
T47 |
11 |
|
T63 |
11 |
Summary for Cross cp_pin_cross
Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cp_pin_cross
Bins
cp_en_override | cp_override_value | cp_pin_allowed_0 | cp_pin_allowed_1 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
from_1to0 |
auto[0] |
auto[0] |
75 |
1 |
|
|
T17 |
1 |
|
T377 |
1 |
|
T133 |
1 |
auto[0] |
from_1to0 |
auto[0] |
auto[1] |
69 |
1 |
|
|
T17 |
1 |
|
T10 |
1 |
|
T302 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[0] |
83 |
1 |
|
|
T17 |
1 |
|
T63 |
2 |
|
T10 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[1] |
69 |
1 |
|
|
T47 |
1 |
|
T63 |
1 |
|
T174 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[0] |
76 |
1 |
|
|
T17 |
1 |
|
T63 |
1 |
|
T10 |
3 |
auto[0] |
from_0to1 |
auto[0] |
auto[1] |
73 |
1 |
|
|
T47 |
1 |
|
T10 |
1 |
|
T174 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[0] |
82 |
1 |
|
|
T17 |
1 |
|
T10 |
1 |
|
T44 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[1] |
68 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[0] |
73 |
1 |
|
|
T63 |
1 |
|
T10 |
3 |
|
T377 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[1] |
70 |
1 |
|
|
T47 |
1 |
|
T10 |
3 |
|
T174 |
3 |
auto[1] |
from_1to0 |
auto[1] |
auto[0] |
68 |
1 |
|
|
T47 |
1 |
|
T10 |
1 |
|
T173 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[1] |
74 |
1 |
|
|
T47 |
1 |
|
T63 |
1 |
|
T10 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[0] |
71 |
1 |
|
|
T47 |
2 |
|
T10 |
1 |
|
T173 |
2 |
auto[1] |
from_0to1 |
auto[0] |
auto[1] |
61 |
1 |
|
|
T63 |
1 |
|
T174 |
1 |
|
T377 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[0] |
53 |
1 |
|
|
T63 |
1 |
|
T10 |
2 |
|
T173 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[1] |
86 |
1 |
|
|
T63 |
1 |
|
T10 |
3 |
|
T173 |
2 |
Summary for Variable cp_en_override
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_en_override
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1171 |
1 |
|
|
T17 |
7 |
|
T47 |
14 |
|
T63 |
8 |
auto[1] |
1259 |
1 |
|
|
T17 |
13 |
|
T47 |
6 |
|
T63 |
12 |
Summary for Variable cp_override_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_override_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
from_1to0 |
588 |
1 |
|
|
T17 |
4 |
|
T47 |
4 |
|
T63 |
5 |
from_0to1 |
585 |
1 |
|
|
T17 |
5 |
|
T47 |
4 |
|
T63 |
5 |
Summary for Variable cp_pin_allowed_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_0
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1174 |
1 |
|
|
T17 |
9 |
|
T47 |
7 |
|
T63 |
12 |
auto[1] |
1256 |
1 |
|
|
T17 |
11 |
|
T47 |
13 |
|
T63 |
8 |
Summary for Variable cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1178 |
1 |
|
|
T17 |
12 |
|
T47 |
8 |
|
T63 |
11 |
auto[1] |
1252 |
1 |
|
|
T17 |
8 |
|
T47 |
12 |
|
T63 |
9 |
Summary for Cross cp_pin_cross
Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cp_pin_cross
Bins
cp_en_override | cp_override_value | cp_pin_allowed_0 | cp_pin_allowed_1 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
from_1to0 |
auto[0] |
auto[0] |
75 |
1 |
|
|
T17 |
1 |
|
T174 |
1 |
|
T44 |
2 |
auto[0] |
from_1to0 |
auto[0] |
auto[1] |
67 |
1 |
|
|
T173 |
1 |
|
T44 |
1 |
|
T377 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[0] |
75 |
1 |
|
|
T17 |
1 |
|
T63 |
2 |
|
T10 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[1] |
88 |
1 |
|
|
T47 |
3 |
|
T10 |
1 |
|
T303 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[0] |
65 |
1 |
|
|
T174 |
1 |
|
T44 |
1 |
|
T31 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[1] |
74 |
1 |
|
|
T17 |
1 |
|
T47 |
3 |
|
T63 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[0] |
69 |
1 |
|
|
T10 |
1 |
|
T173 |
1 |
|
T174 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[1] |
73 |
1 |
|
|
T17 |
1 |
|
T63 |
1 |
|
T10 |
2 |
auto[1] |
from_1to0 |
auto[0] |
auto[0] |
69 |
1 |
|
|
T63 |
2 |
|
T10 |
3 |
|
T31 |
2 |
auto[1] |
from_1to0 |
auto[0] |
auto[1] |
69 |
1 |
|
|
T10 |
1 |
|
T173 |
2 |
|
T44 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[0] |
67 |
1 |
|
|
T17 |
1 |
|
T63 |
1 |
|
T174 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[1] |
78 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T10 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[0] |
67 |
1 |
|
|
T63 |
1 |
|
T174 |
1 |
|
T303 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[1] |
76 |
1 |
|
|
T17 |
1 |
|
T63 |
2 |
|
T10 |
2 |
auto[1] |
from_0to1 |
auto[1] |
auto[0] |
84 |
1 |
|
|
T17 |
2 |
|
T47 |
1 |
|
T10 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[1] |
77 |
1 |
|
|
T377 |
1 |
|
T303 |
1 |
|
T135 |
1 |
Summary for Variable cp_en_override
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_en_override
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1208 |
1 |
|
|
T17 |
8 |
|
T47 |
10 |
|
T63 |
13 |
auto[1] |
1222 |
1 |
|
|
T17 |
12 |
|
T47 |
10 |
|
T63 |
7 |
Summary for Variable cp_override_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_override_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
from_1to0 |
589 |
1 |
|
|
T17 |
4 |
|
T47 |
5 |
|
T63 |
5 |
from_0to1 |
583 |
1 |
|
|
T17 |
4 |
|
T47 |
5 |
|
T63 |
6 |
Summary for Variable cp_pin_allowed_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_0
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1218 |
1 |
|
|
T17 |
12 |
|
T47 |
10 |
|
T63 |
12 |
auto[1] |
1212 |
1 |
|
|
T17 |
8 |
|
T47 |
10 |
|
T63 |
8 |
Summary for Variable cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1250 |
1 |
|
|
T17 |
12 |
|
T47 |
12 |
|
T63 |
13 |
auto[1] |
1180 |
1 |
|
|
T17 |
8 |
|
T47 |
8 |
|
T63 |
7 |
Summary for Cross cp_pin_cross
Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cp_pin_cross
Bins
cp_en_override | cp_override_value | cp_pin_allowed_0 | cp_pin_allowed_1 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
from_1to0 |
auto[0] |
auto[0] |
79 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
3 |
auto[0] |
from_1to0 |
auto[0] |
auto[1] |
83 |
1 |
|
|
T10 |
1 |
|
T44 |
1 |
|
T377 |
1 |
auto[0] |
from_1to0 |
auto[1] |
auto[0] |
83 |
1 |
|
|
T17 |
2 |
|
T63 |
1 |
|
T10 |
1 |
auto[0] |
from_1to0 |
auto[1] |
auto[1] |
60 |
1 |
|
|
T10 |
1 |
|
T377 |
1 |
|
T133 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[0] |
77 |
1 |
|
|
T47 |
1 |
|
T63 |
2 |
|
T10 |
2 |
auto[0] |
from_0to1 |
auto[0] |
auto[1] |
65 |
1 |
|
|
T10 |
1 |
|
T302 |
1 |
|
T135 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[0] |
69 |
1 |
|
|
T63 |
1 |
|
T44 |
1 |
|
T31 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[1] |
79 |
1 |
|
|
T17 |
1 |
|
T47 |
2 |
|
T10 |
3 |
auto[1] |
from_1to0 |
auto[0] |
auto[0] |
78 |
1 |
|
|
T17 |
1 |
|
T47 |
2 |
|
T10 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[1] |
64 |
1 |
|
|
T63 |
1 |
|
T10 |
1 |
|
T377 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[0] |
83 |
1 |
|
|
T47 |
1 |
|
T10 |
1 |
|
T174 |
3 |
auto[1] |
from_1to0 |
auto[1] |
auto[1] |
59 |
1 |
|
|
T47 |
1 |
|
T10 |
2 |
|
T173 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[0] |
81 |
1 |
|
|
T17 |
1 |
|
T63 |
2 |
|
T10 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[1] |
68 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T10 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[0] |
73 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[1] |
71 |
1 |
|
|
T10 |
1 |
|
T174 |
2 |
|
T44 |
1 |
Summary for Variable cp_en_override
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_en_override
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1227 |
1 |
|
|
T17 |
12 |
|
T47 |
9 |
|
T63 |
7 |
auto[1] |
1203 |
1 |
|
|
T17 |
8 |
|
T47 |
11 |
|
T63 |
13 |
Summary for Variable cp_override_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_override_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
from_1to0 |
569 |
1 |
|
|
T17 |
5 |
|
T47 |
6 |
|
T63 |
5 |
from_0to1 |
573 |
1 |
|
|
T17 |
5 |
|
T47 |
7 |
|
T63 |
4 |
Summary for Variable cp_pin_allowed_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_0
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1158 |
1 |
|
|
T17 |
11 |
|
T47 |
10 |
|
T63 |
7 |
auto[1] |
1272 |
1 |
|
|
T17 |
9 |
|
T47 |
10 |
|
T63 |
13 |
Summary for Variable cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1237 |
1 |
|
|
T17 |
11 |
|
T47 |
12 |
|
T63 |
8 |
auto[1] |
1193 |
1 |
|
|
T17 |
9 |
|
T47 |
8 |
|
T63 |
12 |
Summary for Cross cp_pin_cross
Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cp_pin_cross
Bins
cp_en_override | cp_override_value | cp_pin_allowed_0 | cp_pin_allowed_1 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
from_1to0 |
auto[0] |
auto[0] |
64 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T173 |
2 |
auto[0] |
from_1to0 |
auto[0] |
auto[1] |
63 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T377 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[0] |
74 |
1 |
|
|
T17 |
2 |
|
T63 |
1 |
|
T10 |
1 |
auto[0] |
from_1to0 |
auto[1] |
auto[1] |
89 |
1 |
|
|
T10 |
2 |
|
T174 |
1 |
|
T44 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[0] |
73 |
1 |
|
|
T17 |
2 |
|
T174 |
1 |
|
T44 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[1] |
58 |
1 |
|
|
T47 |
2 |
|
T10 |
1 |
|
T44 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[0] |
80 |
1 |
|
|
T47 |
1 |
|
T174 |
2 |
|
T377 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[1] |
80 |
1 |
|
|
T17 |
2 |
|
T63 |
1 |
|
T10 |
3 |
auto[1] |
from_1to0 |
auto[0] |
auto[0] |
65 |
1 |
|
|
T47 |
2 |
|
T63 |
1 |
|
T10 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[1] |
59 |
1 |
|
|
T377 |
1 |
|
T303 |
1 |
|
T135 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[0] |
69 |
1 |
|
|
T47 |
1 |
|
T63 |
1 |
|
T10 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[1] |
86 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
2 |
auto[1] |
from_0to1 |
auto[0] |
auto[0] |
61 |
1 |
|
|
T173 |
2 |
|
T174 |
1 |
|
T377 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[1] |
68 |
1 |
|
|
T63 |
1 |
|
T10 |
2 |
|
T174 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[0] |
76 |
1 |
|
|
T47 |
2 |
|
T63 |
1 |
|
T377 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[1] |
77 |
1 |
|
|
T17 |
1 |
|
T47 |
2 |
|
T63 |
1 |
Summary for Variable cp_en_override
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_en_override
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1216 |
1 |
|
|
T17 |
7 |
|
T47 |
9 |
|
T63 |
9 |
auto[1] |
1214 |
1 |
|
|
T17 |
13 |
|
T47 |
11 |
|
T63 |
11 |
Summary for Variable cp_override_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_override_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
from_1to0 |
581 |
1 |
|
|
T17 |
5 |
|
T47 |
4 |
|
T63 |
5 |
from_0to1 |
578 |
1 |
|
|
T17 |
4 |
|
T47 |
4 |
|
T63 |
5 |
Summary for Variable cp_pin_allowed_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_0
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1189 |
1 |
|
|
T17 |
12 |
|
T47 |
5 |
|
T63 |
8 |
auto[1] |
1241 |
1 |
|
|
T17 |
8 |
|
T47 |
15 |
|
T63 |
12 |
Summary for Variable cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1198 |
1 |
|
|
T17 |
9 |
|
T47 |
7 |
|
T63 |
7 |
auto[1] |
1232 |
1 |
|
|
T17 |
11 |
|
T47 |
13 |
|
T63 |
13 |
Summary for Cross cp_pin_cross
Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cp_pin_cross
Bins
cp_en_override | cp_override_value | cp_pin_allowed_0 | cp_pin_allowed_1 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
from_1to0 |
auto[0] |
auto[0] |
80 |
1 |
|
|
T17 |
1 |
|
T10 |
4 |
|
T377 |
1 |
auto[0] |
from_1to0 |
auto[0] |
auto[1] |
73 |
1 |
|
|
T63 |
1 |
|
T173 |
1 |
|
T44 |
1 |
auto[0] |
from_1to0 |
auto[1] |
auto[0] |
74 |
1 |
|
|
T17 |
1 |
|
T10 |
1 |
|
T173 |
1 |
auto[0] |
from_1to0 |
auto[1] |
auto[1] |
82 |
1 |
|
|
T47 |
2 |
|
T63 |
1 |
|
T303 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[0] |
73 |
1 |
|
|
T173 |
1 |
|
T44 |
1 |
|
T377 |
3 |
auto[0] |
from_0to1 |
auto[0] |
auto[1] |
72 |
1 |
|
|
T17 |
1 |
|
T63 |
1 |
|
T10 |
3 |
auto[0] |
from_0to1 |
auto[1] |
auto[0] |
65 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T10 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[1] |
64 |
1 |
|
|
T44 |
1 |
|
T31 |
2 |
|
T302 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[0] |
59 |
1 |
|
|
T174 |
2 |
|
T377 |
2 |
|
T135 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[1] |
67 |
1 |
|
|
T17 |
2 |
|
T63 |
1 |
|
T10 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[0] |
74 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
2 |
auto[1] |
from_1to0 |
auto[1] |
auto[1] |
72 |
1 |
|
|
T47 |
1 |
|
T10 |
2 |
|
T174 |
2 |
auto[1] |
from_0to1 |
auto[0] |
auto[0] |
78 |
1 |
|
|
T63 |
1 |
|
T10 |
4 |
|
T44 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[1] |
60 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[0] |
89 |
1 |
|
|
T173 |
3 |
|
T44 |
2 |
|
T31 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[1] |
77 |
1 |
|
|
T17 |
1 |
|
T47 |
2 |
|
T63 |
2 |
Summary for Variable cp_en_override
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_en_override
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1189 |
1 |
|
|
T17 |
10 |
|
T47 |
9 |
|
T63 |
9 |
auto[1] |
1241 |
1 |
|
|
T17 |
10 |
|
T47 |
11 |
|
T63 |
11 |
Summary for Variable cp_override_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_override_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
from_1to0 |
587 |
1 |
|
|
T17 |
4 |
|
T47 |
5 |
|
T63 |
5 |
from_0to1 |
588 |
1 |
|
|
T17 |
5 |
|
T47 |
5 |
|
T63 |
4 |
Summary for Variable cp_pin_allowed_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_0
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1209 |
1 |
|
|
T17 |
14 |
|
T47 |
10 |
|
T63 |
13 |
auto[1] |
1221 |
1 |
|
|
T17 |
6 |
|
T47 |
10 |
|
T63 |
7 |
Summary for Variable cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1218 |
1 |
|
|
T17 |
10 |
|
T47 |
10 |
|
T63 |
11 |
auto[1] |
1212 |
1 |
|
|
T17 |
10 |
|
T47 |
10 |
|
T63 |
9 |
Summary for Cross cp_pin_cross
Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cp_pin_cross
Bins
cp_en_override | cp_override_value | cp_pin_allowed_0 | cp_pin_allowed_1 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
from_1to0 |
auto[0] |
auto[0] |
74 |
1 |
|
|
T47 |
2 |
|
T63 |
1 |
|
T10 |
1 |
auto[0] |
from_1to0 |
auto[0] |
auto[1] |
69 |
1 |
|
|
T17 |
1 |
|
T63 |
1 |
|
T174 |
1 |
auto[0] |
from_1to0 |
auto[1] |
auto[0] |
72 |
1 |
|
|
T10 |
1 |
|
T173 |
1 |
|
T31 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[1] |
73 |
1 |
|
|
T47 |
1 |
|
T10 |
1 |
|
T173 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[0] |
78 |
1 |
|
|
T17 |
1 |
|
T10 |
1 |
|
T174 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[1] |
60 |
1 |
|
|
T17 |
1 |
|
T63 |
1 |
|
T173 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[0] |
74 |
1 |
|
|
T17 |
1 |
|
T47 |
3 |
|
T10 |
2 |
auto[0] |
from_0to1 |
auto[1] |
auto[1] |
70 |
1 |
|
|
T63 |
1 |
|
T10 |
1 |
|
T44 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[0] |
81 |
1 |
|
|
T17 |
1 |
|
T63 |
2 |
|
T10 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[1] |
74 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[0] |
77 |
1 |
|
|
T10 |
1 |
|
T173 |
1 |
|
T44 |
2 |
auto[1] |
from_1to0 |
auto[1] |
auto[1] |
67 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T10 |
2 |
auto[1] |
from_0to1 |
auto[0] |
auto[0] |
78 |
1 |
|
|
T173 |
1 |
|
T302 |
1 |
|
T133 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[1] |
79 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[0] |
72 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T63 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[1] |
77 |
1 |
|
|
T10 |
2 |
|
T174 |
2 |
|
T31 |
1 |
Summary for Variable cp_en_override
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_en_override
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1229 |
1 |
|
|
T17 |
9 |
|
T47 |
6 |
|
T63 |
7 |
auto[1] |
1201 |
1 |
|
|
T17 |
11 |
|
T47 |
14 |
|
T63 |
13 |
Summary for Variable cp_override_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_override_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
from_1to0 |
592 |
1 |
|
|
T17 |
4 |
|
T47 |
4 |
|
T63 |
5 |
from_0to1 |
590 |
1 |
|
|
T17 |
3 |
|
T47 |
3 |
|
T63 |
5 |
Summary for Variable cp_pin_allowed_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_0
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1247 |
1 |
|
|
T17 |
10 |
|
T47 |
8 |
|
T63 |
8 |
auto[1] |
1183 |
1 |
|
|
T17 |
10 |
|
T47 |
12 |
|
T63 |
12 |
Summary for Variable cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1258 |
1 |
|
|
T17 |
11 |
|
T47 |
7 |
|
T63 |
11 |
auto[1] |
1172 |
1 |
|
|
T17 |
9 |
|
T47 |
13 |
|
T63 |
9 |
Summary for Cross cp_pin_cross
Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cp_pin_cross
Bins
cp_en_override | cp_override_value | cp_pin_allowed_0 | cp_pin_allowed_1 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
from_1to0 |
auto[0] |
auto[0] |
90 |
1 |
|
|
T63 |
1 |
|
T10 |
2 |
|
T174 |
1 |
auto[0] |
from_1to0 |
auto[0] |
auto[1] |
71 |
1 |
|
|
T63 |
1 |
|
T10 |
1 |
|
T173 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[0] |
79 |
1 |
|
|
T173 |
1 |
|
T44 |
1 |
|
T377 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[1] |
64 |
1 |
|
|
T17 |
2 |
|
T47 |
1 |
|
T173 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[0] |
84 |
1 |
|
|
T47 |
1 |
|
T63 |
1 |
|
T10 |
2 |
auto[0] |
from_0to1 |
auto[0] |
auto[1] |
73 |
1 |
|
|
T47 |
1 |
|
T10 |
1 |
|
T173 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[0] |
82 |
1 |
|
|
T47 |
1 |
|
T10 |
2 |
|
T173 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[1] |
72 |
1 |
|
|
T63 |
1 |
|
T174 |
1 |
|
T44 |
2 |
auto[1] |
from_1to0 |
auto[0] |
auto[0] |
76 |
1 |
|
|
T10 |
1 |
|
T377 |
1 |
|
T302 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[1] |
69 |
1 |
|
|
T17 |
1 |
|
T10 |
1 |
|
T173 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[0] |
75 |
1 |
|
|
T63 |
2 |
|
T10 |
3 |
|
T173 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[1] |
68 |
1 |
|
|
T17 |
1 |
|
T47 |
3 |
|
T63 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[0] |
74 |
1 |
|
|
T10 |
2 |
|
T173 |
1 |
|
T377 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[1] |
72 |
1 |
|
|
T17 |
2 |
|
T63 |
1 |
|
T10 |
2 |
auto[1] |
from_0to1 |
auto[1] |
auto[0] |
63 |
1 |
|
|
T17 |
1 |
|
T63 |
2 |
|
T173 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[1] |
70 |
1 |
|
|
T377 |
1 |
|
T31 |
1 |
|
T302 |
1 |
Summary for Variable cp_en_override
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_en_override
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1233 |
1 |
|
|
T17 |
7 |
|
T47 |
11 |
|
T63 |
8 |
auto[1] |
1197 |
1 |
|
|
T17 |
13 |
|
T47 |
9 |
|
T63 |
12 |
Summary for Variable cp_override_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_override_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
from_1to0 |
567 |
1 |
|
|
T17 |
4 |
|
T47 |
7 |
|
T63 |
5 |
from_0to1 |
564 |
1 |
|
|
T17 |
4 |
|
T47 |
8 |
|
T63 |
5 |
Summary for Variable cp_pin_allowed_0
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_0
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1206 |
1 |
|
|
T17 |
13 |
|
T47 |
12 |
|
T63 |
8 |
auto[1] |
1224 |
1 |
|
|
T17 |
7 |
|
T47 |
8 |
|
T63 |
12 |
Summary for Variable cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pin_allowed_1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1213 |
1 |
|
|
T17 |
14 |
|
T47 |
9 |
|
T63 |
10 |
auto[1] |
1217 |
1 |
|
|
T17 |
6 |
|
T47 |
11 |
|
T63 |
10 |
Summary for Cross cp_pin_cross
Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cp_pin_cross
Bins
cp_en_override | cp_override_value | cp_pin_allowed_0 | cp_pin_allowed_1 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
from_1to0 |
auto[0] |
auto[0] |
62 |
1 |
|
|
T17 |
1 |
|
T174 |
1 |
|
T31 |
1 |
auto[0] |
from_1to0 |
auto[0] |
auto[1] |
69 |
1 |
|
|
T47 |
2 |
|
T10 |
1 |
|
T174 |
1 |
auto[0] |
from_1to0 |
auto[1] |
auto[0] |
76 |
1 |
|
|
T47 |
2 |
|
T63 |
1 |
|
T10 |
2 |
auto[0] |
from_1to0 |
auto[1] |
auto[1] |
64 |
1 |
|
|
T63 |
1 |
|
T10 |
2 |
|
T173 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[0] |
83 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T10 |
1 |
auto[0] |
from_0to1 |
auto[0] |
auto[1] |
73 |
1 |
|
|
T47 |
2 |
|
T63 |
1 |
|
T174 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[0] |
73 |
1 |
|
|
T17 |
1 |
|
T47 |
1 |
|
T10 |
1 |
auto[0] |
from_0to1 |
auto[1] |
auto[1] |
67 |
1 |
|
|
T10 |
1 |
|
T173 |
1 |
|
T174 |
1 |
auto[1] |
from_1to0 |
auto[0] |
auto[0] |
81 |
1 |
|
|
T47 |
2 |
|
T63 |
2 |
|
T10 |
3 |
auto[1] |
from_1to0 |
auto[0] |
auto[1] |
77 |
1 |
|
|
T17 |
2 |
|
T44 |
2 |
|
T377 |
2 |
auto[1] |
from_1to0 |
auto[1] |
auto[0] |
76 |
1 |
|
|
T17 |
1 |
|
T10 |
2 |
|
T173 |
1 |
auto[1] |
from_1to0 |
auto[1] |
auto[1] |
62 |
1 |
|
|
T47 |
1 |
|
T63 |
1 |
|
T302 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[0] |
72 |
1 |
|
|
T47 |
2 |
|
T63 |
1 |
|
T10 |
1 |
auto[1] |
from_0to1 |
auto[0] |
auto[1] |
58 |
1 |
|
|
T10 |
1 |
|
T173 |
1 |
|
T303 |
2 |
auto[1] |
from_0to1 |
auto[1] |
auto[0] |
57 |
1 |
|
|
T17 |
2 |
|
T174 |
1 |
|
T44 |
1 |
auto[1] |
from_0to1 |
auto[1] |
auto[1] |
81 |
1 |
|
|
T47 |
2 |
|
T63 |
3 |
|
T10 |
5 |