Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158821	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118869

1

T5

2

T1

24

T6

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143681	1			T5	2		T1	27		T6	8
values[0x0]	66562	1			T5	1		T1	6		T6	3
values[0x1]	67447	1			T1	11		T6	5		T2	285

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	128301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149389

1

T5

3

T1

26

T6

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	792	1			T2	7		T16	1		T17	1
valid_sources[0x01]	781	1			T2	2		T19	2		T3	4
valid_sources[0x02]	945	1			T2	2		T16	1		T17	1
valid_sources[0x03]	994	1			T2	6		T19	1		T3	7
valid_sources[0x04]	903	1			T2	2		T3	4		T7	1
valid_sources[0x05]	1058	1			T2	4		T19	3		T29	1
valid_sources[0x06]	924	1			T2	4		T19	3		T3	7
valid_sources[0x07]	1400	1			T2	5		T17	7		T18	3
valid_sources[0x08]	991	1			T2	5		T19	1		T3	5
valid_sources[0x09]	983	1			T2	5		T19	1		T3	5
valid_sources[0x0a]	994	1			T2	4		T47	1		T3	3
valid_sources[0x0b]	1089	1			T2	5		T24	1		T3	3
valid_sources[0x0c]	2432	1			T2	6		T19	1		T3	4
valid_sources[0x0d]	1502	1			T2	5		T19	4		T3	1
valid_sources[0x0e]	1190	1			T17	1		T19	3		T3	1
valid_sources[0x0f]	1059	1			T2	4		T17	1		T19	1
valid_sources[0x10]	1519	1			T2	4		T17	1		T19	1
valid_sources[0x11]	1282	1			T2	1		T19	2		T3	14
valid_sources[0x12]	1203	1			T2	2		T19	1		T3	4
valid_sources[0x13]	1022	1			T2	3		T24	1		T3	1
valid_sources[0x14]	975	1			T2	9		T3	1		T7	3
valid_sources[0x15]	1123	1			T2	3		T17	2		T3	3
valid_sources[0x16]	1094	1			T2	2		T19	1		T48	43
valid_sources[0x17]	1330	1			T2	4		T19	1		T24	1
valid_sources[0x18]	845	1			T2	2		T3	4		T7	2
valid_sources[0x19]	874	1			T2	1		T3	4		T7	1
valid_sources[0x1a]	931	1			T2	3		T17	1		T7	2
valid_sources[0x1b]	1069	1			T2	5		T19	2		T3	8
valid_sources[0x1c]	1292	1			T2	3		T19	2		T47	2
valid_sources[0x1d]	912	1			T2	4		T14	8		T17	1
valid_sources[0x1e]	940	1			T2	2		T16	1		T3	3
valid_sources[0x1f]	1124	1			T2	3		T19	1		T3	3
valid_sources[0x20]	2225	1			T2	2		T15	62		T19	2
valid_sources[0x21]	919	1			T2	2		T7	2		T63	2
valid_sources[0x22]	861	1			T2	1		T19	3		T3	4
valid_sources[0x23]	934	1			T2	2		T47	16		T3	4
valid_sources[0x24]	955	1			T2	6		T3	9		T9	1
valid_sources[0x25]	1039	1			T2	2		T16	2		T19	1
valid_sources[0x26]	828	1			T2	2		T3	8		T51	4
valid_sources[0x27]	971	1			T2	3		T17	1		T19	2
valid_sources[0x28]	997	1			T2	2		T3	1		T51	2
valid_sources[0x29]	894	1			T2	1		T17	4		T3	1
valid_sources[0x2a]	847	1			T2	3		T17	7		T19	2
valid_sources[0x2b]	933	1			T2	4		T19	2		T3	8
valid_sources[0x2c]	1391	1			T2	2		T19	1		T3	9
valid_sources[0x2d]	862	1			T19	1		T3	3		T7	2
valid_sources[0x2e]	1457	1			T1	44		T2	3		T16	2
valid_sources[0x2f]	952	1			T2	1		T17	2		T3	3
valid_sources[0x30]	989	1			T2	2		T17	2		T19	1
valid_sources[0x31]	1448	1			T2	3		T19	4		T3	6
valid_sources[0x32]	840	1			T2	2		T3	6		T26	43
valid_sources[0x33]	891	1			T2	4		T17	2		T24	1
valid_sources[0x34]	1031	1			T2	1		T19	3		T3	3
valid_sources[0x35]	812	1			T17	1		T19	3		T3	1
valid_sources[0x36]	1694	1			T2	7		T16	1		T19	2
valid_sources[0x37]	1767	1			T2	6		T19	1		T24	1
valid_sources[0x38]	867	1			T2	1		T47	3		T3	7
valid_sources[0x39]	934	1			T17	5		T19	2		T7	2
valid_sources[0x3a]	825	1			T2	2		T17	6		T19	1
valid_sources[0x3b]	938	1			T2	3		T3	8		T7	3
valid_sources[0x3c]	1159	1			T2	5		T17	2		T3	5
valid_sources[0x3d]	1183	1			T2	2		T3	2		T9	1
valid_sources[0x3e]	846	1			T2	5		T13	9		T16	1
valid_sources[0x3f]	921	1			T2	6		T3	7		T7	3
valid_sources[0x40]	923	1			T2	1		T3	4		T114	9
valid_sources[0x41]	1035	1			T2	3		T3	2		T26	29
valid_sources[0x42]	896	1			T24	1		T3	4		T7	1
valid_sources[0x43]	1060	1			T2	4		T14	3		T17	1
valid_sources[0x44]	1097	1			T2	1		T16	1		T17	1
valid_sources[0x45]	1134	1			T2	4		T19	1		T3	1
valid_sources[0x46]	839	1			T2	3		T3	4		T7	1
valid_sources[0x47]	883	1			T2	4		T18	1		T19	1
valid_sources[0x48]	827	1			T2	4		T17	2		T3	7
valid_sources[0x49]	2345	1			T2	4		T14	2		T3	3
valid_sources[0x4a]	989	1			T2	5		T3	10		T7	2
valid_sources[0x4b]	1025	1			T2	3		T14	1		T16	1
valid_sources[0x4c]	1489	1			T2	2		T19	1		T24	1
valid_sources[0x4d]	1047	1			T2	7		T16	1		T17	1
valid_sources[0x4e]	961	1			T2	2		T24	1		T3	3
valid_sources[0x4f]	1259	1			T2	1		T14	1		T3	3
valid_sources[0x50]	911	1			T2	4		T3	2		T51	13
valid_sources[0x51]	844	1			T2	5		T19	3		T24	1
valid_sources[0x52]	1098	1			T2	5		T19	4		T24	1
valid_sources[0x53]	812	1			T2	4		T19	2		T3	7
valid_sources[0x54]	872	1			T2	1		T19	1		T26	15
valid_sources[0x55]	956	1			T2	2		T3	7		T63	1
valid_sources[0x56]	763	1			T2	3		T3	2		T63	1
valid_sources[0x57]	1141	1			T2	4		T14	1		T3	3
valid_sources[0x58]	1230	1			T2	2		T19	2		T3	7
valid_sources[0x59]	956	1			T2	4		T14	1		T16	1
valid_sources[0x5a]	763	1			T24	1		T3	3		T9	4
valid_sources[0x5b]	1729	1			T2	2		T19	1		T3	5
valid_sources[0x5c]	962	1			T2	4		T24	1		T3	4
valid_sources[0x5d]	1012	1			T2	2		T19	1		T26	5
valid_sources[0x5e]	1197	1			T2	1		T3	3		T7	1
valid_sources[0x5f]	686	1			T2	4		T16	1		T19	3
valid_sources[0x60]	952	1			T2	2		T19	1		T3	5
valid_sources[0x61]	1222	1			T2	6		T16	1		T17	2
valid_sources[0x62]	1980	1			T2	6		T19	3		T3	2
valid_sources[0x63]	1634	1			T2	6		T16	1		T17	6
valid_sources[0x64]	888	1			T2	6		T17	1		T19	1
valid_sources[0x65]	939	1			T2	1		T19	2		T24	1
valid_sources[0x66]	1043	1			T2	3		T19	1		T3	3
valid_sources[0x67]	1074	1			T2	4		T16	1		T19	1
valid_sources[0x68]	866	1			T2	6		T17	2		T19	1
valid_sources[0x69]	940	1			T2	4		T3	3		T63	1
valid_sources[0x6a]	1359	1			T2	5		T16	1		T19	1
valid_sources[0x6b]	808	1			T2	2		T24	1		T47	6
valid_sources[0x6c]	911	1			T2	4		T17	3		T19	4
valid_sources[0x6d]	930	1			T2	4		T16	1		T17	2
valid_sources[0x6e]	2459	1			T17	1		T19	3		T24	1
valid_sources[0x6f]	887	1			T2	10		T16	1		T19	2
valid_sources[0x70]	1119	1			T2	6		T24	1		T4	1
valid_sources[0x71]	1058	1			T2	1		T18	1		T3	9
valid_sources[0x72]	1437	1			T2	3		T16	1		T17	2
valid_sources[0x73]	950	1			T2	3		T19	3		T3	7
valid_sources[0x74]	887	1			T2	2		T17	2		T3	4
valid_sources[0x75]	1061	1			T2	3		T19	3		T3	9
valid_sources[0x76]	1230	1			T2	1		T16	2		T19	1
valid_sources[0x77]	1054	1			T3	7		T7	1		T63	1
valid_sources[0x78]	2034	1			T2	6		T24	1		T3	4
valid_sources[0x79]	1001	1			T2	7		T16	2		T19	1
valid_sources[0x7a]	917	1			T2	2		T19	4		T3	3
valid_sources[0x7b]	912	1			T2	2		T19	1		T24	1
valid_sources[0x7c]	963	1			T2	3		T16	1		T19	5
valid_sources[0x7d]	898	1			T2	2		T29	1		T3	1
valid_sources[0x7e]	1173	1			T2	5		T19	1		T3	5
valid_sources[0x7f]	1884	1			T2	4		T16	1		T17	1
valid_sources[0x80]	912	1			T2	6		T47	3		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64068

1

T5

1

T1

14

T6

4

values[0x0]

all_enables

biggest_size

32198

1

T5

1

T1

4

T6

2

values[0x1]

all_enables

biggest_size

22603

1

T1

6

T6

2

T2

61