Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T13,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T6,T13,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T13,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T13,T17
1	0	Covered	T5,T1,T6
1	1	Covered	T6,T13,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T13,T17
0	1	Covered	T37,T84,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T13,T17
0	1	Covered	T6,T13,T17
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T13,T17
1	-	Covered	T6,T13,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T13,T17
DetectSt	168	Covered	T6,T13,T17
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T6,T13,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T13,T17
DebounceSt->IdleSt	163	Covered	T19,T7,T44
DetectSt->IdleSt	186	Covered	T37,T84,T86
DetectSt->StableSt	191	Covered	T6,T13,T17
IdleSt->DebounceSt	148	Covered	T6,T13,T17
StableSt->IdleSt	206	Covered	T6,T13,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T13,T17
0	1	Covered	T6,T13,T17
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T13,T17
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T13,T17
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T13,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T44,T109
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T13,T17
DetectSt	-	-	-	-	1	-	-	Covered	T37,T84,T86
DetectSt	-	-	-	-	0	1	-	Covered	T6,T13,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T13,T17
StableSt	-	-	-	-	-	-	0	Covered	T6,T13,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	274	0	0
CntIncr_A	5213315	145015	0	0
CntNoWrap_A	5213315	4539687	0	0
DetectStDropOut_A	5213315	5	0	0
DetectedOut_A	5213315	811	0	0
DetectedPulseOut_A	5213315	122	0	0
DisabledIdleSt_A	5213315	4388630	0	0
DisabledNoDetection_A	5213315	4390882	0	0
EnterDebounceSt_A	5213315	153	0	0
EnterDetectSt_A	5213315	127	0	0
EnterStableSt_A	5213315	122	0	0
PulseIsPulse_A	5213315	122	0	0
StayInStableSt	5213315	689	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	7141	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	122	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	274	0	0
T2	16218	0	0	0
T6	649	2	0	0
T7	0	3	0	0
T9	0	2	0	0
T10	0	4	0	0
T13	735	2	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	4	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T40	0	6	0	0
T42	0	4	0	0
T44	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	145015	0	0
T2	16218	0	0	0
T6	649	14	0	0
T7	0	66	0	0
T9	0	20	0	0
T10	0	45	0	0
T13	735	10	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	27	0	0
T18	557	0	0	0
T19	6345	10	0	0
T24	492	0	0	0
T40	0	156	0	0
T42	0	96	0	0
T44	0	137	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539687	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	246	0	0
T13	735	332	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	365	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	5	0	0
T37	39018	1	0	0
T84	0	2	0	0
T86	0	1	0	0
T92	0	1	0	0
T93	416	0	0	0
T94	525	0	0	0
T95	3186	0	0	0
T96	5166	0	0	0
T97	745	0	0	0
T98	411	0	0	0
T99	448	0	0	0
T100	442	0	0	0
T101	302189	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	811	0	0
T2	16218	0	0	0
T6	649	5	0	0
T7	0	9	0	0
T9	0	9	0	0
T10	0	5	0	0
T13	735	2	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	14	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T40	0	21	0	0
T42	0	9	0	0
T44	0	21	0	0
T109	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	122	0	0
T2	16218	0	0	0
T6	649	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	1	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	2	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T44	0	3	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4388630	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	187	0	0
T13	735	281	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	248	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4390882	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	188	0	0
T13	735	282	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	250	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	153	0	0
T2	16218	0	0	0
T6	649	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	1	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	2	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T44	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	127	0	0
T2	16218	0	0	0
T6	649	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	1	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	2	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T44	0	3	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	122	0	0
T2	16218	0	0	0
T6	649	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	1	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	2	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T44	0	3	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	122	0	0
T2	16218	0	0	0
T6	649	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	1	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	2	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T44	0	3	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	689	0	0
T2	16218	0	0	0
T6	649	4	0	0
T7	0	8	0	0
T9	0	8	0	0
T10	0	3	0	0
T13	735	1	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	12	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T40	0	18	0	0
T42	0	7	0	0
T44	0	18	0	0
T112	0	16	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	7141	0	0
T1	1309	9	0	0
T2	16218	35	0	0
T5	421	3	0	0
T6	649	3	0	0
T13	735	3	0	0
T14	429	2	0	0
T15	521	5	0	0
T16	539	5	0	0
T17	1571	7	0	0
T18	557	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	122	0	0
T2	16218	0	0	0
T6	649	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	1	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	2	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T40	0	3	0	0
T42	0	2	0	0
T44	0	3	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T19,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T19,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T8,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T8
1	0	Covered	T5,T1,T6
1	1	Covered	T1,T19,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T12
0	1	Covered	T77,T78,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T12
0	1	Unreachable
1	0	Covered	T1,T8,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T8
DetectSt	168	Covered	T1,T8,T12
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T8,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T12
DebounceSt->IdleSt	163	Covered	T19,T32,T117
DetectSt->IdleSt	186	Covered	T77,T78,T79
DetectSt->StableSt	191	Covered	T1,T8,T12
IdleSt->DebounceSt	148	Covered	T1,T19,T8
StableSt->IdleSt	206	Covered	T1,T8,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T19,T8
0	1	Covered	T1,T19,T8
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T12
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T117,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T8
DetectSt	-	-	-	-	1	-	-	Covered	T77,T78,T79
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	141	0	0
CntIncr_A	5213315	4545	0	0
CntNoWrap_A	5213315	4539820	0	0
DetectStDropOut_A	5213315	10	0	0
DetectedOut_A	5213315	10559	0	0
DetectedPulseOut_A	5213315	49	0	0
DisabledIdleSt_A	5213315	4480710	0	0
DisabledNoDetection_A	5213315	4483009	0	0
EnterDebounceSt_A	5213315	82	0	0
EnterDetectSt_A	5213315	59	0	0
EnterStableSt_A	5213315	49	0	0
PulseIsPulse_A	5213315	49	0	0
StayInStableSt	5213315	10510	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	7141	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_sticky_sva.StableStDropOut_A	5213315	40629	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	141	0	0
T1	1309	4	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	2	0	0
T12	0	2	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	2	0	0
T37	0	2	0	0
T54	0	2	0	0
T57	0	6	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4545	0	0
T1	1309	38	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	25	0	0
T12	0	51	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	67	0	0
T37	0	66	0	0
T54	0	92	0	0
T57	0	60	0	0
T65	0	95	0	0
T66	0	84	0	0
T67	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539820	0	0
T1	1309	904	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	10	0	0
T76	0	1	0	0
T77	1366	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T86	642	0	0	0
T120	0	1	0	0
T121	0	4	0	0
T122	5368	0	0	0
T123	839	0	0	0
T124	6586	0	0	0
T125	402	0	0	0
T126	2535	0	0	0
T127	712	0	0	0
T128	711	0	0	0
T129	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	10559	0	0
T1	1309	82	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	75	0	0
T12	0	130	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T37	0	71	0	0
T54	0	604	0	0
T57	0	83	0	0
T65	0	431	0	0
T66	0	567	0	0
T67	0	156	0	0
T115	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	49	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T37	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4480710	0	0
T1	1309	420	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4483009	0	0
T1	1309	421	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	82	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	2	0	0
T37	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	59	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T37	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T115	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	49	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T37	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	49	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T37	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	10510	0	0
T1	1309	80	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	74	0	0
T12	0	129	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T37	0	70	0	0
T54	0	603	0	0
T57	0	80	0	0
T65	0	430	0	0
T66	0	566	0	0
T67	0	155	0	0
T115	0	35	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	7141	0	0
T1	1309	9	0	0
T2	16218	35	0	0
T5	421	3	0	0
T6	649	3	0	0
T13	735	3	0	0
T14	429	2	0	0
T15	521	5	0	0
T16	539	5	0	0
T17	1571	7	0	0
T18	557	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	40629	0	0
T1	1309	318	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	270	0	0
T12	0	100	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T37	0	203	0	0
T54	0	72	0	0
T57	0	792	0	0
T65	0	51	0	0
T66	0	69	0	0
T67	0	68	0	0
T115	0	138	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T14
1	1	Covered	T5,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T19,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T19,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T12,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T8
1	0	Covered	T5,T1,T14
1	1	Covered	T1,T19,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T54
0	1	Covered	T37,T66,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T54
0	1	Unreachable
1	0	Covered	T1,T12,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T8
DetectSt	168	Covered	T1,T12,T54
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T12,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T54
DebounceSt->IdleSt	163	Covered	T19,T8,T37
DetectSt->IdleSt	186	Covered	T37,T66,T76
DetectSt->StableSt	191	Covered	T1,T12,T54
IdleSt->DebounceSt	148	Covered	T1,T19,T8
StableSt->IdleSt	206	Covered	T1,T12,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T19,T8
0	1	Covered	T1,T19,T8
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T54
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T37,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T8
DetectSt	-	-	-	-	1	-	-	Covered	T37,T66,T76
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T54
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	148	0	0
CntIncr_A	5213315	4311	0	0
CntNoWrap_A	5213315	4539813	0	0
DetectStDropOut_A	5213315	9	0	0
DetectedOut_A	5213315	8749	0	0
DetectedPulseOut_A	5213315	51	0	0
DisabledIdleSt_A	5213315	4480710	0	0
DisabledNoDetection_A	5213315	4483009	0	0
EnterDebounceSt_A	5213315	88	0	0
EnterDetectSt_A	5213315	60	0	0
EnterStableSt_A	5213315	51	0	0
PulseIsPulse_A	5213315	51	0	0
StayInStableSt	5213315	8698	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_sticky_sva.StableStDropOut_A	5213315	41556	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	148	0	0
T1	1309	4	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	2	0	0
T12	0	2	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	2	0	0
T37	0	3	0	0
T54	0	2	0	0
T57	0	6	0	0
T65	0	2	0	0
T66	0	6	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4311	0	0
T1	1309	98	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	120	0	0
T12	0	34	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	67	0	0
T37	0	176	0	0
T54	0	25	0	0
T57	0	255	0	0
T65	0	57	0	0
T66	0	120	0	0
T67	0	18	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539813	0	0
T1	1309	904	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	9	0	0
T37	39018	1	0	0
T66	0	2	0	0
T76	0	2	0	0
T93	416	0	0	0
T94	525	0	0	0
T95	3186	0	0	0
T96	5166	0	0	0
T97	745	0	0	0
T98	411	0	0	0
T99	448	0	0	0
T100	442	0	0	0
T101	302189	0	0	0
T130	0	2	0	0
T131	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	8749	0	0
T1	1309	223	0	0
T2	16218	0	0	0
T6	649	0	0	0
T12	0	104	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T32	0	37	0	0
T54	0	164	0	0
T57	0	554	0	0
T65	0	284	0	0
T66	0	41	0	0
T67	0	82	0	0
T73	0	361	0	0
T115	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	51	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T32	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4480710	0	0
T1	1309	420	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4483009	0	0
T1	1309	421	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	88	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	2	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	2	0	0
T37	0	2	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	3	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	60	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T32	0	1	0	0
T37	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	3	0	0
T67	0	1	0	0
T115	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	51	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T32	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	51	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T32	0	1	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	8698	0	0
T1	1309	221	0	0
T2	16218	0	0	0
T6	649	0	0	0
T12	0	103	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T32	0	36	0	0
T54	0	163	0	0
T57	0	551	0	0
T65	0	283	0	0
T66	0	40	0	0
T67	0	81	0	0
T73	0	360	0	0
T115	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	41556	0	0
T1	1309	142	0	0
T2	16218	0	0	0
T6	649	0	0	0
T12	0	151	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T32	0	71	0	0
T54	0	582	0	0
T57	0	148	0	0
T65	0	236	0	0
T66	0	272	0	0
T67	0	170	0	0
T73	0	253	0	0
T115	0	70	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T19,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T19,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T8,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T8
1	0	Covered	T5,T1,T2
1	1	Covered	T1,T19,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T54
0	1	Covered	T65,T73,T74
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T54
0	1	Unreachable
1	0	Covered	T1,T8,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T8
DetectSt	168	Covered	T1,T8,T54
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T8,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T54
DebounceSt->IdleSt	163	Covered	T19,T12,T37
DetectSt->IdleSt	186	Covered	T65,T73,T74
DetectSt->StableSt	191	Covered	T1,T8,T54
IdleSt->DebounceSt	148	Covered	T1,T19,T8
StableSt->IdleSt	206	Covered	T1,T8,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T19,T8
0	1	Covered	T1,T19,T8
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T54
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T37,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T8
DetectSt	-	-	-	-	1	-	-	Covered	T65,T73,T74
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T54
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	149	0	0
CntIncr_A	5213315	11683	0	0
CntNoWrap_A	5213315	4539812	0	0
DetectStDropOut_A	5213315	7	0	0
DetectedOut_A	5213315	35288	0	0
DetectedPulseOut_A	5213315	48	0	0
DisabledIdleSt_A	5213315	4480710	0	0
DisabledNoDetection_A	5213315	4483009	0	0
EnterDebounceSt_A	5213315	94	0	0
EnterDetectSt_A	5213315	55	0	0
EnterStableSt_A	5213315	48	0	0
PulseIsPulse_A	5213315	48	0	0
StayInStableSt	5213315	35240	0	0
gen_high_event_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_sticky_sva.StableStDropOut_A	5213315	8188	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	149	0	0
T1	1309	4	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	2	0	0
T37	0	2	0	0
T54	0	2	0	0
T57	0	6	0	0
T65	0	6	0	0
T66	0	2	0	0
T67	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	11683	0	0
T1	1309	120	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	82	0	0
T12	0	102	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	65	0	0
T37	0	112	0	0
T54	0	84	0	0
T57	0	255	0	0
T65	0	234	0	0
T66	0	82	0	0
T67	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539812	0	0
T1	1309	904	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	7	0	0
T37	39018	0	0	0
T65	1025	3	0	0
T73	0	1	0	0
T74	0	2	0	0
T81	11299	0	0	0
T110	7803	0	0	0
T112	700	0	0	0
T132	0	1	0	0
T133	3058	0	0	0
T134	407	0	0	0
T135	504	0	0	0
T136	806	0	0	0
T137	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	35288	0	0
T1	1309	262	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	176	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T54	0	435	0	0
T57	0	381	0	0
T66	0	439	0	0
T67	0	76	0	0
T73	0	41	0	0
T116	0	26926	0	0
T117	0	207	0	0
T118	0	164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	48	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T54	0	1	0	0
T57	0	3	0	0
T66	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4480710	0	0
T1	1309	420	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4483009	0	0
T1	1309	421	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	94	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T12	0	3	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	2	0	0
T37	0	2	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	3	0	0
T66	0	1	0	0
T67	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	55	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T54	0	1	0	0
T57	0	3	0	0
T65	0	3	0	0
T66	0	1	0	0
T67	0	1	0	0
T73	0	2	0	0
T116	0	2	0	0
T117	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	48	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T54	0	1	0	0
T57	0	3	0	0
T66	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	48	0	0
T1	1309	2	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T54	0	1	0	0
T57	0	3	0	0
T66	0	1	0	0
T67	0	1	0	0
T73	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	35240	0	0
T1	1309	260	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	175	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T54	0	434	0	0
T57	0	378	0	0
T66	0	438	0	0
T67	0	75	0	0
T73	0	40	0	0
T116	0	26924	0	0
T117	0	206	0	0
T118	0	163	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	8188	0	0
T1	1309	93	0	0
T2	16218	0	0	0
T6	649	0	0	0
T8	0	128	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T54	0	263	0	0
T57	0	343	0	0
T66	0	210	0	0
T67	0	179	0	0
T73	0	477	0	0
T116	0	86	0	0
T117	0	61	0	0
T118	0	62	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T9
1	0	Covered	T5,T1,T6
1	1	Covered	T19,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T11
0	1	Covered	T75,T138,T139
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T11
0	1	Covered	T9,T10,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T11
1	-	Covered	T9,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T9,T10
DetectSt	168	Covered	T9,T10,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T11
DebounceSt->IdleSt	163	Covered	T19,T75,T68
DetectSt->IdleSt	186	Covered	T75,T138,T139
DetectSt->StableSt	191	Covered	T9,T10,T11
IdleSt->DebounceSt	148	Covered	T19,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T9,T10
0	1	Covered	T19,T9,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T75
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T75,T138,T139
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	95	0	0
CntIncr_A	5213315	41898	0	0
CntNoWrap_A	5213315	4539866	0	0
DetectStDropOut_A	5213315	3	0	0
DetectedOut_A	5213315	3035	0	0
DetectedPulseOut_A	5213315	43	0	0
DisabledIdleSt_A	5213315	4203821	0	0
DisabledNoDetection_A	5213315	4206068	0	0
EnterDebounceSt_A	5213315	49	0	0
EnterDetectSt_A	5213315	46	0	0
EnterStableSt_A	5213315	43	0	0
PulseIsPulse_A	5213315	43	0	0
StayInStableSt	5213315	2969	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	95	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	4	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	2	0	0
T37	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	3	0	0
T83	0	4	0	0
T140	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	41898	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	182	0	0
T10	0	17	0	0
T11	0	50	0	0
T12	0	138	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	79	0	0
T37	0	92	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	44	0	0
T83	0	134	0	0
T140	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539866	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	3	0	0
T75	682	1	0	0
T117	2164	0	0	0
T118	1161	0	0	0
T138	0	1	0	0
T139	0	1	0	0
T141	402	0	0	0
T142	714	0	0	0
T143	845	0	0	0
T144	5566	0	0	0
T145	52823	0	0	0
T146	502	0	0	0
T147	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	3035	0	0
T9	32593	311	0	0
T10	23280	80	0	0
T11	586	50	0	0
T12	0	83	0	0
T25	1472	0	0	0
T35	0	137	0	0
T37	0	104	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	120	0	0
T140	0	13	0	0
T143	0	42	0	0
T145	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	43	0	0
T9	32593	2	0	0
T10	23280	1	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	2	0	0
T140	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4203821	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4206068	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	49	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	2	0	0
T83	0	2	0	0
T140	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	46	0	0
T9	32593	2	0	0
T10	23280	1	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T75	0	1	0	0
T83	0	2	0	0
T140	0	2	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	43	0	0
T9	32593	2	0	0
T10	23280	1	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	2	0	0
T140	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	43	0	0
T9	32593	2	0	0
T10	23280	1	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T35	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	2	0	0
T140	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2969	0	0
T9	32593	308	0	0
T10	23280	79	0	0
T11	586	48	0	0
T12	0	80	0	0
T25	1472	0	0	0
T35	0	136	0	0
T37	0	101	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	117	0	0
T140	0	11	0	0
T143	0	40	0	0
T145	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	20	0	0
T9	32593	1	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	0	1	0	0
T25	1472	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	1	0	0
T140	0	2	0	0
T145	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T9,T10
1	0	Covered	T5,T2,T14
1	1	Covered	T19,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T9,T150
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T12
1	-	Covered	T10,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T9,T10
DetectSt	168	Covered	T9,T10,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T11
DebounceSt->IdleSt	163	Covered	T19,T9,T151
DetectSt->IdleSt	186	Covered	T9,T150
DetectSt->StableSt	191	Covered	T10,T11,T12
IdleSt->DebounceSt	148	Covered	T19,T9,T10
StableSt->IdleSt	206	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T9,T10
0	1	Covered	T19,T9,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T151,T152
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T9,T150
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	122	0	0
CntIncr_A	5213315	3719	0	0
CntNoWrap_A	5213315	4539839	0	0
DetectStDropOut_A	5213315	2	0	0
DetectedOut_A	5213315	5044	0	0
DetectedPulseOut_A	5213315	54	0	0
DisabledIdleSt_A	5213315	4514598	0	0
DisabledNoDetection_A	5213315	4516846	0	0
EnterDebounceSt_A	5213315	66	0	0
EnterDetectSt_A	5213315	56	0	0
EnterStableSt_A	5213315	54	0	0
PulseIsPulse_A	5213315	54	0	0
StayInStableSt	5213315	4972	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	2846	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	122	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	3	0	0
T10	0	8	0	0
T11	0	2	0	0
T12	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	4	0	0
T83	0	4	0	0
T151	0	3	0	0
T152	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	3719	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	182	0	0
T10	0	197	0	0
T11	0	50	0	0
T12	0	138	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T37	0	41	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	200	0	0
T83	0	134	0	0
T151	0	156	0	0
T152	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539839	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T25	1472	0	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T150	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	5044	0	0
T10	23280	347	0	0
T11	586	26	0	0
T12	8077	177	0	0
T37	0	110	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	204	0	0
T83	0	174	0	0
T142	0	122	0	0
T143	0	120	0	0
T151	0	217	0	0
T152	0	94	0	0
T153	526	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T10	23280	4	0	0
T11	586	1	0	0
T12	8077	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T142	0	2	0	0
T143	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	526	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4514598	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4516846	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	66	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	2	0	0
T10	0	4	0	0
T11	0	1	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T37	0	1	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T151	0	2	0	0
T152	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	56	0	0
T9	32593	1	0	0
T10	23280	4	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T142	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T10	23280	4	0	0
T11	586	1	0	0
T12	8077	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T142	0	2	0	0
T143	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	526	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T10	23280	4	0	0
T11	586	1	0	0
T12	8077	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T142	0	2	0	0
T143	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	526	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4972	0	0
T10	23280	342	0	0
T11	586	25	0	0
T12	8077	175	0	0
T37	0	108	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	201	0	0
T83	0	172	0	0
T142	0	119	0	0
T143	0	119	0	0
T151	0	216	0	0
T152	0	91	0	0
T153	526	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2846	0	0
T1	1309	0	0	0
T2	16218	0	0	0
T4	0	1	0	0
T5	421	2	0	0
T6	649	0	0	0
T13	735	0	0	0
T14	429	3	0	0
T15	521	6	0	0
T16	539	6	0	0
T17	1571	4	0	0
T18	557	0	0	0
T19	0	3	0	0
T24	0	3	0	0
T47	0	4	0	0
T48	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	36	0	0
T10	23280	3	0	0
T11	586	1	0	0
T12	8077	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	1	0	0
T83	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	526	0	0	0