Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T12,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T9,T10
1	0	Covered	T5,T1,T6
1	1	Covered	T19,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T35
0	1	Covered	T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T35
0	1	Covered	T12,T35,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T35
1	-	Covered	T12,T35,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T9,T12
DetectSt	168	Covered	T9,T12,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T12,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T35
DebounceSt->IdleSt	163	Covered	T19,T148,T68
DetectSt->IdleSt	186	Covered	T154
DetectSt->StableSt	191	Covered	T9,T12,T35
IdleSt->DebounceSt	148	Covered	T19,T9,T12
StableSt->IdleSt	206	Covered	T9,T12,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T9,T12
0	1	Covered	T19,T9,T12
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T154
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T35,T37
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	78	0	0
CntIncr_A	5213315	2175	0	0
CntNoWrap_A	5213315	4539883	0	0
DetectStDropOut_A	5213315	1	0	0
DetectedOut_A	5213315	2485	0	0
DetectedPulseOut_A	5213315	36	0	0
DisabledIdleSt_A	5213315	4522651	0	0
DisabledNoDetection_A	5213315	4524901	0	0
EnterDebounceSt_A	5213315	41	0	0
EnterDetectSt_A	5213315	37	0	0
EnterStableSt_A	5213315	36	0	0
PulseIsPulse_A	5213315	36	0	0
StayInStableSt	5213315	2432	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	78	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	2	0	0
T12	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	2	0	0
T35	0	4	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T83	0	2	0	0
T142	0	2	0	0
T151	0	4	0	0
T156	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2175	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	91	0	0
T12	0	138	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	23	0	0
T35	0	158	0	0
T37	0	46	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T83	0	67	0	0
T142	0	46	0	0
T151	0	156	0	0
T156	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539883	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1	0	0
T154	763	1	0	0
T157	680	0	0	0
T158	5046	0	0	0
T159	24060	0	0	0
T160	6456	0	0	0
T161	725	0	0	0
T162	436	0	0	0
T163	643	0	0	0
T164	11138	0	0	0
T165	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2485	0	0
T9	32593	134	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	155	0	0
T25	1472	0	0	0
T32	0	43	0	0
T35	0	180	0	0
T37	0	40	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	40	0	0
T142	0	1	0	0
T151	0	85	0	0
T156	0	32	0	0
T166	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	36	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	2	0	0
T25	1472	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	1	0	0
T142	0	1	0	0
T151	0	2	0	0
T156	0	1	0	0
T166	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4522651	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4524901	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	41	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	1	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T83	0	1	0	0
T142	0	1	0	0
T151	0	2	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	37	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	2	0	0
T25	1472	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	1	0	0
T142	0	1	0	0
T151	0	2	0	0
T156	0	1	0	0
T166	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	36	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	2	0	0
T25	1472	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	1	0	0
T142	0	1	0	0
T151	0	2	0	0
T156	0	1	0	0
T166	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	36	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	2	0	0
T25	1472	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	1	0	0
T142	0	1	0	0
T151	0	2	0	0
T156	0	1	0	0
T166	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2432	0	0
T9	32593	132	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	152	0	0
T25	1472	0	0	0
T32	0	42	0	0
T35	0	177	0	0
T37	0	39	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	39	0	0
T151	0	82	0	0
T156	0	31	0	0
T166	0	79	0	0
T167	0	47	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	19	0	0
T12	8077	1	0	0
T30	11653	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T61	491	0	0	0
T83	0	1	0	0
T142	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T169	421	0	0	0
T170	524	0	0	0
T171	434	0	0	0
T172	422	0	0	0
T173	507	0	0	0
T174	502	0	0	0
T175	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T12,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T10,T12
1	0	Covered	T5,T2,T14
1	1	Covered	T19,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T36
0	1	Covered	T36,T176
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T36
0	1	Covered	T12,T36,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T36
1	-	Covered	T12,T36,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T10,T12
DetectSt	168	Covered	T10,T12,T36
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T12,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T36
DebounceSt->IdleSt	163	Covered	T19,T151,T177
DetectSt->IdleSt	186	Covered	T36,T176
DetectSt->StableSt	191	Covered	T10,T12,T36
IdleSt->DebounceSt	148	Covered	T19,T10,T12
StableSt->IdleSt	206	Covered	T10,T12,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T10,T12
0	1	Covered	T19,T10,T12
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T36
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T10,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T177,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T10,T12
DetectSt	-	-	-	-	1	-	-	Covered	T36,T176
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T36,T37
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	107	0	0
CntIncr_A	5213315	145128	0	0
CntNoWrap_A	5213315	4539854	0	0
DetectStDropOut_A	5213315	2	0	0
DetectedOut_A	5213315	78214	0	0
DetectedPulseOut_A	5213315	49	0	0
DisabledIdleSt_A	5213315	4167209	0	0
DisabledNoDetection_A	5213315	4169462	0	0
EnterDebounceSt_A	5213315	56	0	0
EnterDetectSt_A	5213315	51	0	0
EnterStableSt_A	5213315	49	0	0
PulseIsPulse_A	5213315	49	0	0
StayInStableSt	5213315	78141	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	3217	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	107	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	2	0	0
T12	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	2	0	0
T75	0	4	0	0
T143	0	2	0	0
T151	0	3	0	0
T152	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	145128	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	39	0	0
T12	0	138	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	21708	0	0
T37	0	92	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	99	0	0
T75	0	44	0	0
T143	0	75	0	0
T151	0	156	0	0
T152	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539854	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2	0	0
T35	1069	0	0	0
T36	46698	1	0	0
T65	1025	0	0	0
T110	7803	0	0	0
T112	700	0	0	0
T133	3058	0	0	0
T134	407	0	0	0
T176	0	1	0	0
T178	584	0	0	0
T179	414	0	0	0
T180	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	78214	0	0
T10	23280	42	0	0
T11	586	0	0	0
T12	8077	224	0	0
T36	0	2791	0	0
T37	0	156	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	57	0	0
T75	0	53	0	0
T143	0	40	0	0
T145	0	199	0	0
T151	0	216	0	0
T152	0	94	0	0
T153	526	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	49	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	526	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4167209	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4169462	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	56	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	1	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T143	0	1	0	0
T151	0	2	0	0
T152	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	51	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	526	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	49	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	526	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	49	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	526	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	78141	0	0
T10	23280	40	0	0
T11	586	0	0	0
T12	8077	222	0	0
T36	0	2790	0	0
T37	0	153	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	56	0	0
T75	0	50	0	0
T143	0	39	0	0
T145	0	196	0	0
T151	0	215	0	0
T152	0	92	0	0
T153	526	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	3217	0	0
T1	1309	0	0	0
T2	16218	0	0	0
T5	421	2	0	0
T6	649	0	0	0
T13	735	0	0	0
T14	429	4	0	0
T15	521	5	0	0
T16	539	4	0	0
T17	1571	8	0	0
T18	557	0	0	0
T19	0	7	0	0
T24	0	4	0	0
T29	0	3	0	0
T47	0	6	0	0
T48	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	25	0	0
T12	8077	2	0	0
T30	11653	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T61	491	0	0	0
T64	0	1	0	0
T75	0	1	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0
T167	0	1	0	0
T169	421	0	0	0
T170	524	0	0	0
T171	434	0	0	0
T172	422	0	0	0
T173	507	0	0	0
T174	502	0	0	0
T175	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T10,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T9,T10
1	0	Covered	T5,T1,T2
1	1	Covered	T19,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T35
0	1	Covered	T9,T75,T181
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T35
0	1	Covered	T10,T35,T64
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T35
1	-	Covered	T10,T35,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T9,T10
DetectSt	168	Covered	T9,T10,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T10,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T35
DebounceSt->IdleSt	163	Covered	T19,T9,T182
DetectSt->IdleSt	186	Covered	T9,T75,T181
DetectSt->StableSt	191	Covered	T9,T10,T35
IdleSt->DebounceSt	148	Covered	T19,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T9,T10
0	1	Covered	T19,T9,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T182,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T9,T75,T181
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T35,T64
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	123	0	0
CntIncr_A	5213315	122558	0	0
CntNoWrap_A	5213315	4539838	0	0
DetectStDropOut_A	5213315	3	0	0
DetectedOut_A	5213315	23723	0	0
DetectedPulseOut_A	5213315	54	0	0
DisabledIdleSt_A	5213315	4206682	0	0
DisabledNoDetection_A	5213315	4208933	0	0
EnterDebounceSt_A	5213315	66	0	0
EnterDetectSt_A	5213315	57	0	0
EnterStableSt_A	5213315	54	0	0
PulseIsPulse_A	5213315	54	0	0
StayInStableSt	5213315	23646	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	123	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	5	0	0
T10	0	6	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	2	0	0
T35	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	2	0	0
T75	0	6	0	0
T83	0	2	0	0
T140	0	4	0	0
T182	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	122558	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	273	0	0
T10	0	129	0	0
T19	6345	16	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	23	0	0
T35	0	158	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	99	0	0
T75	0	66	0	0
T83	0	67	0	0
T140	0	78	0	0
T182	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539838	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	3	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T25	1472	0	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T75	0	1	0	0
T181	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	23723	0	0
T9	32593	42	0	0
T10	23280	438	0	0
T11	586	0	0	0
T25	1472	0	0	0
T32	0	68	0	0
T35	0	157	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	56	0	0
T75	0	75	0	0
T83	0	267	0	0
T140	0	81	0	0
T145	0	99	0	0
T156	0	151	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T9	32593	1	0	0
T10	23280	3	0	0
T11	586	0	0	0
T25	1472	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T83	0	1	0	0
T140	0	2	0	0
T145	0	1	0	0
T156	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4206682	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4208933	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	66	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	3	0	0
T10	0	3	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	1	0	0
T75	0	3	0	0
T83	0	1	0	0
T140	0	2	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	57	0	0
T9	32593	2	0	0
T10	23280	3	0	0
T11	586	0	0	0
T25	1472	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	3	0	0
T83	0	1	0	0
T140	0	2	0	0
T145	0	1	0	0
T156	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T9	32593	1	0	0
T10	23280	3	0	0
T11	586	0	0	0
T25	1472	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T83	0	1	0	0
T140	0	2	0	0
T145	0	1	0	0
T156	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T9	32593	1	0	0
T10	23280	3	0	0
T11	586	0	0	0
T25	1472	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	2	0	0
T83	0	1	0	0
T140	0	2	0	0
T145	0	1	0	0
T156	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	23646	0	0
T9	32593	40	0	0
T10	23280	433	0	0
T11	586	0	0	0
T25	1472	0	0	0
T32	0	67	0	0
T35	0	155	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	55	0	0
T75	0	72	0	0
T83	0	265	0	0
T140	0	78	0	0
T145	0	98	0	0
T156	0	147	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	31	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T75	0	1	0	0
T87	0	1	0	0
T140	0	1	0	0
T145	0	1	0	0
T153	526	0	0	0
T156	0	2	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T9
1	0	Covered	T5,T1,T2
1	1	Covered	T19,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T12
0	1	Covered	T9,T12,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T12
1	-	Covered	T9,T12,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T9,T10
DetectSt	168	Covered	T9,T10,T12
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T12
DebounceSt->IdleSt	163	Covered	T19,T148,T184
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T10,T12
IdleSt->DebounceSt	148	Covered	T19,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T9,T10
0	1	Covered	T19,T9,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T12
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T9,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T35
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	68	0	0
CntIncr_A	5213315	120973	0	0
CntNoWrap_A	5213315	4539893	0	0
DetectStDropOut_A	5213315	0	0	0
DetectedOut_A	5213315	2903	0	0
DetectedPulseOut_A	5213315	32	0	0
DisabledIdleSt_A	5213315	4174101	0	0
DisabledNoDetection_A	5213315	4176355	0	0
EnterDebounceSt_A	5213315	36	0	0
EnterDetectSt_A	5213315	32	0	0
EnterStableSt_A	5213315	32	0	0
PulseIsPulse_A	5213315	32	0	0
StayInStableSt	5213315	2855	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	6824	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	68	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	4	0	0
T10	0	4	0	0
T12	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	4	0	0
T37	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	2	0	0
T142	0	2	0	0
T145	0	2	0	0
T156	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	120973	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	182	0	0
T10	0	107	0	0
T12	0	138	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	158	0	0
T37	0	87	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	99	0	0
T142	0	46	0	0
T145	0	60	0	0
T156	0	172	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539893	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2903	0	0
T9	32593	177	0	0
T10	23280	90	0	0
T11	586	0	0	0
T12	0	155	0	0
T25	1472	0	0	0
T35	0	78	0	0
T37	0	319	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	43	0	0
T142	0	186	0	0
T145	0	46	0	0
T156	0	204	0	0
T183	0	367	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	32	0	0
T9	32593	2	0	0
T10	23280	2	0	0
T11	586	0	0	0
T12	0	2	0	0
T25	1472	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T156	0	2	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4174101	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4176355	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	36	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T156	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	32	0	0
T9	32593	2	0	0
T10	23280	2	0	0
T11	586	0	0	0
T12	0	2	0	0
T25	1472	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T156	0	2	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	32	0	0
T9	32593	2	0	0
T10	23280	2	0	0
T11	586	0	0	0
T12	0	2	0	0
T25	1472	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T156	0	2	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	32	0	0
T9	32593	2	0	0
T10	23280	2	0	0
T11	586	0	0	0
T12	0	2	0	0
T25	1472	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T156	0	2	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2855	0	0
T9	32593	175	0	0
T10	23280	86	0	0
T11	586	0	0	0
T12	0	152	0	0
T25	1472	0	0	0
T35	0	75	0	0
T37	0	316	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	41	0	0
T142	0	184	0	0
T145	0	44	0	0
T156	0	202	0	0
T183	0	365	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	6824	0	0
T1	1309	9	0	0
T2	16218	27	0	0
T5	421	1	0	0
T6	649	0	0	0
T13	735	0	0	0
T14	429	5	0	0
T15	521	5	0	0
T16	539	4	0	0
T17	1571	5	0	0
T18	557	2	0	0
T19	0	32	0	0
T24	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	16	0	0
T9	32593	2	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	1	0	0
T25	1472	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T87	0	1	0	0
T149	0	1	0	0
T156	0	2	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T2,T14
1	1	Covered	T5,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T10,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T10,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T35,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T10,T35
1	0	Covered	T5,T2,T14
1	1	Covered	T19,T10,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T37
0	1	Covered	T32,T148
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T37
0	1	Covered	T35,T37,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T35,T37
1	-	Covered	T35,T37,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T10,T35
DetectSt	168	Covered	T10,T35,T37
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T35,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T35,T37
DebounceSt->IdleSt	163	Covered	T19,T151,T182
DetectSt->IdleSt	186	Covered	T32,T148
DetectSt->StableSt	191	Covered	T10,T35,T37
IdleSt->DebounceSt	148	Covered	T19,T10,T35
StableSt->IdleSt	206	Covered	T10,T35,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T10,T35
0	1	Covered	T19,T10,T35
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T35,T37
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T10,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T2,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T35,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T182,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T10,T35
DetectSt	-	-	-	-	1	-	-	Covered	T32,T148
DetectSt	-	-	-	-	0	1	-	Covered	T10,T35,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T37,T151
StableSt	-	-	-	-	-	-	0	Covered	T10,T35,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	118	0	0
CntIncr_A	5213315	179836	0	0
CntNoWrap_A	5213315	4539843	0	0
DetectStDropOut_A	5213315	2	0	0
DetectedOut_A	5213315	112050	0	0
DetectedPulseOut_A	5213315	54	0	0
DisabledIdleSt_A	5213315	4175054	0	0
DisabledNoDetection_A	5213315	4177307	0	0
EnterDebounceSt_A	5213315	62	0	0
EnterDetectSt_A	5213315	56	0	0
EnterStableSt_A	5213315	54	0	0
PulseIsPulse_A	5213315	54	0	0
StayInStableSt	5213315	111973	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	118	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	2	0	0
T35	0	2	0	0
T37	0	10	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T142	0	4	0	0
T151	0	3	0	0
T152	0	2	0	0
T182	0	1	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	179836	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	39	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	23	0	0
T35	0	79	0	0
T37	0	220	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T142	0	92	0	0
T151	0	156	0	0
T152	0	27	0	0
T182	0	84	0	0
T188	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539843	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2	0	0
T32	26822	1	0	0
T73	1140	0	0	0
T82	30065	0	0	0
T83	13887	0	0	0
T102	505	0	0	0
T103	715	0	0	0
T104	541	0	0	0
T105	28280	0	0	0
T106	502	0	0	0
T107	634	0	0	0
T148	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	112050	0	0
T10	23280	43	0	0
T11	586	0	0	0
T12	8077	0	0	0
T35	0	233	0	0
T37	0	241	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T142	0	122	0	0
T143	0	161	0	0
T145	0	211	0	0
T151	0	236	0	0
T152	0	158	0	0
T153	526	0	0	0
T156	0	241	0	0
T188	0	105	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	0	0	0
T35	0	1	0	0
T37	0	5	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	526	0	0	0
T156	0	2	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4175054	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4177307	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	62	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	1	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	5	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T142	0	2	0	0
T151	0	2	0	0
T152	0	1	0	0
T182	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	56	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	0	0	0
T32	0	1	0	0
T35	0	1	0	0
T37	0	5	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	526	0	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	0	0	0
T35	0	1	0	0
T37	0	5	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	526	0	0	0
T156	0	2	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	0	0	0
T35	0	1	0	0
T37	0	5	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T142	0	2	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	526	0	0	0
T156	0	2	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	111973	0	0
T10	23280	41	0	0
T11	586	0	0	0
T12	8077	0	0	0
T35	0	232	0	0
T37	0	235	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T142	0	119	0	0
T143	0	160	0	0
T145	0	210	0	0
T151	0	235	0	0
T152	0	157	0	0
T153	526	0	0	0
T156	0	238	0	0
T188	0	103	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	31	0	0
T35	1069	1	0	0
T37	0	4	0	0
T65	1025	0	0	0
T81	11299	0	0	0
T110	7803	0	0	0
T112	700	0	0	0
T133	3058	0	0	0
T134	407	0	0	0
T135	504	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T179	414	0	0	0
T180	422	0	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T2,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T4,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T4,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T9,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T9
1	0	Covered	T5,T2,T14
1	1	Covered	T19,T4,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T37
0	1	Covered	T75
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T37
0	1	Covered	T9,T37,T83
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T9,T37
1	-	Covered	T9,T37,T83

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T4,T9
DetectSt	168	Covered	T4,T9,T37
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T9,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T37
DebounceSt->IdleSt	163	Covered	T19,T68
DetectSt->IdleSt	186	Covered	T75
DetectSt->StableSt	191	Covered	T4,T9,T37
IdleSt->DebounceSt	148	Covered	T19,T4,T9
StableSt->IdleSt	206	Covered	T9,T37,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T4,T9
0	1	Covered	T19,T4,T9
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T37
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T4,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T37
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T4,T9
DetectSt	-	-	-	-	1	-	-	Covered	T75
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T37,T83
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	86	0	0
CntIncr_A	5213315	2272	0	0
CntNoWrap_A	5213315	4539875	0	0
DetectStDropOut_A	5213315	1	0	0
DetectedOut_A	5213315	2433	0	0
DetectedPulseOut_A	5213315	41	0	0
DisabledIdleSt_A	5213315	4520808	0	0
DisabledNoDetection_A	5213315	4523049	0	0
EnterDebounceSt_A	5213315	44	0	0
EnterDetectSt_A	5213315	42	0	0
EnterStableSt_A	5213315	41	0	0
PulseIsPulse_A	5213315	41	0	0
StayInStableSt	5213315	2368	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	6433	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	86	0	0
T3	19566	0	0	0
T4	500	2	0	0
T9	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	2	0	0
T37	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	4	0	0
T83	0	2	0	0
T140	0	2	0	0
T151	0	4	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2272	0	0
T3	19566	0	0	0
T4	500	18	0	0
T9	0	91	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	23	0	0
T37	0	82	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	44	0	0
T83	0	67	0	0
T140	0	39	0	0
T151	0	156	0	0
T152	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539875	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1	0	0
T75	682	1	0	0
T117	2164	0	0	0
T118	1161	0	0	0
T141	402	0	0	0
T142	714	0	0	0
T143	845	0	0	0
T144	5566	0	0	0
T145	52823	0	0	0
T146	502	0	0	0
T147	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2433	0	0
T4	500	45	0	0
T7	20808	0	0	0
T9	0	135	0	0
T26	18391	0	0	0
T32	0	41	0	0
T37	0	156	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T75	0	39	0	0
T83	0	124	0	0
T113	408	0	0	0
T140	0	92	0	0
T143	0	123	0	0
T151	0	84	0	0
T152	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	41	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	1	0	0
T26	18391	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T75	0	1	0	0
T83	0	1	0	0
T113	408	0	0	0
T140	0	1	0	0
T143	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4520808	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4523049	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	44	0	0
T3	19566	0	0	0
T4	500	1	0	0
T9	0	1	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	2	0	0
T83	0	1	0	0
T140	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	42	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	1	0	0
T26	18391	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T75	0	2	0	0
T83	0	1	0	0
T113	408	0	0	0
T140	0	1	0	0
T143	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	41	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	1	0	0
T26	18391	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T75	0	1	0	0
T83	0	1	0	0
T113	408	0	0	0
T140	0	1	0	0
T143	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	41	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	1	0	0
T26	18391	0	0	0
T32	0	1	0	0
T37	0	2	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T75	0	1	0	0
T83	0	1	0	0
T113	408	0	0	0
T140	0	1	0	0
T143	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2368	0	0
T4	500	43	0	0
T7	20808	0	0	0
T9	0	134	0	0
T26	18391	0	0	0
T32	0	39	0	0
T37	0	153	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T75	0	37	0	0
T83	0	123	0	0
T113	408	0	0	0
T140	0	91	0	0
T143	0	121	0	0
T151	0	81	0	0
T152	0	85	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	6433	0	0
T1	1309	0	0	0
T2	16218	25	0	0
T5	421	2	0	0
T6	649	0	0	0
T13	735	0	0	0
T14	429	5	0	0
T15	521	6	0	0
T16	539	4	0	0
T17	1571	3	0	0
T18	557	0	0	0
T19	0	37	0	0
T24	0	9	0	0
T47	0	4	0	0
T48	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	17	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T25	1472	0	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T83	0	1	0	0
T140	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T183	0	1	0	0
T187	0	1	0	0