Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T2,T14
1	1	Covered	T5,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T4,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T4,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T9
1	0	Covered	T5,T2,T14
1	1	Covered	T19,T4,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T10
0	1	Covered	T119,T190,T191
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T9,T10
0	1	Covered	T4,T9,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T9,T10
1	-	Covered	T4,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T4,T9
DetectSt	168	Covered	T4,T9,T10
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T9,T10
DebounceSt->IdleSt	163	Covered	T19,T139,T192
DetectSt->IdleSt	186	Covered	T119,T190,T191
DetectSt->StableSt	191	Covered	T4,T9,T10
IdleSt->DebounceSt	148	Covered	T19,T4,T9
StableSt->IdleSt	206	Covered	T4,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T4,T9
0	1	Covered	T19,T4,T9
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T4,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T2,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T139
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T4,T9
DetectSt	-	-	-	-	1	-	-	Covered	T119,T190,T191
DetectSt	-	-	-	-	0	1	-	Covered	T4,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T4,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	151	0	0
CntIncr_A	5213315	12371	0	0
CntNoWrap_A	5213315	4539810	0	0
DetectStDropOut_A	5213315	4	0	0
DetectedOut_A	5213315	5552	0	0
DetectedPulseOut_A	5213315	70	0	0
DisabledIdleSt_A	5213315	4513248	0	0
DisabledNoDetection_A	5213315	4515491	0	0
EnterDebounceSt_A	5213315	78	0	0
EnterDetectSt_A	5213315	74	0	0
EnterStableSt_A	5213315	70	0	0
PulseIsPulse_A	5213315	70	0	0
StayInStableSt	5213315	5456	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	151	0	0
T3	19566	0	0	0
T4	500	2	0	0
T9	0	4	0	0
T10	0	6	0	0
T12	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	2	0	0
T37	0	8	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	4	0	0
T83	0	4	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	12371	0	0
T3	19566	0	0	0
T4	500	18	0	0
T9	0	182	0	0
T10	0	229	0	0
T12	0	138	0	0
T19	6345	16	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	79	0	0
T37	0	174	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	200	0	0
T83	0	134	0	0
T182	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539810	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4	0	0
T119	13346	1	0	0
T139	0	1	0	0
T189	514	0	0	0
T190	0	1	0	0
T191	0	1	0	0
T193	454	0	0	0
T194	6035	0	0	0
T195	494	0	0	0
T196	3335	0	0	0
T197	38896	0	0	0
T198	648	0	0	0
T199	588	0	0	0
T200	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	5552	0	0
T4	500	10	0	0
T7	20808	0	0	0
T9	0	87	0	0
T10	0	130	0	0
T12	0	207	0	0
T26	18391	0	0	0
T35	0	351	0	0
T37	0	285	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	82	0	0
T75	0	52	0	0
T83	0	83	0	0
T113	408	0	0	0
T182	0	72	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	70	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	2	0	0
T26	18391	0	0	0
T35	0	1	0	0
T37	0	4	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	2	0	0
T75	0	2	0	0
T83	0	2	0	0
T113	408	0	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4513248	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4515491	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	78	0	0
T3	19566	0	0	0
T4	500	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	1	0	0
T37	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	2	0	0
T83	0	2	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	74	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	2	0	0
T26	18391	0	0	0
T35	0	1	0	0
T37	0	4	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	2	0	0
T75	0	2	0	0
T83	0	2	0	0
T113	408	0	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	70	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	2	0	0
T26	18391	0	0	0
T35	0	1	0	0
T37	0	4	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	2	0	0
T75	0	2	0	0
T83	0	2	0	0
T113	408	0	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	70	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	2	0	0
T10	0	3	0	0
T12	0	2	0	0
T26	18391	0	0	0
T35	0	1	0	0
T37	0	4	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	2	0	0
T75	0	2	0	0
T83	0	2	0	0
T113	408	0	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	5456	0	0
T4	500	9	0	0
T7	20808	0	0	0
T9	0	85	0	0
T10	0	125	0	0
T12	0	205	0	0
T26	18391	0	0	0
T35	0	349	0	0
T37	0	281	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	79	0	0
T75	0	49	0	0
T83	0	81	0	0
T113	408	0	0	0
T182	0	70	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	44	0	0
T4	500	1	0	0
T7	20808	0	0	0
T9	0	2	0	0
T10	0	1	0	0
T12	0	2	0	0
T26	18391	0	0	0
T37	0	4	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T83	0	2	0	0
T113	408	0	0	0
T142	0	1	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T2,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T9,T10
1	0	Covered	T5,T2,T14
1	1	Covered	T19,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T11
0	1	Covered	T9
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T11
0	1	Covered	T10,T12,T140
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T11
1	-	Covered	T10,T12,T140

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T9,T10
DetectSt	168	Covered	T9,T10,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T11
DebounceSt->IdleSt	163	Covered	T19,T68,T201
DetectSt->IdleSt	186	Covered	T9
DetectSt->StableSt	191	Covered	T9,T10,T11
IdleSt->DebounceSt	148	Covered	T19,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T9,T10
0	1	Covered	T19,T9,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T201
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T9
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T140
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	75	0	0
CntIncr_A	5213315	30531	0	0
CntNoWrap_A	5213315	4539886	0	0
DetectStDropOut_A	5213315	1	0	0
DetectedOut_A	5213315	1671	0	0
DetectedPulseOut_A	5213315	35	0	0
DisabledIdleSt_A	5213315	4439955	0	0
DisabledNoDetection_A	5213315	4442210	0	0
EnterDebounceSt_A	5213315	39	0	0
EnterDetectSt_A	5213315	36	0	0
EnterStableSt_A	5213315	35	0	0
PulseIsPulse_A	5213315	35	0	0
StayInStableSt	5213315	1619	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	6475	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	75	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	2	0	0
T12	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T119	0	2	0	0
T140	0	2	0	0
T143	0	2	0	0
T149	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	30531	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	182	0	0
T10	0	112	0	0
T11	0	50	0	0
T12	0	138	0	0
T19	6345	16	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	10854	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T119	0	54	0	0
T140	0	39	0	0
T143	0	75	0	0
T149	0	17536	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539886	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T25	1472	0	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1671	0	0
T9	32593	133	0	0
T10	23280	100	0	0
T11	586	50	0	0
T12	0	173	0	0
T25	1472	0	0	0
T36	0	38	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T119	0	38	0	0
T140	0	9	0	0
T143	0	41	0	0
T149	0	86	0	0
T190	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	35	0	0
T9	32593	1	0	0
T10	23280	2	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T36	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T119	0	1	0	0
T140	0	1	0	0
T143	0	1	0	0
T149	0	3	0	0
T190	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4439955	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4442210	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	39	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	1	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T119	0	1	0	0
T140	0	1	0	0
T143	0	1	0	0
T149	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	36	0	0
T9	32593	2	0	0
T10	23280	2	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T36	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T119	0	1	0	0
T140	0	1	0	0
T143	0	1	0	0
T149	0	3	0	0
T190	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	35	0	0
T9	32593	1	0	0
T10	23280	2	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T36	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T119	0	1	0	0
T140	0	1	0	0
T143	0	1	0	0
T149	0	3	0	0
T190	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	35	0	0
T9	32593	1	0	0
T10	23280	2	0	0
T11	586	1	0	0
T12	0	2	0	0
T25	1472	0	0	0
T36	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T119	0	1	0	0
T140	0	1	0	0
T143	0	1	0	0
T149	0	3	0	0
T190	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1619	0	0
T9	32593	131	0	0
T10	23280	98	0	0
T11	586	48	0	0
T12	0	170	0	0
T25	1472	0	0	0
T36	0	36	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T119	0	36	0	0
T140	0	8	0	0
T143	0	39	0	0
T149	0	82	0	0
T190	0	78	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	6475	0	0
T1	1309	0	0	0
T2	16218	26	0	0
T5	421	4	0	0
T6	649	0	0	0
T13	735	0	0	0
T14	429	2	0	0
T15	521	6	0	0
T16	539	4	0	0
T17	1571	6	0	0
T18	557	0	0	0
T19	0	27	0	0
T24	0	6	0	0
T47	0	4	0	0
T48	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	18	0	0
T10	23280	2	0	0
T11	586	0	0	0
T12	8077	1	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T149	0	2	0	0
T153	526	0	0	0
T186	0	1	0	0
T190	0	1	0	0
T202	0	2	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T2,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T2,T14
1	1	Covered	T5,T2,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T10,T11
1	0	Covered	T5,T2,T14
1	1	Covered	T19,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T191
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T12,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T12
1	-	Covered	T10,T12,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T10,T11
DetectSt	168	Covered	T10,T11,T12
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T12
DebounceSt->IdleSt	163	Covered	T19,T151,T148
DetectSt->IdleSt	186	Covered	T191
DetectSt->StableSt	191	Covered	T10,T11,T12
IdleSt->DebounceSt	148	Covered	T19,T10,T11
StableSt->IdleSt	206	Covered	T10,T12,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T10,T11
0	1	Covered	T19,T10,T11
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T2,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T148,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T191
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T12,T36
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	100	0	0
CntIncr_A	5213315	69346	0	0
CntNoWrap_A	5213315	4539861	0	0
DetectStDropOut_A	5213315	1	0	0
DetectedOut_A	5213315	62467	0	0
DetectedPulseOut_A	5213315	46	0	0
DisabledIdleSt_A	5213315	4255000	0	0
DisabledNoDetection_A	5213315	4257254	0	0
EnterDebounceSt_A	5213315	54	0	0
EnterDetectSt_A	5213315	47	0	0
EnterStableSt_A	5213315	46	0	0
PulseIsPulse_A	5213315	46	0	0
StayInStableSt	5213315	62404	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	100	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	2	0	0
T140	0	4	0	0
T151	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	69346	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	39	0	0
T11	0	50	0	0
T12	0	69	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	79	0	0
T36	0	10854	0	0
T37	0	82	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	100	0	0
T140	0	78	0	0
T151	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539861	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1	0	0
T79	1521	0	0	0
T186	3485	0	0	0
T191	601	1	0	0
T204	422	0	0	0
T205	8295	0	0	0
T206	406	0	0	0
T207	600	0	0	0
T208	2810	0	0	0
T209	429	0	0	0
T210	17746	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	62467	0	0
T10	23280	28	0	0
T11	586	127	0	0
T12	8077	408	0	0
T35	0	149	0	0
T36	0	39	0	0
T37	0	223	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	165	0	0
T140	0	128	0	0
T142	0	26	0	0
T151	0	235	0	0
T153	526	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	46	0	0
T10	23280	1	0	0
T11	586	1	0	0
T12	8077	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	1	0	0
T140	0	2	0	0
T142	0	2	0	0
T151	0	1	0	0
T153	526	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4255000	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4257254	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T3	19566	0	0	0
T4	500	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	1	0	0
T140	0	2	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	47	0	0
T10	23280	1	0	0
T11	586	1	0	0
T12	8077	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	1	0	0
T140	0	2	0	0
T142	0	2	0	0
T151	0	1	0	0
T153	526	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	46	0	0
T10	23280	1	0	0
T11	586	1	0	0
T12	8077	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	1	0	0
T140	0	2	0	0
T142	0	2	0	0
T151	0	1	0	0
T153	526	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	46	0	0
T10	23280	1	0	0
T11	586	1	0	0
T12	8077	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	1	0	0
T140	0	2	0	0
T142	0	2	0	0
T151	0	1	0	0
T153	526	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	62404	0	0
T10	23280	27	0	0
T11	586	125	0	0
T12	8077	407	0	0
T35	0	148	0	0
T36	0	38	0	0
T37	0	220	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	164	0	0
T140	0	125	0	0
T142	0	24	0	0
T151	0	234	0	0
T153	526	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	29	0	0
T10	23280	1	0	0
T11	586	0	0	0
T12	8077	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T67	0	1	0	0
T140	0	1	0	0
T142	0	2	0	0
T151	0	1	0	0
T153	526	0	0	0
T156	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T2,T14
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T14
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T12,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T9
1	0	Covered	T5,T2,T14
1	1	Covered	T19,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T36
0	1	Covered	T183
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T36
0	1	Covered	T37,T83,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T36
1	-	Covered	T37,T83,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T9,T12
DetectSt	168	Covered	T9,T12,T36
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T12,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T36
DebounceSt->IdleSt	163	Covered	T19,T68
DetectSt->IdleSt	186	Covered	T183
DetectSt->StableSt	191	Covered	T9,T12,T36
IdleSt->DebounceSt	148	Covered	T19,T9,T12
StableSt->IdleSt	206	Covered	T9,T12,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T9,T12
0	1	Covered	T19,T9,T12
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T36
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T183
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T83,T151
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	70	0	0
CntIncr_A	5213315	21664	0	0
CntNoWrap_A	5213315	4539891	0	0
DetectStDropOut_A	5213315	1	0	0
DetectedOut_A	5213315	30096	0	0
DetectedPulseOut_A	5213315	33	0	0
DisabledIdleSt_A	5213315	4302306	0	0
DisabledNoDetection_A	5213315	4304552	0	0
EnterDebounceSt_A	5213315	36	0	0
EnterDetectSt_A	5213315	34	0	0
EnterStableSt_A	5213315	33	0	0
PulseIsPulse_A	5213315	33	0	0
StayInStableSt	5213315	30040	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	6420	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	70	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	2	0	0
T12	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	2	0	0
T67	0	2	0	0
T83	0	2	0	0
T140	0	2	0	0
T151	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	21664	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	91	0	0
T12	0	69	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	10854	0	0
T37	0	92	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	99	0	0
T67	0	100	0	0
T83	0	67	0	0
T140	0	39	0	0
T151	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539891	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1	0	0
T166	563	0	0	0
T183	80324	1	0	0
T211	510	0	0	0
T212	414	0	0	0
T213	12652	0	0	0
T214	753	0	0	0
T215	1429	0	0	0
T216	1087	0	0	0
T217	968	0	0	0
T218	19886	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	30096	0	0
T9	32593	361	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	111	0	0
T25	1472	0	0	0
T36	0	13685	0	0
T37	0	82	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	42	0	0
T67	0	126	0	0
T75	0	63	0	0
T83	0	76	0	0
T140	0	8	0	0
T151	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	33	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	1	0	0
T25	1472	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T67	0	1	0	0
T75	0	1	0	0
T83	0	1	0	0
T140	0	1	0	0
T151	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4302306	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4304552	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	36	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	1	0	0
T12	0	1	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T64	0	1	0	0
T67	0	1	0	0
T83	0	1	0	0
T140	0	1	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	34	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	1	0	0
T25	1472	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T67	0	1	0	0
T75	0	1	0	0
T83	0	1	0	0
T140	0	1	0	0
T151	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	33	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	1	0	0
T25	1472	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T67	0	1	0	0
T75	0	1	0	0
T83	0	1	0	0
T140	0	1	0	0
T151	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	33	0	0
T9	32593	1	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	1	0	0
T25	1472	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	1	0	0
T67	0	1	0	0
T75	0	1	0	0
T83	0	1	0	0
T140	0	1	0	0
T151	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	30040	0	0
T9	32593	359	0	0
T10	23280	0	0	0
T11	586	0	0	0
T12	0	109	0	0
T25	1472	0	0	0
T36	0	13683	0	0
T37	0	79	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T64	0	40	0	0
T67	0	124	0	0
T75	0	62	0	0
T83	0	75	0	0
T140	0	7	0	0
T151	0	81	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	6420	0	0
T1	1309	0	0	0
T2	16218	26	0	0
T5	421	2	0	0
T6	649	0	0	0
T13	735	0	0	0
T14	429	3	0	0
T15	521	3	0	0
T16	539	6	0	0
T17	1571	6	0	0
T18	557	0	0	0
T19	0	22	0	0
T24	0	7	0	0
T47	0	4	0	0
T48	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	10	0	0
T37	39018	1	0	0
T75	0	1	0	0
T83	0	1	0	0
T93	416	0	0	0
T94	525	0	0	0
T95	3186	0	0	0
T96	5166	0	0	0
T97	745	0	0	0
T98	411	0	0	0
T99	448	0	0	0
T100	442	0	0	0
T101	302189	0	0	0
T140	0	1	0	0
T142	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T156	0	1	0	0
T183	0	1	0	0
T219	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T4,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T4,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T10
1	0	Covered	T5,T1,T6
1	1	Covered	T19,T4,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T11
0	1	Covered	T168,T190,T220
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T10,T11
0	1	Covered	T35,T37,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T10,T11
1	-	Covered	T35,T37,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T4,T10
DetectSt	168	Covered	T4,T10,T11
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T10,T11
DebounceSt->IdleSt	163	Covered	T19,T167,T68
DetectSt->IdleSt	186	Covered	T168,T190,T220
DetectSt->StableSt	191	Covered	T4,T10,T11
IdleSt->DebounceSt	148	Covered	T19,T4,T10
StableSt->IdleSt	206	Covered	T10,T35,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T4,T10
0	1	Covered	T19,T4,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T11
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T4,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T201
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T4,T10
DetectSt	-	-	-	-	1	-	-	Covered	T168,T190,T220
DetectSt	-	-	-	-	0	1	-	Covered	T4,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T37,T151
StableSt	-	-	-	-	-	-	0	Covered	T4,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	112	0	0
CntIncr_A	5213315	81531	0	0
CntNoWrap_A	5213315	4539849	0	0
DetectStDropOut_A	5213315	3	0	0
DetectedOut_A	5213315	4167	0	0
DetectedPulseOut_A	5213315	51	0	0
DisabledIdleSt_A	5213315	4213658	0	0
DisabledNoDetection_A	5213315	4215910	0	0
EnterDebounceSt_A	5213315	58	0	0
EnterDetectSt_A	5213315	54	0	0
EnterStableSt_A	5213315	51	0	0
PulseIsPulse_A	5213315	51	0	0
StayInStableSt	5213315	4091	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	112	0	0
T3	19566	0	0	0
T4	500	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	2	0	0
T35	0	4	0	0
T37	0	6	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	2	0	0
T140	0	2	0	0
T151	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	81531	0	0
T3	19566	0	0	0
T4	500	18	0	0
T10	0	39	0	0
T11	0	50	0	0
T19	6345	17	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	23	0	0
T35	0	158	0	0
T37	0	128	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	100	0	0
T140	0	39	0	0
T151	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539849	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	3	0	0
T90	42924	0	0	0
T168	803	1	0	0
T190	0	1	0	0
T220	0	1	0	0
T221	424	0	0	0
T222	421	0	0	0
T223	522	0	0	0
T224	492	0	0	0
T225	26047	0	0	0
T226	506	0	0	0
T227	4894	0	0	0
T228	22847	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4167	0	0
T4	500	73	0	0
T7	20808	0	0	0
T10	0	110	0	0
T11	0	50	0	0
T26	18391	0	0	0
T32	0	40	0	0
T35	0	40	0	0
T37	0	237	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	37	0	0
T75	0	81	0	0
T113	408	0	0	0
T140	0	24	0	0
T151	0	104	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	51	0	0
T4	500	1	0	0
T7	20808	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T26	18391	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	3	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T113	408	0	0	0
T140	0	1	0	0
T151	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4213658	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4215910	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	58	0	0
T3	19566	0	0	0
T4	500	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	3	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T67	0	1	0	0
T140	0	1	0	0
T151	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54	0	0
T4	500	1	0	0
T7	20808	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T26	18391	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	3	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T113	408	0	0	0
T140	0	1	0	0
T151	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	51	0	0
T4	500	1	0	0
T7	20808	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T26	18391	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	3	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T113	408	0	0	0
T140	0	1	0	0
T151	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	51	0	0
T4	500	1	0	0
T7	20808	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T26	18391	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	0	3	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T113	408	0	0	0
T140	0	1	0	0
T151	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4091	0	0
T4	500	71	0	0
T7	20808	0	0	0
T10	0	108	0	0
T11	0	48	0	0
T26	18391	0	0	0
T32	0	38	0	0
T35	0	38	0	0
T37	0	233	0	0
T49	425	0	0	0
T50	422	0	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T67	0	35	0	0
T75	0	80	0	0
T113	408	0	0	0
T140	0	23	0	0
T151	0	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	26	0	0
T35	1069	2	0	0
T37	0	2	0	0
T65	1025	0	0	0
T75	0	1	0	0
T81	11299	0	0	0
T87	0	2	0	0
T110	7803	0	0	0
T112	700	0	0	0
T133	3058	0	0	0
T134	407	0	0	0
T135	504	0	0	0
T140	0	1	0	0
T142	0	1	0	0
T148	0	1	0	0
T151	0	2	0	0
T156	0	2	0	0
T179	414	0	0	0
T180	422	0	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T9,T10,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T9
1	0	Covered	T5,T1,T6
1	1	Covered	T19,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T35
0	1	Covered	T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T35
0	1	Covered	T10,T35,T156
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T35
1	-	Covered	T10,T35,T156

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T9,T10
DetectSt	168	Covered	T9,T10,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T10,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T35
DebounceSt->IdleSt	163	Covered	T19,T227,T68
DetectSt->IdleSt	186	Covered	T90
DetectSt->StableSt	191	Covered	T9,T10,T35
IdleSt->DebounceSt	148	Covered	T19,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T9,T10
0	1	Covered	T19,T9,T10
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T227
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T90
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T35,T156
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	55	0	0
CntIncr_A	5213315	1626	0	0
CntNoWrap_A	5213315	4539906	0	0
DetectStDropOut_A	5213315	1	0	0
DetectedOut_A	5213315	2639	0	0
DetectedPulseOut_A	5213315	25	0	0
DisabledIdleSt_A	5213315	4526763	0	0
DisabledNoDetection_A	5213315	4529020	0	0
EnterDebounceSt_A	5213315	29	0	0
EnterDetectSt_A	5213315	26	0	0
EnterStableSt_A	5213315	25	0	0
PulseIsPulse_A	5213315	25	0	0
StayInStableSt	5213315	2599	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5213315	7141	0	0
gen_low_level_sva.LowLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	55	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	2	0	0
T10	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	4	0	0
T37	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	2	0	0
T140	0	2	0	0
T156	0	4	0	0
T166	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1626	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	91	0	0
T10	0	112	0	0
T19	6345	18	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	158	0	0
T37	0	46	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	22	0	0
T140	0	39	0	0
T156	0	172	0	0
T166	0	18	0	0
T182	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539906	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1	0	0
T90	42924	1	0	0
T132	1379	0	0	0
T228	22847	0	0	0
T229	1656	0	0	0
T230	749	0	0	0
T231	523	0	0	0
T232	425	0	0	0
T233	9116	0	0	0
T234	493	0	0	0
T235	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2639	0	0
T9	32593	269	0	0
T10	23280	126	0	0
T11	586	0	0	0
T25	1472	0	0	0
T35	0	300	0	0
T37	0	241	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T75	0	147	0	0
T87	0	118	0	0
T140	0	295	0	0
T156	0	244	0	0
T166	0	48	0	0
T182	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	25	0	0
T9	32593	1	0	0
T10	23280	2	0	0
T11	586	0	0	0
T25	1472	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T75	0	1	0	0
T87	0	2	0	0
T140	0	1	0	0
T156	0	2	0	0
T166	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4526763	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4529020	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	29	0	0
T3	19566	0	0	0
T4	500	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T75	0	1	0	0
T140	0	1	0	0
T156	0	2	0	0
T166	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	26	0	0
T9	32593	1	0	0
T10	23280	2	0	0
T11	586	0	0	0
T25	1472	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T75	0	1	0	0
T87	0	2	0	0
T140	0	1	0	0
T156	0	2	0	0
T166	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	25	0	0
T9	32593	1	0	0
T10	23280	2	0	0
T11	586	0	0	0
T25	1472	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T75	0	1	0	0
T87	0	2	0	0
T140	0	1	0	0
T156	0	2	0	0
T166	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	25	0	0
T9	32593	1	0	0
T10	23280	2	0	0
T11	586	0	0	0
T25	1472	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T75	0	1	0	0
T87	0	2	0	0
T140	0	1	0	0
T156	0	2	0	0
T166	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2599	0	0
T9	32593	267	0	0
T10	23280	124	0	0
T11	586	0	0	0
T25	1472	0	0	0
T35	0	297	0	0
T37	0	239	0	0
T38	7459	0	0	0
T39	5419	0	0	0
T40	2614	0	0	0
T41	4865	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T75	0	145	0	0
T87	0	115	0	0
T140	0	293	0	0
T156	0	242	0	0
T166	0	46	0	0
T182	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	7141	0	0
T1	1309	9	0	0
T2	16218	35	0	0
T5	421	3	0	0
T6	649	3	0	0
T13	735	3	0	0
T14	429	2	0	0
T15	521	5	0	0
T16	539	5	0	0
T17	1571	7	0	0
T18	557	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	10	0	0
T10	23280	2	0	0
T11	586	0	0	0
T12	8077	0	0	0
T35	0	1	0	0
T38	7459	0	0	0
T41	4865	0	0	0
T42	730	0	0	0
T43	4917	0	0	0
T59	493	0	0	0
T60	493	0	0	0
T87	0	1	0	0
T90	0	1	0	0
T153	526	0	0	0
T156	0	2	0	0
T201	0	1	0	0
T202	0	1	0	0
T236	0	1	0	0