Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T19,T3
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T2,T19,T3
1	1	Covered	T2,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T19,T39,T41
1	0	Covered	T19,T46,T81

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
1	0	Covered	T71,T72,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T19,T3
1	-	Covered	T2,T19,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T19,T3
DetectSt	168	Covered	T2,T19,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T19,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T111,T237
DetectSt->IdleSt	186	Covered	T19,T39,T41
DetectSt->StableSt	191	Covered	T2,T19,T3
IdleSt->DebounceSt	148	Covered	T2,T19,T3
StableSt->IdleSt	206	Covered	T2,T19,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T2,T19,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T111,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T39,T41
DetectSt	-	-	-	-	0	1	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	0	0	-	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	0	Covered	T2,T19,T3
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	3169	0	0
CntIncr_A	5213315	105002	0	0
CntNoWrap_A	5213315	4536792	0	0
DetectStDropOut_A	5213315	550	0	0
DetectedOut_A	5213315	65368	0	0
DetectedPulseOut_A	5213315	829	0	0
DisabledIdleSt_A	5213315	4096958	0	0
DisabledNoDetection_A	5213315	4099081	0	0
EnterDebounceSt_A	5213315	1594	0	0
EnterDetectSt_A	5213315	1576	0	0
EnterStableSt_A	5213315	829	0	0
PulseIsPulse_A	5213315	829	0	0
StayInStableSt	5213315	64453	0	0
gen_high_event_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	721	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	3169	0	0
T2	16218	26	0	0
T3	0	28	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	16	0	0
T24	492	0	0	0
T30	0	28	0	0
T38	0	26	0	0
T39	0	20	0	0
T41	0	8	0	0
T43	0	38	0	0
T45	0	32	0	0
T46	0	60	0	0
T47	506	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	105002	0	0
T2	16218	832	0	0
T3	0	1064	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	369	0	0
T24	492	0	0	0
T30	0	1218	0	0
T38	0	533	0	0
T39	0	553	0	0
T41	0	178	0	0
T43	0	871	0	0
T45	0	835	0	0
T46	0	1992	0	0
T47	506	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4536792	0	0
T1	1309	908	0	0
T2	16218	15766	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	550	0	0
T3	19566	0	0	0
T4	500	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T39	0	10	0	0
T41	0	4	0	0
T43	0	19	0	0
T45	0	16	0	0
T46	0	17	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T81	0	1	0	0
T96	0	10	0	0
T238	0	10	0	0
T239	0	26	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	65368	0	0
T2	16218	1650	0	0
T3	0	835	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	339	0	0
T24	492	0	0	0
T30	0	354	0	0
T33	0	633	0	0
T38	0	378	0	0
T47	506	0	0	0
T110	0	28	0	0
T111	0	77	0	0
T240	0	345	0	0
T241	0	624	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	829	0	0
T2	16218	13	0	0
T3	0	14	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	14	0	0
T33	0	11	0	0
T38	0	13	0	0
T47	506	0	0	0
T110	0	8	0	0
T111	0	1	0	0
T240	0	11	0	0
T241	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4096958	0	0
T1	1309	908	0	0
T2	16218	8904	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4099081	0	0
T1	1309	909	0	0
T2	16218	8904	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1594	0	0
T2	16218	13	0	0
T3	0	14	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	9	0	0
T24	492	0	0	0
T30	0	14	0	0
T38	0	13	0	0
T39	0	10	0	0
T41	0	4	0	0
T43	0	19	0	0
T45	0	16	0	0
T46	0	30	0	0
T47	506	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1576	0	0
T2	16218	13	0	0
T3	0	14	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	7	0	0
T24	492	0	0	0
T30	0	14	0	0
T38	0	13	0	0
T39	0	10	0	0
T41	0	4	0	0
T43	0	19	0	0
T45	0	16	0	0
T46	0	30	0	0
T47	506	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	829	0	0
T2	16218	13	0	0
T3	0	14	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	14	0	0
T33	0	11	0	0
T38	0	13	0	0
T47	506	0	0	0
T110	0	8	0	0
T111	0	1	0	0
T240	0	11	0	0
T241	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	829	0	0
T2	16218	13	0	0
T3	0	14	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	14	0	0
T33	0	11	0	0
T38	0	13	0	0
T47	506	0	0	0
T110	0	8	0	0
T111	0	1	0	0
T240	0	11	0	0
T241	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	64453	0	0
T2	16218	1634	0	0
T3	0	819	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	334	0	0
T24	492	0	0	0
T30	0	340	0	0
T33	0	621	0	0
T38	0	365	0	0
T47	506	0	0	0
T110	0	20	0	0
T111	0	76	0	0
T240	0	333	0	0
T241	0	599	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	721	0	0
T2	16218	10	0	0
T3	0	12	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	14	0	0
T33	0	10	0	0
T38	0	13	0	0
T47	506	0	0	0
T110	0	8	0	0
T111	0	1	0	0
T240	0	10	0	0
T241	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T19,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T2,T17,T19
1	1	Covered	T2,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T32,T82,T83
1	0	Covered	T19,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
1	0	Covered	T69,T68

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T19,T3
1	-	Covered	T2,T19,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T19,T3
DetectSt	168	Covered	T2,T19,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T19,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T26,T12
DetectSt->IdleSt	186	Covered	T19,T32,T82
DetectSt->StableSt	191	Covered	T2,T19,T3
IdleSt->DebounceSt	148	Covered	T2,T19,T3
StableSt->IdleSt	206	Covered	T2,T19,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T12,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T32,T82
DetectSt	-	-	-	-	0	1	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	0	0	-	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	0	Covered	T2,T19,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	912	0	0
CntIncr_A	5213315	47168	0	0
CntNoWrap_A	5213315	4539049	0	0
DetectStDropOut_A	5213315	75	0	0
DetectedOut_A	5213315	13134	0	0
DetectedPulseOut_A	5213315	333	0	0
DisabledIdleSt_A	5213315	4164453	0	0
DisabledNoDetection_A	5213315	4166070	0	0
EnterDebounceSt_A	5213315	501	0	0
EnterDetectSt_A	5213315	414	0	0
EnterStableSt_A	5213315	333	0	0
PulseIsPulse_A	5213315	333	0	0
StayInStableSt	5213315	12767	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	295	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	912	0	0
T2	16218	6	0	0
T3	0	2	0	0
T7	0	4	0	0
T9	0	2	0	0
T10	0	4	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	8	0	0
T24	492	0	0	0
T26	0	9	0	0
T44	0	2	0	0
T47	506	0	0	0
T80	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	47168	0	0
T2	16218	264	0	0
T3	0	67	0	0
T7	0	368	0	0
T9	0	25	0	0
T10	0	183	0	0
T12	0	20	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	177	0	0
T24	492	0	0	0
T26	0	697	0	0
T44	0	98	0	0
T47	506	0	0	0
T80	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539049	0	0
T1	1309	908	0	0
T2	16218	15786	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	75	0	0
T32	26822	1	0	0
T34	0	2	0	0
T73	1140	0	0	0
T82	30065	6	0	0
T83	13887	5	0	0
T85	0	3	0	0
T87	0	2	0	0
T88	0	4	0	0
T89	0	4	0	0
T90	0	7	0	0
T91	0	7	0	0
T102	505	0	0	0
T103	715	0	0	0
T104	541	0	0	0
T105	28280	0	0	0
T106	502	0	0	0
T107	634	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	13134	0	0
T2	16218	137	0	0
T3	0	66	0	0
T7	0	25	0	0
T9	0	3	0	0
T10	0	37	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	93	0	0
T24	492	0	0	0
T26	0	53	0	0
T44	0	19	0	0
T47	506	0	0	0
T53	0	19	0	0
T108	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	333	0	0
T2	16218	3	0	0
T3	0	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	0	4	0	0
T44	0	1	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4164453	0	0
T1	1309	908	0	0
T2	16218	14145	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4166070	0	0
T1	1309	909	0	0
T2	16218	14146	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	501	0	0
T2	16218	3	0	0
T3	0	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T26	0	5	0	0
T44	0	1	0	0
T47	506	0	0	0
T80	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	414	0	0
T2	16218	3	0	0
T3	0	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	3	0	0
T24	492	0	0	0
T26	0	4	0	0
T44	0	1	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	333	0	0
T2	16218	3	0	0
T3	0	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	0	4	0	0
T44	0	1	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	333	0	0
T2	16218	3	0	0
T3	0	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	0	4	0	0
T44	0	1	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	12767	0	0
T2	16218	134	0	0
T3	0	65	0	0
T7	0	23	0	0
T9	0	2	0	0
T10	0	35	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	92	0	0
T24	492	0	0	0
T26	0	49	0	0
T44	0	18	0	0
T47	506	0	0	0
T53	0	18	0	0
T108	0	78	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	295	0	0
T2	16218	3	0	0
T3	0	1	0	0
T7	0	2	0	0
T9	0	1	0	0
T10	0	2	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	0	4	0	0
T44	0	1	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T19,T3
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T2,T19,T3
1	1	Covered	T2,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T19,T39,T38
1	0	Covered	T19,T38,T46

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T19,T3
1	-	Covered	T2,T19,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T19,T3
DetectSt	168	Covered	T2,T19,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T19,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T111,T237
DetectSt->IdleSt	186	Covered	T19,T39,T38
DetectSt->StableSt	191	Covered	T2,T19,T3
IdleSt->DebounceSt	148	Covered	T2,T19,T3
StableSt->IdleSt	206	Covered	T2,T19,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T2,T19,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T111,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T39,T38
DetectSt	-	-	-	-	0	1	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	0	0	-	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	0	Covered	T2,T19,T3
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	2890	0	0
CntIncr_A	5213315	101801	0	0
CntNoWrap_A	5213315	4537071	0	0
DetectStDropOut_A	5213315	472	0	0
DetectedOut_A	5213315	71934	0	0
DetectedPulseOut_A	5213315	789	0	0
DisabledIdleSt_A	5213315	4089356	0	0
DisabledNoDetection_A	5213315	4091475	0	0
EnterDebounceSt_A	5213315	1459	0	0
EnterDetectSt_A	5213315	1432	0	0
EnterStableSt_A	5213315	789	0	0
PulseIsPulse_A	5213315	789	0	0
StayInStableSt	5213315	71054	0	0
gen_high_event_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	698	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2890	0	0
T2	16218	24	0	0
T3	0	18	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	16	0	0
T24	492	0	0	0
T30	0	50	0	0
T38	0	8	0	0
T39	0	52	0	0
T41	0	49	0	0
T43	0	6	0	0
T45	0	10	0	0
T46	0	14	0	0
T47	506	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	101801	0	0
T2	16218	1044	0	0
T3	0	612	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	341	0	0
T24	492	0	0	0
T30	0	2150	0	0
T38	0	276	0	0
T39	0	1457	0	0
T41	0	1127	0	0
T43	0	135	0	0
T45	0	261	0	0
T46	0	459	0	0
T47	506	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4537071	0	0
T1	1309	908	0	0
T2	16218	15768	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	472	0	0
T3	19566	0	0	0
T4	500	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T38	0	1	0	0
T39	0	26	0	0
T41	0	24	0	0
T43	0	3	0	0
T45	0	5	0	0
T46	0	5	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T81	0	17	0	0
T96	0	2	0	0
T239	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	71934	0	0
T2	16218	1728	0	0
T3	0	528	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	279	0	0
T24	492	0	0	0
T30	0	2052	0	0
T33	0	687	0	0
T47	506	0	0	0
T110	0	1819	0	0
T111	0	308	0	0
T238	0	1116	0	0
T240	0	1724	0	0
T241	0	1302	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	789	0	0
T2	16218	12	0	0
T3	0	9	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	25	0	0
T33	0	6	0	0
T47	506	0	0	0
T110	0	24	0	0
T111	0	5	0	0
T238	0	13	0	0
T240	0	22	0	0
T241	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4089356	0	0
T1	1309	908	0	0
T2	16218	8493	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4091475	0	0
T1	1309	909	0	0
T2	16218	8494	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1459	0	0
T2	16218	12	0	0
T3	0	9	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	9	0	0
T24	492	0	0	0
T30	0	25	0	0
T38	0	4	0	0
T39	0	26	0	0
T41	0	25	0	0
T43	0	3	0	0
T45	0	5	0	0
T46	0	7	0	0
T47	506	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1432	0	0
T2	16218	12	0	0
T3	0	9	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	7	0	0
T24	492	0	0	0
T30	0	25	0	0
T38	0	4	0	0
T39	0	26	0	0
T41	0	25	0	0
T43	0	3	0	0
T45	0	5	0	0
T46	0	7	0	0
T47	506	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	789	0	0
T2	16218	12	0	0
T3	0	9	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	25	0	0
T33	0	6	0	0
T47	506	0	0	0
T110	0	24	0	0
T111	0	5	0	0
T238	0	13	0	0
T240	0	22	0	0
T241	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	789	0	0
T2	16218	12	0	0
T3	0	9	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	25	0	0
T33	0	6	0	0
T47	506	0	0	0
T110	0	24	0	0
T111	0	5	0	0
T238	0	13	0	0
T240	0	22	0	0
T241	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	71054	0	0
T2	16218	1714	0	0
T3	0	517	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	274	0	0
T24	492	0	0	0
T30	0	2026	0	0
T33	0	681	0	0
T47	506	0	0	0
T110	0	1795	0	0
T111	0	303	0	0
T238	0	1102	0	0
T240	0	1698	0	0
T241	0	1278	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	698	0	0
T2	16218	10	0	0
T3	0	7	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	24	0	0
T33	0	6	0	0
T47	506	0	0	0
T110	0	24	0	0
T111	0	5	0	0
T238	0	12	0	0
T240	0	18	0	0
T241	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T19,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T2,T17,T19
1	1	Covered	T2,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T19,T26,T85
1	0	Covered	T19,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T19

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T19,T3
1	-	Covered	T2,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T19,T3
DetectSt	168	Covered	T2,T19,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T19,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T10,T31
DetectSt->IdleSt	186	Covered	T19,T26,T85
DetectSt->StableSt	191	Covered	T2,T19,T3
IdleSt->DebounceSt	148	Covered	T2,T19,T3
StableSt->IdleSt	206	Covered	T2,T19,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T31,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T26,T85
DetectSt	-	-	-	-	0	1	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	0	0	-	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	0	Covered	T2,T19,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	816	0	0
CntIncr_A	5213315	46408	0	0
CntNoWrap_A	5213315	4539145	0	0
DetectStDropOut_A	5213315	77	0	0
DetectedOut_A	5213315	11978	0	0
DetectedPulseOut_A	5213315	304	0	0
DisabledIdleSt_A	5213315	4165429	0	0
DisabledNoDetection_A	5213315	4167103	0	0
EnterDebounceSt_A	5213315	432	0	0
EnterDetectSt_A	5213315	386	0	0
EnterStableSt_A	5213315	304	0	0
PulseIsPulse_A	5213315	304	0	0
StayInStableSt	5213315	11644	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	272	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	816	0	0
T2	16218	4	0	0
T3	0	2	0	0
T7	0	6	0	0
T10	0	3	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	8	0	0
T24	492	0	0	0
T26	0	18	0	0
T30	0	2	0	0
T31	0	8	0	0
T47	506	0	0	0
T53	0	2	0	0
T108	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	46408	0	0
T2	16218	132	0	0
T3	0	85	0	0
T7	0	561	0	0
T10	0	160	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	117	0	0
T24	492	0	0	0
T26	0	1465	0	0
T30	0	89	0	0
T31	0	652	0	0
T47	506	0	0	0
T53	0	130	0	0
T108	0	387	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539145	0	0
T1	1309	908	0	0
T2	16218	15788	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	77	0	0
T3	19566	0	0	0
T4	500	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	9	0	0
T29	752	0	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T85	0	9	0	0
T89	0	2	0	0
T90	0	2	0	0
T116	0	4	0	0
T243	0	2	0	0
T244	0	7	0	0
T245	0	3	0	0
T246	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	11978	0	0
T2	16218	135	0	0
T3	0	49	0	0
T7	0	27	0	0
T10	0	96	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	92	0	0
T24	492	0	0	0
T30	0	32	0	0
T31	0	12	0	0
T47	506	0	0	0
T53	0	17	0	0
T108	0	130	0	0
T242	0	344	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	304	0	0
T2	16218	2	0	0
T3	0	1	0	0
T7	0	3	0	0
T10	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	3	0	0
T242	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4165429	0	0
T1	1309	908	0	0
T2	16218	14066	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4167103	0	0
T1	1309	909	0	0
T2	16218	14068	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	432	0	0
T2	16218	2	0	0
T3	0	1	0	0
T7	0	3	0	0
T10	0	2	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T26	0	9	0	0
T30	0	1	0	0
T31	0	5	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	386	0	0
T2	16218	2	0	0
T3	0	1	0	0
T7	0	3	0	0
T10	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	3	0	0
T24	492	0	0	0
T26	0	9	0	0
T30	0	1	0	0
T31	0	3	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	304	0	0
T2	16218	2	0	0
T3	0	1	0	0
T7	0	3	0	0
T10	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	3	0	0
T242	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	304	0	0
T2	16218	2	0	0
T3	0	1	0	0
T7	0	3	0	0
T10	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	3	0	0
T242	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	11644	0	0
T2	16218	133	0	0
T3	0	48	0	0
T7	0	24	0	0
T10	0	95	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	91	0	0
T24	492	0	0	0
T30	0	31	0	0
T31	0	9	0	0
T47	506	0	0	0
T53	0	16	0	0
T108	0	127	0	0
T242	0	338	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	272	0	0
T2	16218	2	0	0
T3	0	1	0	0
T7	0	3	0	0
T10	0	1	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T30	0	1	0	0
T31	0	3	0	0
T32	0	2	0	0
T47	506	0	0	0
T53	0	1	0	0
T108	0	3	0	0
T242	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T19,T3
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T2,T19,T3
1	1	Covered	T2,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T2,T19,T39
1	0	Covered	T2,T19,T46

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T3,T38
0	1	Covered	T19,T3,T38
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T3,T38
1	-	Covered	T19,T3,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T19,T3
DetectSt	168	Covered	T2,T19,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T19,T3,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T111,T237
DetectSt->IdleSt	186	Covered	T2,T19,T39
DetectSt->StableSt	191	Covered	T19,T3,T38
IdleSt->DebounceSt	148	Covered	T2,T19,T3
StableSt->IdleSt	206	Covered	T19,T3,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T2,T19,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T111,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T19,T39
DetectSt	-	-	-	-	0	1	-	Covered	T19,T3,T38
DetectSt	-	-	-	-	0	0	-	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T19,T3,T38
StableSt	-	-	-	-	-	-	0	Covered	T19,T3,T38
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	3050	0	0
CntIncr_A	5213315	109072	0	0
CntNoWrap_A	5213315	4536911	0	0
DetectStDropOut_A	5213315	506	0	0
DetectedOut_A	5213315	54733	0	0
DetectedPulseOut_A	5213315	740	0	0
DisabledIdleSt_A	5213315	4103775	0	0
DisabledNoDetection_A	5213315	4105909	0	0
EnterDebounceSt_A	5213315	1542	0	0
EnterDetectSt_A	5213315	1511	0	0
EnterStableSt_A	5213315	740	0	0
PulseIsPulse_A	5213315	740	0	0
StayInStableSt	5213315	53916	0	0
gen_high_event_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	659	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	3050	0	0
T2	16218	50	0	0
T3	0	6	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	16	0	0
T24	492	0	0	0
T30	0	40	0	0
T38	0	48	0	0
T39	0	46	0	0
T41	0	17	0	0
T43	0	12	0	0
T45	0	22	0	0
T46	0	30	0	0
T47	506	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	109072	0	0
T2	16218	2838	0	0
T3	0	165	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	313	0	0
T24	492	0	0	0
T30	0	1760	0	0
T38	0	1152	0	0
T39	0	1290	0	0
T41	0	402	0	0
T43	0	271	0	0
T45	0	577	0	0
T46	0	992	0	0
T47	506	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4536911	0	0
T1	1309	908	0	0
T2	16218	15742	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	506	0	0
T2	16218	13	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T33	0	4	0	0
T39	0	23	0	0
T41	0	8	0	0
T43	0	6	0	0
T45	0	11	0	0
T46	0	6	0	0
T47	506	0	0	0
T96	0	25	0	0
T239	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	54733	0	0
T3	19566	120	0	0
T4	500	0	0	0
T19	6345	352	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T30	0	496	0	0
T38	0	1634	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T111	0	812	0	0
T218	0	1864	0	0
T238	0	629	0	0
T247	0	1630	0	0
T248	0	2362	0	0
T249	0	681	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	740	0	0
T3	19566	3	0	0
T4	500	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T30	0	20	0	0
T38	0	24	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T111	0	9	0	0
T218	0	29	0	0
T238	0	18	0	0
T247	0	22	0	0
T248	0	28	0	0
T249	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4103775	0	0
T1	1309	908	0	0
T2	16218	9923	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4105909	0	0
T1	1309	909	0	0
T2	16218	9926	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1542	0	0
T2	16218	25	0	0
T3	0	3	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	9	0	0
T24	492	0	0	0
T30	0	20	0	0
T38	0	24	0	0
T39	0	23	0	0
T41	0	9	0	0
T43	0	6	0	0
T45	0	11	0	0
T46	0	15	0	0
T47	506	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1511	0	0
T2	16218	25	0	0
T3	0	3	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	7	0	0
T24	492	0	0	0
T30	0	20	0	0
T38	0	24	0	0
T39	0	23	0	0
T41	0	9	0	0
T43	0	6	0	0
T45	0	11	0	0
T46	0	15	0	0
T47	506	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	740	0	0
T3	19566	3	0	0
T4	500	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T30	0	20	0	0
T38	0	24	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T111	0	9	0	0
T218	0	29	0	0
T238	0	18	0	0
T247	0	22	0	0
T248	0	28	0	0
T249	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	740	0	0
T3	19566	3	0	0
T4	500	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T30	0	20	0	0
T38	0	24	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T111	0	9	0	0
T218	0	29	0	0
T238	0	18	0	0
T247	0	22	0	0
T248	0	28	0	0
T249	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	53916	0	0
T3	19566	117	0	0
T4	500	0	0	0
T19	6345	347	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T30	0	476	0	0
T38	0	1610	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T111	0	803	0	0
T218	0	1832	0	0
T238	0	609	0	0
T247	0	1604	0	0
T248	0	2334	0	0
T249	0	668	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	659	0	0
T3	19566	3	0	0
T4	500	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T30	0	20	0	0
T38	0	24	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T111	0	9	0	0
T218	0	26	0	0
T238	0	16	0	0
T247	0	18	0	0
T248	0	28	0	0
T249	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T19,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T26,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T19,T26,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T19,T26,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T3,T26
1	0	Covered	T2,T17,T19
1	1	Covered	T19,T26,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T26,T7
0	1	Covered	T19,T38,T53
1	0	Covered	T19,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T26,T7
0	1	Covered	T26,T7,T31
1	0	Covered	T19

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T26,T7
1	-	Covered	T26,T7,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T26,T7
DetectSt	168	Covered	T19,T26,T7
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T19,T26,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T26,T7
DebounceSt->IdleSt	163	Covered	T19,T26,T10
DetectSt->IdleSt	186	Covered	T19,T38,T53
DetectSt->StableSt	191	Covered	T19,T26,T7
IdleSt->DebounceSt	148	Covered	T19,T26,T7
StableSt->IdleSt	206	Covered	T19,T26,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T26,T7
0	1	Covered	T19,T26,T7
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T26,T7
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T26,T7
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T26,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T10,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T26,T7
DetectSt	-	-	-	-	1	-	-	Covered	T19,T38,T53
DetectSt	-	-	-	-	0	1	-	Covered	T19,T26,T7
DetectSt	-	-	-	-	0	0	-	Covered	T19,T26,T7
StableSt	-	-	-	-	-	-	1	Covered	T19,T26,T7
StableSt	-	-	-	-	-	-	0	Covered	T19,T26,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	795	0	0
CntIncr_A	5213315	45456	0	0
CntNoWrap_A	5213315	4539166	0	0
DetectStDropOut_A	5213315	70	0	0
DetectedOut_A	5213315	12822	0	0
DetectedPulseOut_A	5213315	299	0	0
DisabledIdleSt_A	5213315	4188520	0	0
DisabledNoDetection_A	5213315	4190227	0	0
EnterDebounceSt_A	5213315	424	0	0
EnterDetectSt_A	5213315	372	0	0
EnterStableSt_A	5213315	299	0	0
PulseIsPulse_A	5213315	299	0	0
StayInStableSt	5213315	12507	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	281	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	795	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	8	0	0
T10	0	1	0	0
T19	6345	8	0	0
T24	492	0	0	0
T26	18391	11	0	0
T29	752	0	0	0
T31	0	27	0	0
T38	0	7	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T53	0	4	0	0
T108	0	15	0	0
T242	0	4	0	0
T250	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	45456	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	768	0	0
T10	0	63	0	0
T19	6345	187	0	0
T24	492	0	0	0
T26	18391	742	0	0
T29	752	0	0	0
T31	0	1828	0	0
T38	0	356	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T53	0	292	0	0
T108	0	1308	0	0
T242	0	257	0	0
T250	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539166	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	70	0	0
T3	19566	0	0	0
T4	500	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T38	0	3	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T53	0	2	0	0
T105	0	1	0	0
T108	0	7	0	0
T183	0	4	0	0
T242	0	2	0	0
T251	0	4	0	0
T252	0	6	0	0
T253	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	12822	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	19	0	0
T19	6345	92	0	0
T24	492	0	0	0
T26	18391	168	0	0
T29	752	0	0	0
T31	0	600	0	0
T32	0	55	0	0
T34	0	191	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T83	0	12	0	0
T238	0	69	0	0
T247	0	195	0	0
T254	0	309	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	299	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	5	0	0
T29	752	0	0	0
T31	0	12	0	0
T32	0	2	0	0
T34	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T83	0	1	0	0
T238	0	2	0	0
T247	0	4	0	0
T254	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4188520	0	0
T1	1309	908	0	0
T2	16218	15792	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4190227	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	424	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	4	0	0
T10	0	1	0	0
T19	6345	5	0	0
T24	492	0	0	0
T26	18391	6	0	0
T29	752	0	0	0
T31	0	15	0	0
T38	0	4	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T53	0	2	0	0
T108	0	8	0	0
T242	0	2	0	0
T250	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	372	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	4	0	0
T19	6345	3	0	0
T24	492	0	0	0
T26	18391	5	0	0
T29	752	0	0	0
T31	0	12	0	0
T32	0	2	0	0
T38	0	3	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T53	0	2	0	0
T83	0	1	0	0
T108	0	7	0	0
T242	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	299	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	5	0	0
T29	752	0	0	0
T31	0	12	0	0
T32	0	2	0	0
T34	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T83	0	1	0	0
T238	0	2	0	0
T247	0	4	0	0
T254	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	299	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	4	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	5	0	0
T29	752	0	0	0
T31	0	12	0	0
T32	0	2	0	0
T34	0	2	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T83	0	1	0	0
T238	0	2	0	0
T247	0	4	0	0
T254	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	12507	0	0
T3	19566	0	0	0
T4	500	0	0	0
T7	0	15	0	0
T19	6345	91	0	0
T24	492	0	0	0
T26	18391	163	0	0
T29	752	0	0	0
T31	0	588	0	0
T32	0	53	0	0
T34	0	189	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T83	0	11	0	0
T238	0	67	0	0
T247	0	187	0	0
T254	0	301	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	281	0	0
T7	20808	4	0	0
T8	1575	0	0	0
T26	18391	5	0	0
T31	0	12	0	0
T32	0	2	0	0
T34	0	2	0	0
T51	521	0	0	0
T55	499	0	0	0
T56	984	0	0	0
T62	525	0	0	0
T63	501	0	0	0
T83	0	1	0	0
T85	0	4	0	0
T113	408	0	0	0
T114	429	0	0	0
T116	0	4	0	0
T238	0	2	0	0
T254	0	8	0	0