Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T19,T3
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T2,T19,T3
1	1	Covered	T2,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T19,T39,T41
1	0	Covered	T19,T110,T241

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
1	0	Covered	T70

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T19,T3
1	-	Covered	T2,T19,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T19,T3
DetectSt	168	Covered	T2,T19,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T19,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T111,T237
DetectSt->IdleSt	186	Covered	T19,T39,T41
DetectSt->StableSt	191	Covered	T2,T19,T3
IdleSt->DebounceSt	148	Covered	T2,T19,T3
StableSt->IdleSt	206	Covered	T2,T19,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T2,T19,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T111,T237
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T39,T41
DetectSt	-	-	-	-	0	1	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	0	0	-	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	0	Covered	T2,T19,T3
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	2834	0	0
CntIncr_A	5213315	108878	0	0
CntNoWrap_A	5213315	4537127	0	0
DetectStDropOut_A	5213315	533	0	0
DetectedOut_A	5213315	45259	0	0
DetectedPulseOut_A	5213315	636	0	0
DisabledIdleSt_A	5213315	4109747	0	0
DisabledNoDetection_A	5213315	4111891	0	0
EnterDebounceSt_A	5213315	1435	0	0
EnterDetectSt_A	5213315	1401	0	0
EnterStableSt_A	5213315	636	0	0
PulseIsPulse_A	5213315	636	0	0
StayInStableSt	5213315	44556	0	0
gen_high_event_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	567	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	2834	0	0
T2	16218	10	0	0
T3	0	46	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	16	0	0
T24	492	0	0	0
T30	0	2	0	0
T38	0	34	0	0
T39	0	48	0	0
T41	0	47	0	0
T43	0	54	0	0
T45	0	6	0	0
T46	0	48	0	0
T47	506	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	108878	0	0
T2	16218	315	0	0
T3	0	1978	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	418	0	0
T24	492	0	0	0
T30	0	77	0	0
T38	0	1139	0	0
T39	0	1347	0	0
T41	0	1078	0	0
T43	0	1242	0	0
T45	0	157	0	0
T46	0	1224	0	0
T47	506	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4537127	0	0
T1	1309	908	0	0
T2	16218	15782	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	533	0	0
T3	19566	0	0	0
T4	500	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	18391	0	0	0
T29	752	0	0	0
T39	0	24	0	0
T41	0	23	0	0
T43	0	27	0	0
T45	0	3	0	0
T47	506	0	0	0
T48	454	0	0	0
T49	425	0	0	0
T50	422	0	0	0
T96	0	10	0	0
T111	0	9	0	0
T239	0	8	0	0
T241	0	3	0	0
T255	0	21	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	45259	0	0
T2	16218	405	0	0
T3	0	2146	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	313	0	0
T24	492	0	0	0
T30	0	35	0	0
T33	0	1698	0	0
T38	0	190	0	0
T46	0	2079	0	0
T47	506	0	0	0
T81	0	1656	0	0
T238	0	190	0	0
T240	0	1631	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	636	0	0
T2	16218	5	0	0
T3	0	23	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	1	0	0
T33	0	21	0	0
T38	0	17	0	0
T46	0	24	0	0
T47	506	0	0	0
T81	0	11	0	0
T238	0	3	0	0
T240	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4109747	0	0
T1	1309	908	0	0
T2	16218	9760	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4111891	0	0
T1	1309	909	0	0
T2	16218	9762	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1435	0	0
T2	16218	5	0	0
T3	0	23	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	9	0	0
T24	492	0	0	0
T30	0	1	0	0
T38	0	17	0	0
T39	0	24	0	0
T41	0	24	0	0
T43	0	27	0	0
T45	0	3	0	0
T46	0	24	0	0
T47	506	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	1401	0	0
T2	16218	5	0	0
T3	0	23	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	7	0	0
T24	492	0	0	0
T30	0	1	0	0
T38	0	17	0	0
T39	0	24	0	0
T41	0	24	0	0
T43	0	27	0	0
T45	0	3	0	0
T46	0	24	0	0
T47	506	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	636	0	0
T2	16218	5	0	0
T3	0	23	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	1	0	0
T33	0	21	0	0
T38	0	17	0	0
T46	0	24	0	0
T47	506	0	0	0
T81	0	11	0	0
T238	0	3	0	0
T240	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	636	0	0
T2	16218	5	0	0
T3	0	23	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	1	0	0
T33	0	21	0	0
T38	0	17	0	0
T46	0	24	0	0
T47	506	0	0	0
T81	0	11	0	0
T238	0	3	0	0
T240	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	44556	0	0
T2	16218	399	0	0
T3	0	2119	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	308	0	0
T24	492	0	0	0
T30	0	34	0	0
T33	0	1674	0	0
T38	0	173	0	0
T46	0	2053	0	0
T47	506	0	0	0
T81	0	1643	0	0
T238	0	186	0	0
T240	0	1602	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	567	0	0
T2	16218	4	0	0
T3	0	19	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T30	0	1	0	0
T33	0	18	0	0
T38	0	17	0	0
T46	0	22	0	0
T47	506	0	0	0
T81	0	9	0	0
T238	0	2	0	0
T240	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T19,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T19,T3
1	0	Covered	T2,T17,T19
1	1	Covered	T2,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T31,T242,T82
1	0	Covered	T19,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T3
0	1	Covered	T2,T26,T7
1	0	Covered	T19

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T19,T3
1	-	Covered	T2,T26,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T19,T3
DetectSt	168	Covered	T2,T19,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T19,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T3,T7
DetectSt->IdleSt	186	Covered	T19,T31,T242
DetectSt->StableSt	191	Covered	T2,T19,T3
IdleSt->DebounceSt	148	Covered	T2,T19,T3
StableSt->IdleSt	206	Covered	T2,T19,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T19,T3
0	1	Covered	T2,T19,T3
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T19,T68
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T7,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T31,T242
DetectSt	-	-	-	-	0	1	-	Covered	T2,T19,T3
DetectSt	-	-	-	-	0	0	-	Covered	T2,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T19,T26
StableSt	-	-	-	-	-	-	0	Covered	T2,T19,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5213315	842	0	0
CntIncr_A	5213315	48622	0	0
CntNoWrap_A	5213315	4539119	0	0
DetectStDropOut_A	5213315	60	0	0
DetectedOut_A	5213315	12806	0	0
DetectedPulseOut_A	5213315	330	0	0
DisabledIdleSt_A	5213315	4191663	0	0
DisabledNoDetection_A	5213315	4193372	0	0
EnterDebounceSt_A	5213315	448	0	0
EnterDetectSt_A	5213315	396	0	0
EnterStableSt_A	5213315	330	0	0
PulseIsPulse_A	5213315	330	0	0
StayInStableSt	5213315	12454	0	0
gen_high_level_sva.HighLevelEvent_A	5213315	4542260	0	0
gen_not_sticky_sva.StableStDropOut_A	5213315	305	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	842	0	0
T2	16218	2	0	0
T3	0	7	0	0
T7	0	12	0	0
T10	0	21	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	8	0	0
T24	492	0	0	0
T26	0	6	0	0
T31	0	18	0	0
T46	0	4	0	0
T47	506	0	0	0
T53	0	27	0	0
T108	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	48622	0	0
T2	16218	59	0	0
T3	0	174	0	0
T7	0	868	0	0
T10	0	1583	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	153	0	0
T24	492	0	0	0
T26	0	447	0	0
T31	0	1406	0	0
T46	0	136	0	0
T47	506	0	0	0
T53	0	1576	0	0
T108	0	218	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4539119	0	0
T1	1309	908	0	0
T2	16218	15790	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	60	0	0
T31	23836	3	0	0
T57	1475	0	0	0
T58	721	0	0	0
T82	0	9	0	0
T88	0	3	0	0
T90	0	4	0	0
T109	678	0	0	0
T145	0	5	0	0
T184	0	9	0	0
T242	0	8	0	0
T256	0	3	0	0
T257	0	2	0	0
T258	0	6	0	0
T259	498	0	0	0
T260	421	0	0	0
T261	402	0	0	0
T262	564	0	0	0
T263	2250	0	0	0
T264	530	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	12806	0	0
T2	16218	74	0	0
T3	0	260	0	0
T7	0	312	0	0
T10	0	415	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	92	0	0
T24	492	0	0	0
T26	0	39	0	0
T31	0	195	0	0
T46	0	132	0	0
T47	506	0	0	0
T53	0	425	0	0
T108	0	127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	330	0	0
T2	16218	1	0	0
T3	0	3	0	0
T7	0	5	0	0
T10	0	10	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	0	3	0	0
T31	0	4	0	0
T46	0	2	0	0
T47	506	0	0	0
T53	0	13	0	0
T108	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4191663	0	0
T1	1309	908	0	0
T2	16218	15388	0	0
T5	421	20	0	0
T6	649	248	0	0
T13	735	334	0	0
T14	429	28	0	0
T15	521	120	0	0
T16	539	138	0	0
T17	1571	369	0	0
T18	557	156	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4193372	0	0
T1	1309	909	0	0
T2	16218	15391	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	448	0	0
T2	16218	1	0	0
T3	0	4	0	0
T7	0	7	0	0
T10	0	11	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	5	0	0
T24	492	0	0	0
T26	0	3	0	0
T31	0	11	0	0
T46	0	2	0	0
T47	506	0	0	0
T53	0	14	0	0
T108	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	396	0	0
T2	16218	1	0	0
T3	0	3	0	0
T7	0	5	0	0
T10	0	10	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	3	0	0
T24	492	0	0	0
T26	0	3	0	0
T31	0	7	0	0
T46	0	2	0	0
T47	506	0	0	0
T53	0	13	0	0
T108	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	330	0	0
T2	16218	1	0	0
T3	0	3	0	0
T7	0	5	0	0
T10	0	10	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	0	3	0	0
T31	0	4	0	0
T46	0	2	0	0
T47	506	0	0	0
T53	0	13	0	0
T108	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	330	0	0
T2	16218	1	0	0
T3	0	3	0	0
T7	0	5	0	0
T10	0	10	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	1	0	0
T24	492	0	0	0
T26	0	3	0	0
T31	0	4	0	0
T46	0	2	0	0
T47	506	0	0	0
T53	0	13	0	0
T108	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	12454	0	0
T2	16218	73	0	0
T3	0	254	0	0
T7	0	307	0	0
T10	0	405	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	91	0	0
T24	492	0	0	0
T26	0	36	0	0
T31	0	191	0	0
T46	0	128	0	0
T47	506	0	0	0
T53	0	412	0	0
T108	0	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	4542260	0	0
T1	1309	909	0	0
T2	16218	15796	0	0
T5	421	21	0	0
T6	649	249	0	0
T13	735	335	0	0
T14	429	29	0	0
T15	521	121	0	0
T16	539	139	0	0
T17	1571	371	0	0
T18	557	157	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5213315	305	0	0
T2	16218	1	0	0
T7	0	5	0	0
T10	0	10	0	0
T13	735	0	0	0
T14	429	0	0	0
T15	521	0	0	0
T16	539	0	0	0
T17	1571	0	0	0
T18	557	0	0	0
T19	6345	0	0	0
T24	492	0	0	0
T26	0	3	0	0
T31	0	4	0	0
T32	0	1	0	0
T47	506	0	0	0
T53	0	13	0	0
T83	0	3	0	0
T108	0	2	0	0
T250	0	1	0	0