Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1077305136	10067	0	0
auto_block_debounce_ctl_rd_A	1077305136	1960	0	0
auto_block_out_ctl_rd_A	1077305136	3056	0	0
com_det_ctl_0_rd_A	1077305136	3434	0	0
com_det_ctl_1_rd_A	1077305136	3350	0	0
com_det_ctl_2_rd_A	1077305136	3360	0	0
com_det_ctl_3_rd_A	1077305136	3402	0	0
com_out_ctl_0_rd_A	1077305136	4139	0	0
com_out_ctl_1_rd_A	1077305136	4345	0	0
com_out_ctl_2_rd_A	1077305136	4062	0	0
com_out_ctl_3_rd_A	1077305136	4365	0	0
com_pre_det_ctl_0_rd_A	1077305136	1413	0	0
com_pre_det_ctl_1_rd_A	1077305136	1596	0	0
com_pre_det_ctl_2_rd_A	1077305136	1459	0	0
com_pre_det_ctl_3_rd_A	1077305136	1589	0	0
com_pre_sel_ctl_0_rd_A	1077305136	4390	0	0
com_pre_sel_ctl_1_rd_A	1077305136	4506	0	0
com_pre_sel_ctl_2_rd_A	1077305136	4615	0	0
com_pre_sel_ctl_3_rd_A	1077305136	4805	0	0
com_sel_ctl_0_rd_A	1077305136	4484	0	0
com_sel_ctl_1_rd_A	1077305136	4615	0	0
com_sel_ctl_2_rd_A	1077305136	4336	0	0
com_sel_ctl_3_rd_A	1077305136	4976	0	0
ec_rst_ctl_rd_A	1077305136	2376	0	0
intr_enable_rd_A	1077305136	1996	0	0
key_intr_ctl_rd_A	1077305136	5070	0	0
key_intr_debounce_ctl_rd_A	1077305136	1593	0	0
key_invert_ctl_rd_A	1077305136	7720	0	0
pin_allowed_ctl_rd_A	1077305136	9210	0	0
pin_out_ctl_rd_A	1077305136	5959	0	0
pin_out_value_rd_A	1077305136	5426	0	0
regwen_rd_A	1077305136	1593	0	0
ulp_ac_debounce_ctl_rd_A	1077305136	1710	0	0
ulp_ctl_rd_A	1077305136	1624	0	0
ulp_lid_debounce_ctl_rd_A	1077305136	1556	0	0
ulp_pwrb_debounce_ctl_rd_A	1077305136	1524	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	10067	0	0
T9	106189	9	0	0
T10	281652	8	0	0
T11	31435	0	0	0
T12	0	4	0	0
T25	44192	0	0	0
T32	0	13	0	0
T37	0	24	0	0
T38	223773	0	0	0
T39	677452	0	0	0
T40	313784	0	0	0
T41	233537	0	0	0
T44	0	3	0	0
T54	0	6	0	0
T59	246990	0	0	0
T60	41949	0	0	0
T83	0	10	0	0
T250	0	13	0	0
T291	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1960	0	0
T12	923281	3	0	0
T30	139838	0	0	0
T32	0	36	0	0
T44	0	28	0	0
T61	238470	0	0	0
T84	0	35	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	16	0	0
T291	0	19	0	0
T292	0	8	0	0
T293	0	6	0	0
T294	0	14	0	0
T295	0	13	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	3056	0	0
T12	923281	7	0	0
T30	139838	0	0	0
T32	0	51	0	0
T42	364996	3	0	0
T43	122947	0	0	0
T44	0	18	0	0
T84	0	29	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T183	0	15	0	0
T291	0	27	0	0
T292	0	3	0	0
T293	0	8	0	0
T294	0	4	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	3434	0	0
T12	923281	7	0	0
T32	0	45	0	0
T38	223773	15	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	18	0	0
T60	41949	0	0	0
T81	0	49	0	0
T82	0	75	0	0
T108	0	57	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	38	0	0
T240	0	24	0	0
T291	0	10	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	3350	0	0
T12	923281	8	0	0
T32	0	39	0	0
T38	223773	25	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	6	0	0
T60	41949	0	0	0
T81	0	57	0	0
T82	0	53	0	0
T108	0	65	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	31	0	0
T240	0	51	0	0
T291	0	21	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	3360	0	0
T12	923281	8	0	0
T32	0	22	0	0
T38	223773	31	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	5	0	0
T60	41949	0	0	0
T81	0	39	0	0
T82	0	74	0	0
T108	0	83	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	23	0	0
T240	0	61	0	0
T291	0	21	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	3402	0	0
T12	923281	8	0	0
T32	0	26	0	0
T38	223773	35	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	5	0	0
T60	41949	0	0	0
T81	0	45	0	0
T82	0	76	0	0
T108	0	77	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	25	0	0
T240	0	43	0	0
T291	0	21	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4139	0	0
T12	923281	7	0	0
T32	0	43	0	0
T38	223773	33	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	8	0	0
T60	41949	0	0	0
T81	0	53	0	0
T82	0	78	0	0
T108	0	72	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	23	0	0
T240	0	36	0	0
T291	0	19	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4345	0	0
T12	923281	2	0	0
T32	0	36	0	0
T38	223773	20	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	12	0	0
T60	41949	0	0	0
T81	0	54	0	0
T82	0	71	0	0
T108	0	65	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	49	0	0
T240	0	56	0	0
T291	0	20	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4062	0	0
T12	923281	8	0	0
T32	0	40	0	0
T38	223773	17	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	5	0	0
T60	41949	0	0	0
T81	0	42	0	0
T82	0	82	0	0
T108	0	49	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	51	0	0
T240	0	19	0	0
T291	0	29	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4365	0	0
T12	923281	1	0	0
T32	0	27	0	0
T38	223773	41	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	12	0	0
T60	41949	0	0	0
T81	0	43	0	0
T82	0	83	0	0
T108	0	72	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	18	0	0
T240	0	25	0	0
T291	0	21	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1413	0	0
T12	923281	6	0	0
T30	139838	0	0	0
T32	0	39	0	0
T44	0	8	0	0
T61	238470	0	0	0
T90	0	15	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	15	0	0
T202	0	16	0	0
T227	0	25	0	0
T291	0	23	0	0
T296	0	9	0	0
T297	0	52	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1596	0	0
T12	923281	8	0	0
T30	139838	0	0	0
T32	0	23	0	0
T44	0	2	0	0
T61	238470	0	0	0
T74	0	2	0	0
T90	0	35	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	14	0	0
T202	0	16	0	0
T227	0	17	0	0
T291	0	17	0	0
T296	0	6	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1459	0	0
T12	923281	5	0	0
T30	139838	0	0	0
T32	0	35	0	0
T61	238470	0	0	0
T90	0	15	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	5	0	0
T202	0	23	0	0
T227	0	3	0	0
T291	0	8	0	0
T296	0	14	0	0
T297	0	26	0	0
T298	0	3	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1589	0	0
T12	923281	5	0	0
T30	139838	0	0	0
T32	0	35	0	0
T44	0	1	0	0
T61	238470	0	0	0
T74	0	6	0	0
T90	0	26	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	8	0	0
T202	0	23	0	0
T227	0	28	0	0
T291	0	7	0	0
T297	0	32	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4390	0	0
T12	923281	5	0	0
T32	0	38	0	0
T38	223773	43	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	7	0	0
T60	41949	0	0	0
T81	0	42	0	0
T82	0	69	0	0
T108	0	59	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	20	0	0
T240	0	35	0	0
T291	0	23	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4506	0	0
T12	923281	8	0	0
T32	0	39	0	0
T38	223773	36	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	1	0	0
T60	41949	0	0	0
T81	0	43	0	0
T82	0	73	0	0
T108	0	54	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	30	0	0
T240	0	29	0	0
T291	0	33	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4615	0	0
T12	923281	8	0	0
T32	0	38	0	0
T38	223773	34	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	4	0	0
T60	41949	0	0	0
T81	0	54	0	0
T82	0	80	0	0
T108	0	84	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	9	0	0
T240	0	34	0	0
T291	0	17	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4805	0	0
T12	923281	14	0	0
T32	0	37	0	0
T38	223773	33	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	8	0	0
T60	41949	0	0	0
T81	0	48	0	0
T82	0	88	0	0
T108	0	67	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	47	0	0
T240	0	43	0	0
T291	0	9	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4484	0	0
T12	923281	2	0	0
T32	0	38	0	0
T38	223773	32	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T60	41949	0	0	0
T81	0	44	0	0
T82	0	70	0	0
T108	0	68	0	0
T124	0	42	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	33	0	0
T240	0	48	0	0
T291	0	24	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4615	0	0
T12	923281	3	0	0
T32	0	47	0	0
T38	223773	28	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	12	0	0
T60	41949	0	0	0
T81	0	43	0	0
T82	0	99	0	0
T108	0	68	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	53	0	0
T240	0	44	0	0
T291	0	35	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4336	0	0
T12	923281	15	0	0
T32	0	45	0	0
T38	223773	6	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	6	0	0
T60	41949	0	0	0
T81	0	50	0	0
T82	0	68	0	0
T108	0	79	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	33	0	0
T240	0	45	0	0
T291	0	28	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	4976	0	0
T12	923281	0	0	0
T32	0	20	0	0
T38	223773	40	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	8	0	0
T60	41949	0	0	0
T81	0	30	0	0
T82	0	92	0	0
T108	0	61	0	0
T124	0	40	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T238	0	33	0	0
T240	0	40	0	0
T291	0	33	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	2376	0	0
T12	923281	22	0	0
T32	0	48	0	0
T38	223773	8	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	10	0	0
T60	41949	0	0	0
T81	0	15	0	0
T82	0	46	0	0
T97	0	9	0	0
T108	0	19	0	0
T136	0	3	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T178	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1996	0	0
T12	923281	6	0	0
T30	139838	0	0	0
T32	0	45	0	0
T44	0	5	0	0
T61	238470	0	0	0
T74	0	14	0	0
T90	0	63	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	42	0	0
T227	0	27	0	0
T291	0	10	0	0
T296	0	20	0	0
T299	0	26	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	5070	0	0
T12	923281	12	0	0
T30	139838	0	0	0
T32	0	27	0	0
T44	0	5	0	0
T61	238470	0	0	0
T67	0	3	0	0
T140	0	9	0	0
T143	0	2	0	0
T152	0	4	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T182	0	5	0	0
T188	0	8	0	0
T291	0	38	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1593	0	0
T12	923281	9	0	0
T30	139838	0	0	0
T32	0	26	0	0
T44	0	2	0	0
T61	238470	0	0	0
T90	0	31	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	13	0	0
T202	0	18	0	0
T227	0	17	0	0
T291	0	6	0	0
T296	0	4	0	0
T297	0	29	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	7720	0	0
T12	923281	72	0	0
T32	0	151	0	0
T41	233537	0	0	0
T42	364996	0	0	0
T43	122947	0	0	0
T44	0	137	0	0
T60	41949	39	0	0
T61	0	43	0	0
T95	0	63	0	0
T153	55272	0	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T183	0	107	0	0
T291	0	109	0	0
T300	0	68	0	0
T301	0	64	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	9210	0	0
T12	923281	7	0	0
T30	139838	0	0	0
T32	0	224	0	0
T44	0	58	0	0
T61	238470	0	0	0
T84	0	82	0	0
T135	0	62	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	46	0	0
T200	0	60	0	0
T291	0	213	0	0
T302	0	41	0	0
T303	0	38	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	5959	0	0
T12	923281	7	0	0
T30	139838	0	0	0
T32	0	262	0	0
T44	0	39	0	0
T61	238470	0	0	0
T84	0	80	0	0
T135	0	86	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	74	0	0
T200	0	53	0	0
T291	0	181	0	0
T302	0	23	0	0
T303	0	45	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	5426	0	0
T12	923281	5	0	0
T30	139838	0	0	0
T32	0	226	0	0
T44	0	48	0	0
T61	238470	0	0	0
T84	0	66	0	0
T135	0	70	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	71	0	0
T200	0	79	0	0
T291	0	227	0	0
T302	0	38	0	0
T303	0	48	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1593	0	0
T12	923281	9	0	0
T30	139838	0	0	0
T32	0	27	0	0
T44	0	9	0	0
T61	238470	0	0	0
T74	0	9	0	0
T90	0	20	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	4	0	0
T202	0	29	0	0
T227	0	13	0	0
T291	0	5	0	0
T296	0	10	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1710	0	0
T12	923281	18	0	0
T30	139838	0	0	0
T32	0	30	0	0
T44	0	12	0	0
T61	238470	0	0	0
T65	0	7	0	0
T67	0	4	0	0
T123	0	2	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	10	0	0
T214	0	4	0	0
T291	0	25	0	0
T304	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1624	0	0
T12	923281	7	0	0
T30	139838	0	0	0
T32	0	27	0	0
T44	0	12	0	0
T61	238470	0	0	0
T65	0	1	0	0
T67	0	6	0	0
T123	0	9	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	26	0	0
T214	0	6	0	0
T291	0	14	0	0
T304	0	9	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1556	0	0
T12	923281	13	0	0
T30	139838	0	0	0
T32	0	54	0	0
T44	0	11	0	0
T61	238470	0	0	0
T65	0	4	0	0
T67	0	8	0	0
T123	0	9	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	8	0	0
T214	0	2	0	0
T291	0	16	0	0
T296	0	18	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1077305136	1524	0	0
T12	923281	3	0	0
T30	139838	0	0	0
T32	0	50	0	0
T44	0	5	0	0
T61	238470	0	0	0
T65	0	3	0	0
T67	0	8	0	0
T123	0	6	0	0
T169	202650	0	0	0
T170	99567	0	0	0
T171	204191	0	0	0
T172	204951	0	0	0
T173	60852	0	0	0
T174	248799	0	0	0
T175	48951	0	0	0
T183	0	11	0	0
T214	0	2	0	0
T291	0	7	0	0
T296	0	17	0	0