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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.44 96.78 100.00 98.72 98.89 99.61 92.13


Total test records in report: 907
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T87 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.14940270 Jul 05 05:09:49 PM PDT 24 Jul 05 05:10:32 PM PDT 24 22202474994 ps
T302 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1778125049 Jul 05 05:09:34 PM PDT 24 Jul 05 05:09:37 PM PDT 24 2104668845 ps
T20 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3394373535 Jul 05 05:09:39 PM PDT 24 Jul 05 05:09:43 PM PDT 24 8527405068 ps
T91 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4221145330 Jul 05 05:08:39 PM PDT 24 Jul 05 05:08:43 PM PDT 24 2270814021 ps
T92 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2783983760 Jul 05 05:09:55 PM PDT 24 Jul 05 05:10:01 PM PDT 24 2148574166 ps
T323 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2687083097 Jul 05 05:09:08 PM PDT 24 Jul 05 05:09:12 PM PDT 24 2038947087 ps
T99 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2413969977 Jul 05 05:09:47 PM PDT 24 Jul 05 05:09:55 PM PDT 24 2043633024 ps
T90 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2308852520 Jul 05 05:09:39 PM PDT 24 Jul 05 05:10:01 PM PDT 24 43169995564 ps
T94 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3717472885 Jul 05 05:09:34 PM PDT 24 Jul 05 05:09:39 PM PDT 24 2077135414 ps
T365 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.4224904413 Jul 05 05:09:01 PM PDT 24 Jul 05 05:09:03 PM PDT 24 2478813994 ps
T21 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.327579778 Jul 05 05:09:40 PM PDT 24 Jul 05 05:09:49 PM PDT 24 10113196540 ps
T303 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1543681186 Jul 05 05:08:52 PM PDT 24 Jul 05 05:08:58 PM PDT 24 4019123803 ps
T318 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.722930227 Jul 05 05:09:15 PM PDT 24 Jul 05 05:09:20 PM PDT 24 5256538799 ps
T319 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1336162739 Jul 05 05:09:34 PM PDT 24 Jul 05 05:09:41 PM PDT 24 2031426301 ps
T100 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3842614279 Jul 05 05:09:20 PM PDT 24 Jul 05 05:09:25 PM PDT 24 2216734133 ps
T367 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3008011941 Jul 05 05:09:13 PM PDT 24 Jul 05 05:09:16 PM PDT 24 2109712276 ps
T304 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.730264730 Jul 05 05:08:51 PM PDT 24 Jul 05 05:08:57 PM PDT 24 3000241944 ps
T791 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1398112552 Jul 05 05:10:10 PM PDT 24 Jul 05 05:10:13 PM PDT 24 2028916575 ps
T792 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.492841199 Jul 05 05:09:16 PM PDT 24 Jul 05 05:09:23 PM PDT 24 2015053730 ps
T793 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1357564595 Jul 05 05:09:33 PM PDT 24 Jul 05 05:09:36 PM PDT 24 3004880040 ps
T794 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.719380517 Jul 05 05:09:57 PM PDT 24 Jul 05 05:10:01 PM PDT 24 2135248603 ps
T795 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2345024405 Jul 05 05:09:34 PM PDT 24 Jul 05 05:09:37 PM PDT 24 2125831934 ps
T796 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1542832398 Jul 05 05:10:23 PM PDT 24 Jul 05 05:10:29 PM PDT 24 2011586854 ps
T797 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3460648963 Jul 05 05:10:19 PM PDT 24 Jul 05 05:10:21 PM PDT 24 2095645386 ps
T798 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.491094616 Jul 05 05:09:49 PM PDT 24 Jul 05 05:09:55 PM PDT 24 2014383186 ps
T320 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2381199486 Jul 05 05:09:27 PM PDT 24 Jul 05 05:09:34 PM PDT 24 2046402701 ps
T305 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.383952773 Jul 05 05:10:06 PM PDT 24 Jul 05 05:10:09 PM PDT 24 2060308761 ps
T306 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3473358770 Jul 05 05:09:02 PM PDT 24 Jul 05 05:09:11 PM PDT 24 6037328181 ps
T321 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1906181233 Jul 05 05:08:44 PM PDT 24 Jul 05 05:08:51 PM PDT 24 2026765741 ps
T341 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2847816276 Jul 05 05:10:04 PM PDT 24 Jul 05 05:10:34 PM PDT 24 42808862518 ps
T322 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2112379424 Jul 05 05:08:46 PM PDT 24 Jul 05 05:08:58 PM PDT 24 4897499003 ps
T799 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.811295942 Jul 05 05:10:16 PM PDT 24 Jul 05 05:10:20 PM PDT 24 2024273078 ps
T366 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2639390961 Jul 05 05:08:46 PM PDT 24 Jul 05 05:08:49 PM PDT 24 2075849852 ps
T800 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.181136163 Jul 05 05:09:56 PM PDT 24 Jul 05 05:10:04 PM PDT 24 2034192426 ps
T801 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1337975622 Jul 05 05:10:03 PM PDT 24 Jul 05 05:10:10 PM PDT 24 2101663589 ps
T802 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.4072811496 Jul 05 05:10:18 PM PDT 24 Jul 05 05:10:24 PM PDT 24 2010933942 ps
T803 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3420121468 Jul 05 05:10:06 PM PDT 24 Jul 05 05:10:38 PM PDT 24 9881795325 ps
T804 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.4108490025 Jul 05 05:09:58 PM PDT 24 Jul 05 05:10:21 PM PDT 24 9305050541 ps
T805 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.581143145 Jul 05 05:09:51 PM PDT 24 Jul 05 05:09:58 PM PDT 24 2013278060 ps
T344 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3967193254 Jul 05 05:09:49 PM PDT 24 Jul 05 05:10:48 PM PDT 24 22237572913 ps
T95 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4272666032 Jul 05 05:09:41 PM PDT 24 Jul 05 05:09:46 PM PDT 24 2637164043 ps
T806 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1271211276 Jul 05 05:08:59 PM PDT 24 Jul 05 05:09:10 PM PDT 24 5079070345 ps
T807 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.342922921 Jul 05 05:10:03 PM PDT 24 Jul 05 05:10:07 PM PDT 24 2020473458 ps
T307 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1481181323 Jul 05 05:09:05 PM PDT 24 Jul 05 05:09:13 PM PDT 24 4028620443 ps
T808 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2190360284 Jul 05 05:09:55 PM PDT 24 Jul 05 05:10:02 PM PDT 24 2013974128 ps
T809 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1085584789 Jul 05 05:08:51 PM PDT 24 Jul 05 05:08:55 PM PDT 24 2143775638 ps
T810 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1060193522 Jul 05 05:09:02 PM PDT 24 Jul 05 05:09:06 PM PDT 24 2018425676 ps
T811 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.639883961 Jul 05 05:09:48 PM PDT 24 Jul 05 05:09:57 PM PDT 24 2049102068 ps
T812 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3251913168 Jul 05 05:09:56 PM PDT 24 Jul 05 05:10:06 PM PDT 24 7532669679 ps
T813 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4154558319 Jul 05 05:10:13 PM PDT 24 Jul 05 05:10:15 PM PDT 24 2028481710 ps
T308 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2050679686 Jul 05 05:09:19 PM PDT 24 Jul 05 05:11:12 PM PDT 24 49352785628 ps
T814 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.697873455 Jul 05 05:09:57 PM PDT 24 Jul 05 05:10:00 PM PDT 24 2130250894 ps
T815 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1340763331 Jul 05 05:09:08 PM PDT 24 Jul 05 05:09:12 PM PDT 24 2018895575 ps
T816 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3947694654 Jul 05 05:09:19 PM PDT 24 Jul 05 05:09:23 PM PDT 24 2046084079 ps
T817 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1961232188 Jul 05 05:09:10 PM PDT 24 Jul 05 05:09:14 PM PDT 24 2167719955 ps
T818 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1590718401 Jul 05 05:10:16 PM PDT 24 Jul 05 05:10:19 PM PDT 24 2032458126 ps
T819 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.68731552 Jul 05 05:08:46 PM PDT 24 Jul 05 05:08:51 PM PDT 24 2058219773 ps
T820 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2183424134 Jul 05 05:10:10 PM PDT 24 Jul 05 05:10:16 PM PDT 24 2016333822 ps
T309 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.279153147 Jul 05 05:08:46 PM PDT 24 Jul 05 05:08:51 PM PDT 24 3172435747 ps
T821 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1678916717 Jul 05 05:09:29 PM PDT 24 Jul 05 05:09:39 PM PDT 24 7693918007 ps
T822 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.415524837 Jul 05 05:09:49 PM PDT 24 Jul 05 05:09:52 PM PDT 24 2073700762 ps
T823 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2969048211 Jul 05 05:09:27 PM PDT 24 Jul 05 05:09:31 PM PDT 24 2237799425 ps
T824 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2979822674 Jul 05 05:10:25 PM PDT 24 Jul 05 05:10:28 PM PDT 24 2021195438 ps
T324 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3992372144 Jul 05 05:08:47 PM PDT 24 Jul 05 05:09:05 PM PDT 24 6053042023 ps
T825 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2729325417 Jul 05 05:09:01 PM PDT 24 Jul 05 05:09:07 PM PDT 24 3466993546 ps
T342 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.818737409 Jul 05 05:09:16 PM PDT 24 Jul 05 05:10:14 PM PDT 24 22233435143 ps
T826 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1482176955 Jul 05 05:09:01 PM PDT 24 Jul 05 05:09:04 PM PDT 24 2040692255 ps
T827 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.903067968 Jul 05 05:10:24 PM PDT 24 Jul 05 05:10:33 PM PDT 24 4692722056 ps
T828 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2534800551 Jul 05 05:09:55 PM PDT 24 Jul 05 05:09:59 PM PDT 24 2023383103 ps
T310 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2895320138 Jul 05 05:09:33 PM PDT 24 Jul 05 05:09:36 PM PDT 24 2056557841 ps
T829 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.151719422 Jul 05 05:10:13 PM PDT 24 Jul 05 05:10:17 PM PDT 24 2022615224 ps
T830 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.4227159943 Jul 05 05:10:06 PM PDT 24 Jul 05 05:10:12 PM PDT 24 2011807921 ps
T831 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2209844072 Jul 05 05:08:59 PM PDT 24 Jul 05 05:09:10 PM PDT 24 22772948982 ps
T832 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1507576946 Jul 05 05:10:02 PM PDT 24 Jul 05 05:10:09 PM PDT 24 2009874981 ps
T311 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3794092343 Jul 05 05:09:50 PM PDT 24 Jul 05 05:09:57 PM PDT 24 2050660788 ps
T833 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2873010955 Jul 05 05:09:31 PM PDT 24 Jul 05 05:09:38 PM PDT 24 2048022744 ps
T834 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3498491172 Jul 05 05:08:51 PM PDT 24 Jul 05 05:08:57 PM PDT 24 2032383815 ps
T835 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.577346933 Jul 05 05:09:56 PM PDT 24 Jul 05 05:10:13 PM PDT 24 22452943131 ps
T836 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.146077065 Jul 05 05:09:35 PM PDT 24 Jul 05 05:09:42 PM PDT 24 2109833675 ps
T837 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.246415182 Jul 05 05:10:04 PM PDT 24 Jul 05 05:10:11 PM PDT 24 7252972987 ps
T838 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2756620635 Jul 05 05:10:16 PM PDT 24 Jul 05 05:10:22 PM PDT 24 2012624956 ps
T312 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.736220304 Jul 05 05:09:40 PM PDT 24 Jul 05 05:09:47 PM PDT 24 2056656466 ps
T839 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.999902112 Jul 05 05:08:52 PM PDT 24 Jul 05 05:08:55 PM PDT 24 2179850527 ps
T313 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1804454548 Jul 05 05:09:48 PM PDT 24 Jul 05 05:09:51 PM PDT 24 2072290585 ps
T840 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3355914715 Jul 05 05:09:07 PM PDT 24 Jul 05 05:10:08 PM PDT 24 39685919170 ps
T841 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.4100464389 Jul 05 05:09:49 PM PDT 24 Jul 05 05:11:17 PM PDT 24 42423592142 ps
T842 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.706936790 Jul 05 05:10:05 PM PDT 24 Jul 05 05:10:12 PM PDT 24 2012619916 ps
T843 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.170130274 Jul 05 05:09:48 PM PDT 24 Jul 05 05:09:57 PM PDT 24 9666672262 ps
T844 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1186173549 Jul 05 05:09:31 PM PDT 24 Jul 05 05:09:37 PM PDT 24 2011377681 ps
T314 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1607320127 Jul 05 05:10:05 PM PDT 24 Jul 05 05:10:08 PM PDT 24 2079720663 ps
T845 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.375712022 Jul 05 05:09:55 PM PDT 24 Jul 05 05:09:58 PM PDT 24 2021091107 ps
T846 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3869974019 Jul 05 05:10:04 PM PDT 24 Jul 05 05:10:11 PM PDT 24 2088755418 ps
T847 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2497833615 Jul 05 05:10:10 PM PDT 24 Jul 05 05:10:13 PM PDT 24 2041962893 ps
T848 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3460116290 Jul 05 05:09:30 PM PDT 24 Jul 05 05:10:00 PM PDT 24 22199495313 ps
T343 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1477041446 Jul 05 05:10:03 PM PDT 24 Jul 05 05:10:20 PM PDT 24 43498214085 ps
T849 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3354009154 Jul 05 05:09:55 PM PDT 24 Jul 05 05:10:44 PM PDT 24 22208419809 ps
T850 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2872852436 Jul 05 05:09:40 PM PDT 24 Jul 05 05:09:47 PM PDT 24 2088746059 ps
T851 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3427307260 Jul 05 05:10:21 PM PDT 24 Jul 05 05:10:27 PM PDT 24 2011428223 ps
T852 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1066468521 Jul 05 05:09:56 PM PDT 24 Jul 05 05:10:00 PM PDT 24 2165135098 ps
T853 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2572765041 Jul 05 05:09:06 PM PDT 24 Jul 05 05:09:18 PM PDT 24 22655548080 ps
T854 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2948661906 Jul 05 05:10:02 PM PDT 24 Jul 05 05:10:07 PM PDT 24 2124979068 ps
T855 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1003819573 Jul 05 05:09:14 PM PDT 24 Jul 05 05:09:22 PM PDT 24 2117796572 ps
T856 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2029536489 Jul 05 05:08:51 PM PDT 24 Jul 05 05:10:33 PM PDT 24 42644961476 ps
T857 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.766078592 Jul 05 05:10:12 PM PDT 24 Jul 05 05:10:16 PM PDT 24 2020142463 ps
T858 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2605690637 Jul 05 05:09:21 PM PDT 24 Jul 05 05:09:25 PM PDT 24 4036120084 ps
T859 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2980097198 Jul 05 05:10:22 PM PDT 24 Jul 05 05:10:25 PM PDT 24 2032976785 ps
T860 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1351614332 Jul 05 05:10:02 PM PDT 24 Jul 05 05:10:09 PM PDT 24 2038882981 ps
T861 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3555934658 Jul 05 05:09:34 PM PDT 24 Jul 05 05:10:06 PM PDT 24 42917370196 ps
T862 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.347738437 Jul 05 05:10:11 PM PDT 24 Jul 05 05:10:14 PM PDT 24 2031344070 ps
T863 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3051523160 Jul 05 05:09:30 PM PDT 24 Jul 05 05:09:33 PM PDT 24 2051526388 ps
T864 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.573770734 Jul 05 05:09:50 PM PDT 24 Jul 05 05:09:54 PM PDT 24 2046191354 ps
T865 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.781335122 Jul 05 05:10:01 PM PDT 24 Jul 05 05:10:19 PM PDT 24 22391914017 ps
T866 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1147330795 Jul 05 05:10:11 PM PDT 24 Jul 05 05:10:13 PM PDT 24 2049888568 ps
T867 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3571337371 Jul 05 05:09:39 PM PDT 24 Jul 05 05:10:26 PM PDT 24 42687820581 ps
T868 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2028286832 Jul 05 05:10:21 PM PDT 24 Jul 05 05:10:28 PM PDT 24 2016578136 ps
T869 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1995192959 Jul 05 05:09:56 PM PDT 24 Jul 05 05:10:00 PM PDT 24 2215631650 ps
T870 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1730519917 Jul 05 05:10:01 PM PDT 24 Jul 05 05:10:05 PM PDT 24 2264142675 ps
T871 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1259249223 Jul 05 05:10:11 PM PDT 24 Jul 05 05:10:15 PM PDT 24 2030590832 ps
T872 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3228829872 Jul 05 05:09:59 PM PDT 24 Jul 05 05:10:06 PM PDT 24 2012162431 ps
T873 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2388237268 Jul 05 05:09:53 PM PDT 24 Jul 05 05:10:01 PM PDT 24 2109024779 ps
T874 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.652512137 Jul 05 05:09:26 PM PDT 24 Jul 05 05:09:28 PM PDT 24 2071177274 ps
T875 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3584040718 Jul 05 05:09:28 PM PDT 24 Jul 05 05:09:31 PM PDT 24 2150866628 ps
T876 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2101572518 Jul 05 05:08:46 PM PDT 24 Jul 05 05:09:41 PM PDT 24 22184268742 ps
T315 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1071588816 Jul 05 05:09:20 PM PDT 24 Jul 05 05:10:34 PM PDT 24 39814286520 ps
T877 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2835771489 Jul 05 05:09:25 PM PDT 24 Jul 05 05:09:46 PM PDT 24 8542288751 ps
T878 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2309945873 Jul 05 05:09:26 PM PDT 24 Jul 05 05:09:28 PM PDT 24 2101150120 ps
T879 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1969708936 Jul 05 05:08:52 PM PDT 24 Jul 05 05:08:57 PM PDT 24 4366116256 ps
T316 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3524832457 Jul 05 05:09:09 PM PDT 24 Jul 05 05:09:14 PM PDT 24 2707058823 ps
T880 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.732054660 Jul 05 05:09:55 PM PDT 24 Jul 05 05:10:03 PM PDT 24 2012760301 ps
T881 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.933590983 Jul 05 05:09:26 PM PDT 24 Jul 05 05:09:30 PM PDT 24 2045546192 ps
T882 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2854583710 Jul 05 05:08:51 PM PDT 24 Jul 05 05:09:44 PM PDT 24 39352043760 ps
T883 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.79801995 Jul 05 05:09:26 PM PDT 24 Jul 05 05:09:56 PM PDT 24 22207708251 ps
T884 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2847174777 Jul 05 05:10:53 PM PDT 24 Jul 05 05:10:56 PM PDT 24 2028882154 ps
T885 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2894112930 Jul 05 05:10:10 PM PDT 24 Jul 05 05:10:15 PM PDT 24 2015849446 ps
T886 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2510460268 Jul 05 05:10:12 PM PDT 24 Jul 05 05:10:18 PM PDT 24 2011621873 ps
T887 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3367993625 Jul 05 05:10:16 PM PDT 24 Jul 05 05:10:19 PM PDT 24 2026837872 ps
T888 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.4150382377 Jul 05 05:10:23 PM PDT 24 Jul 05 05:10:29 PM PDT 24 2015047545 ps
T889 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.20193695 Jul 05 05:09:54 PM PDT 24 Jul 05 05:10:19 PM PDT 24 10400654666 ps
T890 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.99347704 Jul 05 05:08:48 PM PDT 24 Jul 05 05:09:30 PM PDT 24 39641011767 ps
T891 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2025015611 Jul 05 05:09:55 PM PDT 24 Jul 05 05:09:58 PM PDT 24 2075532079 ps
T892 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2721167514 Jul 05 05:13:02 PM PDT 24 Jul 05 05:14:02 PM PDT 24 42579362533 ps
T893 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2326721220 Jul 05 05:10:12 PM PDT 24 Jul 05 05:10:18 PM PDT 24 2013419053 ps
T894 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3210887717 Jul 05 05:09:32 PM PDT 24 Jul 05 05:09:52 PM PDT 24 5169074402 ps
T895 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.582243061 Jul 05 05:10:26 PM PDT 24 Jul 05 05:10:29 PM PDT 24 2040462876 ps
T896 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.208015469 Jul 05 05:09:54 PM PDT 24 Jul 05 05:10:38 PM PDT 24 9401906917 ps
T897 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1458455146 Jul 05 05:09:49 PM PDT 24 Jul 05 05:09:57 PM PDT 24 2012962951 ps
T898 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1919507550 Jul 05 05:09:30 PM PDT 24 Jul 05 05:09:33 PM PDT 24 2128643709 ps
T317 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.172225879 Jul 05 05:09:20 PM PDT 24 Jul 05 05:09:30 PM PDT 24 2534674296 ps
T899 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1903225695 Jul 05 05:08:56 PM PDT 24 Jul 05 05:09:02 PM PDT 24 2012169058 ps
T900 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3683980157 Jul 05 05:09:36 PM PDT 24 Jul 05 05:09:41 PM PDT 24 2122229327 ps
T901 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.110765160 Jul 05 05:09:41 PM PDT 24 Jul 05 05:09:44 PM PDT 24 2077160113 ps
T902 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3499141924 Jul 05 05:10:11 PM PDT 24 Jul 05 05:10:17 PM PDT 24 2013530668 ps
T903 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2904128972 Jul 05 05:09:56 PM PDT 24 Jul 05 05:09:59 PM PDT 24 2031315396 ps
T904 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1738850500 Jul 05 05:09:49 PM PDT 24 Jul 05 05:09:53 PM PDT 24 4816132394 ps
T905 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1644900294 Jul 05 05:09:28 PM PDT 24 Jul 05 05:09:36 PM PDT 24 2043986851 ps
T906 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2188889687 Jul 05 05:09:19 PM PDT 24 Jul 05 05:09:29 PM PDT 24 4720621282 ps
T907 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3328230780 Jul 05 05:09:28 PM PDT 24 Jul 05 05:09:35 PM PDT 24 2053706182 ps

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3614214946
Short name T3
Test name
Test status
Simulation time 1493183761811 ps
CPU time 546.17 seconds
Started Jul 05 05:31:03 PM PDT 24
Finished Jul 05 05:40:11 PM PDT 24
Peak memory 210280 kb
Host smart-fa1beea7-ed56-4410-9fa4-ac7e66a78ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614214946 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.3614214946
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2738048353
Short name T8
Test name
Test status
Simulation time 63161431890 ps
CPU time 173.65 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:34:46 PM PDT 24
Peak memory 201936 kb
Host smart-83d55967-2369-4d9a-a2de-b1227ab957b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738048353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.2738048353
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1034441406
Short name T39
Test name
Test status
Simulation time 14404368460 ps
CPU time 17.24 seconds
Started Jul 05 05:32:07 PM PDT 24
Finished Jul 05 05:32:25 PM PDT 24
Peak memory 201640 kb
Host smart-9e26bca2-b3da-49ec-bffa-a41f896bbd93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034441406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1034441406
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.4100731456
Short name T23
Test name
Test status
Simulation time 47364515388 ps
CPU time 62.04 seconds
Started Jul 05 05:32:12 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 210320 kb
Host smart-17f57626-d9ba-4337-aa5b-24a83d7496e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100731456 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.4100731456
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.3590682243
Short name T107
Test name
Test status
Simulation time 5879978525 ps
CPU time 4.26 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:31:38 PM PDT 24
Peak memory 201692 kb
Host smart-78b58b91-d9ef-44ce-9c1a-177b671b0204
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590682243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.3590682243
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3961557910
Short name T167
Test name
Test status
Simulation time 890718523149 ps
CPU time 202.14 seconds
Started Jul 05 05:31:15 PM PDT 24
Finished Jul 05 05:34:38 PM PDT 24
Peak memory 218376 kb
Host smart-7fdbb702-6968-4a61-aeb8-498f8fc45dd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961557910 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3961557910
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.866828956
Short name T66
Test name
Test status
Simulation time 394348121788 ps
CPU time 85.47 seconds
Started Jul 05 05:31:24 PM PDT 24
Finished Jul 05 05:32:50 PM PDT 24
Peak memory 201936 kb
Host smart-94f3239b-db57-4657-8415-6b6836d244d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866828956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_st
ress_all.866828956
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.363224393
Short name T102
Test name
Test status
Simulation time 40427801922 ps
CPU time 25.44 seconds
Started Jul 05 05:30:22 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201640 kb
Host smart-1f4b22e2-da61-45cc-8a92-07cdef2c8a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363224393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.363224393
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.831653372
Short name T184
Test name
Test status
Simulation time 246651376164 ps
CPU time 71.31 seconds
Started Jul 05 05:31:53 PM PDT 24
Finished Jul 05 05:33:07 PM PDT 24
Peak memory 210280 kb
Host smart-781d8ab7-092c-49a9-9700-a2c6d019e0c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831653372 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.831653372
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.14940270
Short name T87
Test name
Test status
Simulation time 22202474994 ps
CPU time 40.7 seconds
Started Jul 05 05:09:49 PM PDT 24
Finished Jul 05 05:10:32 PM PDT 24
Peak memory 202276 kb
Host smart-e52bab48-868f-4507-a77c-e0f7783d92bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14940270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_tl_intg_err.14940270
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1197859541
Short name T31
Test name
Test status
Simulation time 146345272126 ps
CPU time 194.74 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:35:58 PM PDT 24
Peak memory 201844 kb
Host smart-cf758f83-fdaf-4909-b228-b544d93db04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197859541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.1197859541
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.4279255192
Short name T44
Test name
Test status
Simulation time 89546454807 ps
CPU time 233.89 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:35:20 PM PDT 24
Peak memory 218400 kb
Host smart-ebe9fd7a-22ca-407a-b660-8aaefb37cf60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279255192 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.4279255192
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.682281031
Short name T61
Test name
Test status
Simulation time 38111798853 ps
CPU time 49.21 seconds
Started Jul 05 05:30:27 PM PDT 24
Finished Jul 05 05:31:17 PM PDT 24
Peak memory 201648 kb
Host smart-a278fc1b-07e3-4863-bb2b-b4046528d241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682281031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.682281031
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2659770475
Short name T118
Test name
Test status
Simulation time 121625127597 ps
CPU time 20.03 seconds
Started Jul 05 05:32:01 PM PDT 24
Finished Jul 05 05:32:22 PM PDT 24
Peak memory 201760 kb
Host smart-6e9b417c-5663-42d2-81ac-f506b0b5dfd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659770475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2659770475
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2075924173
Short name T110
Test name
Test status
Simulation time 148029780872 ps
CPU time 49.71 seconds
Started Jul 05 05:35:59 PM PDT 24
Finished Jul 05 05:36:50 PM PDT 24
Peak memory 201844 kb
Host smart-954f71ad-dadc-4d0f-b11a-bddd283907cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075924173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2075924173
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3179235474
Short name T18
Test name
Test status
Simulation time 58265294144 ps
CPU time 54.68 seconds
Started Jul 05 05:31:35 PM PDT 24
Finished Jul 05 05:32:31 PM PDT 24
Peak memory 201880 kb
Host smart-151a620e-faf3-405f-9d40-9032b4fe9db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179235474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.3179235474
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2822880262
Short name T53
Test name
Test status
Simulation time 34183725685 ps
CPU time 87.25 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:33:46 PM PDT 24
Peak memory 218276 kb
Host smart-5e664e8c-c3c6-41cb-aee2-a26e4ae4b1e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822880262 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2822880262
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.264723760
Short name T83
Test name
Test status
Simulation time 6269992168 ps
CPU time 8.25 seconds
Started Jul 05 05:31:26 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201388 kb
Host smart-a4e4865b-6edf-4463-8723-ea24a7669ec9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264723760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ultra_low_pwr.264723760
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3499751154
Short name T88
Test name
Test status
Simulation time 42014121250 ps
CPU time 60.26 seconds
Started Jul 05 05:30:27 PM PDT 24
Finished Jul 05 05:31:28 PM PDT 24
Peak memory 221152 kb
Host smart-e9dd1b19-1b28-4385-9f0d-ac5d3d58f100
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499751154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.3499751154
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.995090296
Short name T206
Test name
Test status
Simulation time 273946193270 ps
CPU time 52.18 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:32:11 PM PDT 24
Peak memory 218412 kb
Host smart-8c32412c-b8fe-4e02-ae0f-a2ea335f5ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995090296 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.995090296
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3753887142
Short name T353
Test name
Test status
Simulation time 107951931303 ps
CPU time 288.08 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:36:03 PM PDT 24
Peak memory 201912 kb
Host smart-ab7a63c6-054a-45a3-9bd1-30a427f2ec71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753887142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.3753887142
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2767975249
Short name T228
Test name
Test status
Simulation time 92729949297 ps
CPU time 114.2 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:32:38 PM PDT 24
Peak memory 218392 kb
Host smart-530d2553-8034-46a1-a783-439ac12166e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767975249 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.2767975249
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3674602204
Short name T221
Test name
Test status
Simulation time 89420844900 ps
CPU time 110.45 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:34:31 PM PDT 24
Peak memory 201920 kb
Host smart-4b5eae33-cd0f-4d70-9827-9352b5091d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674602204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.3674602204
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.730264730
Short name T304
Test name
Test status
Simulation time 3000241944 ps
CPU time 5.57 seconds
Started Jul 05 05:08:51 PM PDT 24
Finished Jul 05 05:08:57 PM PDT 24
Peak memory 202296 kb
Host smart-93c391cb-1b63-4565-8b30-2536ed0b8f99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730264730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_aliasing.730264730
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2783983760
Short name T92
Test name
Test status
Simulation time 2148574166 ps
CPU time 4.16 seconds
Started Jul 05 05:09:55 PM PDT 24
Finished Jul 05 05:10:01 PM PDT 24
Peak memory 202288 kb
Host smart-9d4b573d-6048-472d-bf6d-e5f365f59a74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783983760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.2783983760
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.3100936487
Short name T165
Test name
Test status
Simulation time 2869992356 ps
CPU time 6.04 seconds
Started Jul 05 05:30:49 PM PDT 24
Finished Jul 05 05:30:55 PM PDT 24
Peak memory 201676 kb
Host smart-b78b31e4-2afb-43a3-9bf6-b9b25ff731e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100936487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.3100936487
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3797459919
Short name T101
Test name
Test status
Simulation time 142191143850 ps
CPU time 167 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:33:50 PM PDT 24
Peak memory 201856 kb
Host smart-79cd5505-f284-4d7f-9f9a-1693d45fe1cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797459919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.3797459919
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.4273282975
Short name T216
Test name
Test status
Simulation time 616225079117 ps
CPU time 68.11 seconds
Started Jul 05 05:32:20 PM PDT 24
Finished Jul 05 05:33:30 PM PDT 24
Peak memory 210296 kb
Host smart-385c210c-bd76-4f35-a881-af02579887f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273282975 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.4273282975
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.2379394999
Short name T229
Test name
Test status
Simulation time 350737553526 ps
CPU time 664.92 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:42:31 PM PDT 24
Peak memory 201912 kb
Host smart-34326d00-170d-4c45-b60f-47f485cb0645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379394999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.2379394999
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1247512054
Short name T151
Test name
Test status
Simulation time 27037916840 ps
CPU time 59.43 seconds
Started Jul 05 05:31:19 PM PDT 24
Finished Jul 05 05:32:19 PM PDT 24
Peak memory 212052 kb
Host smart-45f0db56-7e86-400a-874c-868e5563048c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247512054 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.1247512054
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3510097403
Short name T333
Test name
Test status
Simulation time 168332528167 ps
CPU time 65.11 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:32:51 PM PDT 24
Peak memory 201884 kb
Host smart-3a428901-1bb4-4098-98f2-1ebe6076f90b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510097403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3510097403
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3887002659
Short name T10
Test name
Test status
Simulation time 151317825076 ps
CPU time 37.14 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:32:29 PM PDT 24
Peak memory 201920 kb
Host smart-da7a823b-6b55-4e43-b353-a864a5e34258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887002659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.3887002659
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.947989460
Short name T328
Test name
Test status
Simulation time 127278430001 ps
CPU time 87.32 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:32:37 PM PDT 24
Peak memory 201852 kb
Host smart-b7f8a02f-89fe-4bdd-9d57-eb53261e653a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947989460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_wi
th_pre_cond.947989460
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1148444939
Short name T258
Test name
Test status
Simulation time 135901775443 ps
CPU time 78.95 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:32:34 PM PDT 24
Peak memory 214848 kb
Host smart-b2677005-cd6a-4952-bd25-724b2d57d8b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148444939 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.1148444939
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.3373489281
Short name T301
Test name
Test status
Simulation time 2037202893 ps
CPU time 1.85 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 201624 kb
Host smart-5f09c392-1a41-433c-a1d9-73235f6ad43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373489281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.3373489281
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2112379424
Short name T322
Test name
Test status
Simulation time 4897499003 ps
CPU time 11.66 seconds
Started Jul 05 05:08:46 PM PDT 24
Finished Jul 05 05:08:58 PM PDT 24
Peak memory 202292 kb
Host smart-aa0b251a-b510-426d-b050-6dba4081b5c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112379424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.2112379424
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3924552662
Short name T329
Test name
Test status
Simulation time 150685484295 ps
CPU time 395.47 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:37:54 PM PDT 24
Peak memory 201844 kb
Host smart-1ba3c737-594a-460d-abbd-05d3f0291ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924552662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.3924552662
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3717472885
Short name T94
Test name
Test status
Simulation time 2077135414 ps
CPU time 4.66 seconds
Started Jul 05 05:09:34 PM PDT 24
Finished Jul 05 05:09:39 PM PDT 24
Peak memory 202160 kb
Host smart-94da3272-b02f-4252-810f-7497ec6e08d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717472885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.3717472885
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.530526978
Short name T125
Test name
Test status
Simulation time 82195565209 ps
CPU time 208.25 seconds
Started Jul 05 05:32:00 PM PDT 24
Finished Jul 05 05:35:30 PM PDT 24
Peak memory 201852 kb
Host smart-0532ae2d-2669-4112-a382-77a3c564c7f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530526978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_combo_detect.530526978
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1807568811
Short name T734
Test name
Test status
Simulation time 187310472767 ps
CPU time 97.75 seconds
Started Jul 05 05:32:20 PM PDT 24
Finished Jul 05 05:33:59 PM PDT 24
Peak memory 201824 kb
Host smart-7195fb47-a7b4-41a1-8100-7620dba327c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807568811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1807568811
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3567966455
Short name T336
Test name
Test status
Simulation time 97834864423 ps
CPU time 62.28 seconds
Started Jul 05 05:32:42 PM PDT 24
Finished Jul 05 05:33:45 PM PDT 24
Peak memory 201864 kb
Host smart-dfe61d12-92c6-4473-af9e-1306288ee537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567966455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.3567966455
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3967193254
Short name T344
Test name
Test status
Simulation time 22237572913 ps
CPU time 57.08 seconds
Started Jul 05 05:09:49 PM PDT 24
Finished Jul 05 05:10:48 PM PDT 24
Peak memory 202272 kb
Host smart-8bf25653-5342-4da7-95b7-c0b61f2e4b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967193254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.3967193254
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.1730324586
Short name T762
Test name
Test status
Simulation time 104027191878 ps
CPU time 267.06 seconds
Started Jul 05 05:30:31 PM PDT 24
Finished Jul 05 05:34:58 PM PDT 24
Peak memory 201892 kb
Host smart-4e1b83ff-5c74-402e-b9a6-7f87c2c7530f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730324586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.1730324586
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4092356643
Short name T346
Test name
Test status
Simulation time 73002429814 ps
CPU time 189.08 seconds
Started Jul 05 05:32:11 PM PDT 24
Finished Jul 05 05:35:21 PM PDT 24
Peak memory 201788 kb
Host smart-c197e06e-a6a2-43e4-b4d4-8aa3ac44d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092356643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.4092356643
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.2662208056
Short name T180
Test name
Test status
Simulation time 15495383517 ps
CPU time 10.28 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201544 kb
Host smart-2116826c-fa78-4b1c-a038-26a8a41ee128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662208056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.2662208056
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1719261616
Short name T347
Test name
Test status
Simulation time 125320296886 ps
CPU time 159.8 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:35:17 PM PDT 24
Peak memory 201852 kb
Host smart-6095c10a-fe13-4ee8-b497-9ea8586c3a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719261616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.1719261616
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4096287901
Short name T274
Test name
Test status
Simulation time 105222543315 ps
CPU time 259.61 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:37:06 PM PDT 24
Peak memory 201924 kb
Host smart-2258348b-9043-43fd-b2cd-b26c5c030686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096287901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.4096287901
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3375966595
Short name T351
Test name
Test status
Simulation time 99346690630 ps
CPU time 59.35 seconds
Started Jul 05 05:32:46 PM PDT 24
Finished Jul 05 05:33:47 PM PDT 24
Peak memory 201816 kb
Host smart-539fc782-d705-4769-a99c-1c5afcb98e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375966595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.3375966595
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3172107413
Short name T119
Test name
Test status
Simulation time 23363568265 ps
CPU time 14.68 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:32:59 PM PDT 24
Peak memory 201876 kb
Host smart-98fa0492-db8a-4aeb-8c90-39f245cc1a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172107413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.3172107413
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3992372144
Short name T324
Test name
Test status
Simulation time 6053042023 ps
CPU time 17.29 seconds
Started Jul 05 05:08:47 PM PDT 24
Finished Jul 05 05:09:05 PM PDT 24
Peak memory 202012 kb
Host smart-7ca511a8-1163-4a84-9c2f-64dd42fea05c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992372144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.3992372144
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3032985908
Short name T25
Test name
Test status
Simulation time 3306827070 ps
CPU time 2.76 seconds
Started Jul 05 05:30:51 PM PDT 24
Finished Jul 05 05:30:55 PM PDT 24
Peak memory 201704 kb
Host smart-bb79bd58-88e3-442b-aad4-53411883d20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032985908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3
032985908
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4166426795
Short name T232
Test name
Test status
Simulation time 49410983148 ps
CPU time 66.39 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:32:01 PM PDT 24
Peak memory 201780 kb
Host smart-e7e4ad28-433f-4bf4-89d6-9377ebab0ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166426795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.4166426795
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.366837127
Short name T179
Test name
Test status
Simulation time 54626586241 ps
CPU time 33.19 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:37 PM PDT 24
Peak memory 201860 kb
Host smart-f1b1207c-eeb6-4512-9481-0bf0638715e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366837127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_wi
th_pre_cond.366837127
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.320677683
Short name T357
Test name
Test status
Simulation time 86161673154 ps
CPU time 57.86 seconds
Started Jul 05 05:31:10 PM PDT 24
Finished Jul 05 05:32:08 PM PDT 24
Peak memory 201788 kb
Host smart-f7e68a4f-01f1-4124-a78a-aff828e5def7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320677683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.320677683
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3651990869
Short name T263
Test name
Test status
Simulation time 128512194212 ps
CPU time 77.59 seconds
Started Jul 05 05:31:09 PM PDT 24
Finished Jul 05 05:32:28 PM PDT 24
Peak memory 201864 kb
Host smart-e8b6a899-ff55-48af-831e-b1a46bbf8dbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651990869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3651990869
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.3889005884
Short name T375
Test name
Test status
Simulation time 2514964016 ps
CPU time 4.11 seconds
Started Jul 05 05:31:26 PM PDT 24
Finished Jul 05 05:31:31 PM PDT 24
Peak memory 201644 kb
Host smart-ab3fa7ef-1d0e-49f1-a4a1-4c3d41e26440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889005884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.3889005884
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3385627391
Short name T334
Test name
Test status
Simulation time 79320527263 ps
CPU time 13.9 seconds
Started Jul 05 05:31:47 PM PDT 24
Finished Jul 05 05:32:01 PM PDT 24
Peak memory 201876 kb
Host smart-5fb9098f-2431-4c71-973b-5744bdbc31c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385627391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.3385627391
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.1655211700
Short name T81
Test name
Test status
Simulation time 72885259994 ps
CPU time 46.71 seconds
Started Jul 05 05:31:59 PM PDT 24
Finished Jul 05 05:32:48 PM PDT 24
Peak memory 201900 kb
Host smart-999c287d-95b3-462c-916d-c9341a7865b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655211700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.1655211700
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1608026983
Short name T337
Test name
Test status
Simulation time 73257580884 ps
CPU time 171.45 seconds
Started Jul 05 05:30:49 PM PDT 24
Finished Jul 05 05:33:41 PM PDT 24
Peak memory 201860 kb
Host smart-b0b44b31-9866-4ffa-ae4b-709d4b6f6128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608026983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.1608026983
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1890322885
Short name T369
Test name
Test status
Simulation time 101094725026 ps
CPU time 59.86 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:33:44 PM PDT 24
Peak memory 201864 kb
Host smart-dcb88775-81e9-4e2a-aeb5-435baf200b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890322885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.1890322885
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2188284737
Short name T339
Test name
Test status
Simulation time 78290743623 ps
CPU time 213.7 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:36:17 PM PDT 24
Peak memory 201928 kb
Host smart-42d6bc18-9456-40d7-a6f4-953b5c4bfb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188284737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.2188284737
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1846890088
Short name T340
Test name
Test status
Simulation time 65827972876 ps
CPU time 87.38 seconds
Started Jul 05 05:32:51 PM PDT 24
Finished Jul 05 05:34:20 PM PDT 24
Peak memory 201908 kb
Host smart-64051e37-01f4-47a3-95de-c8f3be036f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846890088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.1846890088
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.3220866173
Short name T163
Test name
Test status
Simulation time 4557540001 ps
CPU time 10 seconds
Started Jul 05 05:30:21 PM PDT 24
Finished Jul 05 05:30:31 PM PDT 24
Peak memory 201676 kb
Host smart-e816cd0b-ed61-498f-898e-af5fd25f5428
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220866173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.3220866173
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.1950609341
Short name T162
Test name
Test status
Simulation time 3984672157 ps
CPU time 3.07 seconds
Started Jul 05 05:31:19 PM PDT 24
Finished Jul 05 05:31:23 PM PDT 24
Peak memory 201644 kb
Host smart-4415b5bf-7a7a-4e3e-b2a4-72ca17264625
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950609341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.1950609341
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2185941766
Short name T196
Test name
Test status
Simulation time 16603467809 ps
CPU time 20.21 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:31:46 PM PDT 24
Peak memory 218372 kb
Host smart-9f2f81e5-6552-4f09-8577-5598407d9c13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185941766 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2185941766
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.31843469
Short name T37
Test name
Test status
Simulation time 54758691530 ps
CPU time 22.78 seconds
Started Jul 05 05:32:09 PM PDT 24
Finished Jul 05 05:32:33 PM PDT 24
Peak memory 210276 kb
Host smart-12402fd5-143c-45b5-a440-cdf117458ba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31843469 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.31843469
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2254560019
Short name T104
Test name
Test status
Simulation time 79585620640 ps
CPU time 43.28 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:32:17 PM PDT 24
Peak memory 201760 kb
Host smart-1bbce919-72b9-4d04-bc47-3c4743333155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254560019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.2254560019
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4221145330
Short name T91
Test name
Test status
Simulation time 2270814021 ps
CPU time 2.97 seconds
Started Jul 05 05:08:39 PM PDT 24
Finished Jul 05 05:08:43 PM PDT 24
Peak memory 202188 kb
Host smart-8ede4d59-33bc-441d-9ae8-a8b0e49b3687
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221145330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.4221145330
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.1283175050
Short name T4
Test name
Test status
Simulation time 2627511844 ps
CPU time 2.2 seconds
Started Jul 05 05:30:51 PM PDT 24
Finished Jul 05 05:30:55 PM PDT 24
Peak memory 201660 kb
Host smart-bfdbb3fd-2852-46c7-b3a3-b16028bc4fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283175050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.1283175050
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.793696539
Short name T79
Test name
Test status
Simulation time 38143589405 ps
CPU time 92.62 seconds
Started Jul 05 05:32:25 PM PDT 24
Finished Jul 05 05:33:58 PM PDT 24
Peak memory 201852 kb
Host smart-500d1e2f-493a-4616-ba5f-50c7a00f6531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793696539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_wi
th_pre_cond.793696539
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.279153147
Short name T309
Test name
Test status
Simulation time 3172435747 ps
CPU time 4.35 seconds
Started Jul 05 05:08:46 PM PDT 24
Finished Jul 05 05:08:51 PM PDT 24
Peak memory 202260 kb
Host smart-7701af5d-5ee4-498e-8b73-d1aef86a959e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279153147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_aliasing.279153147
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.99347704
Short name T890
Test name
Test status
Simulation time 39641011767 ps
CPU time 41.43 seconds
Started Jul 05 05:08:48 PM PDT 24
Finished Jul 05 05:09:30 PM PDT 24
Peak memory 202260 kb
Host smart-3f0ed416-85ef-4ce5-a384-2287e84c0199
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99347704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_c
sr_bit_bash.99347704
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2639390961
Short name T366
Test name
Test status
Simulation time 2075849852 ps
CPU time 3.18 seconds
Started Jul 05 05:08:46 PM PDT 24
Finished Jul 05 05:08:49 PM PDT 24
Peak memory 201960 kb
Host smart-d426b23e-93da-4152-b9a6-252817974ba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639390961 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2639390961
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1906181233
Short name T321
Test name
Test status
Simulation time 2026765741 ps
CPU time 5.89 seconds
Started Jul 05 05:08:44 PM PDT 24
Finished Jul 05 05:08:51 PM PDT 24
Peak memory 201808 kb
Host smart-3b16898d-f8ca-49fa-b7d5-cbc6fc4bcb7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906181233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1906181233
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.4125413784
Short name T790
Test name
Test status
Simulation time 2029131699 ps
CPU time 1.96 seconds
Started Jul 05 05:08:44 PM PDT 24
Finished Jul 05 05:08:46 PM PDT 24
Peak memory 201624 kb
Host smart-44178a84-f27f-49c3-8636-d626c7a7b4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125413784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.4125413784
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2101572518
Short name T876
Test name
Test status
Simulation time 22184268742 ps
CPU time 54.9 seconds
Started Jul 05 05:08:46 PM PDT 24
Finished Jul 05 05:09:41 PM PDT 24
Peak memory 202252 kb
Host smart-8a86126e-b03e-4f60-b102-178b570bdb61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101572518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.2101572518
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2854583710
Short name T882
Test name
Test status
Simulation time 39352043760 ps
CPU time 52.85 seconds
Started Jul 05 05:08:51 PM PDT 24
Finished Jul 05 05:09:44 PM PDT 24
Peak memory 202132 kb
Host smart-296722d6-9530-4ffb-9c6d-b1b1e025325f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854583710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.2854583710
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1543681186
Short name T303
Test name
Test status
Simulation time 4019123803 ps
CPU time 5.72 seconds
Started Jul 05 05:08:52 PM PDT 24
Finished Jul 05 05:08:58 PM PDT 24
Peak memory 201924 kb
Host smart-ce996dea-dc36-4d73-be86-b653f5f3732f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543681186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.1543681186
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.999902112
Short name T839
Test name
Test status
Simulation time 2179850527 ps
CPU time 2.47 seconds
Started Jul 05 05:08:52 PM PDT 24
Finished Jul 05 05:08:55 PM PDT 24
Peak memory 202108 kb
Host smart-f5a0b7b0-4d9b-4821-91ea-87a51462e482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999902112 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.999902112
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3498491172
Short name T834
Test name
Test status
Simulation time 2032383815 ps
CPU time 5.99 seconds
Started Jul 05 05:08:51 PM PDT 24
Finished Jul 05 05:08:57 PM PDT 24
Peak memory 201812 kb
Host smart-3e8c1c1a-2284-4588-89c6-45a7f986f24f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498491172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3498491172
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1903225695
Short name T899
Test name
Test status
Simulation time 2012169058 ps
CPU time 5.59 seconds
Started Jul 05 05:08:56 PM PDT 24
Finished Jul 05 05:09:02 PM PDT 24
Peak memory 201736 kb
Host smart-533aa4ac-c627-4f48-be91-56f1d4023bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903225695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1903225695
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1969708936
Short name T879
Test name
Test status
Simulation time 4366116256 ps
CPU time 4.56 seconds
Started Jul 05 05:08:52 PM PDT 24
Finished Jul 05 05:08:57 PM PDT 24
Peak memory 201940 kb
Host smart-9e21b278-3907-43f1-b28d-b785aff622d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969708936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.1969708936
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.68731552
Short name T819
Test name
Test status
Simulation time 2058219773 ps
CPU time 4.6 seconds
Started Jul 05 05:08:46 PM PDT 24
Finished Jul 05 05:08:51 PM PDT 24
Peak memory 202120 kb
Host smart-1ab07ba2-afad-47a7-9d52-18ceb3d9a1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68731552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.68731552
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2029536489
Short name T856
Test name
Test status
Simulation time 42644961476 ps
CPU time 101.89 seconds
Started Jul 05 05:08:51 PM PDT 24
Finished Jul 05 05:10:33 PM PDT 24
Peak memory 202220 kb
Host smart-36b5bd3a-6686-42b1-91e8-b24918c8cc82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029536489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.2029536489
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.146077065
Short name T836
Test name
Test status
Simulation time 2109833675 ps
CPU time 6.57 seconds
Started Jul 05 05:09:35 PM PDT 24
Finished Jul 05 05:09:42 PM PDT 24
Peak memory 201940 kb
Host smart-156c849e-510c-43eb-a18a-6576dde42753
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146077065 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.146077065
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1778125049
Short name T302
Test name
Test status
Simulation time 2104668845 ps
CPU time 2.43 seconds
Started Jul 05 05:09:34 PM PDT 24
Finished Jul 05 05:09:37 PM PDT 24
Peak memory 201988 kb
Host smart-b9073776-7bb1-48d1-89aa-5ca0e0a113a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778125049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.1778125049
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2025015611
Short name T891
Test name
Test status
Simulation time 2075532079 ps
CPU time 1.08 seconds
Started Jul 05 05:09:55 PM PDT 24
Finished Jul 05 05:09:58 PM PDT 24
Peak memory 201684 kb
Host smart-63f0394c-16c4-4200-ab87-ddb8a9b40d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025015611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.2025015611
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3210887717
Short name T894
Test name
Test status
Simulation time 5169074402 ps
CPU time 19.55 seconds
Started Jul 05 05:09:32 PM PDT 24
Finished Jul 05 05:09:52 PM PDT 24
Peak memory 202240 kb
Host smart-abba1748-58a6-4dfa-9905-65967d78c928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210887717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.3210887717
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1357564595
Short name T793
Test name
Test status
Simulation time 3004880040 ps
CPU time 2.8 seconds
Started Jul 05 05:09:33 PM PDT 24
Finished Jul 05 05:09:36 PM PDT 24
Peak memory 202180 kb
Host smart-880de5f1-0ea9-4267-9487-853c72ddedde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357564595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.1357564595
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3555934658
Short name T861
Test name
Test status
Simulation time 42917370196 ps
CPU time 31.45 seconds
Started Jul 05 05:09:34 PM PDT 24
Finished Jul 05 05:10:06 PM PDT 24
Peak memory 202276 kb
Host smart-fedd0b47-57af-4aee-88fe-7fdec894d0fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555934658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.3555934658
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3670614486
Short name T93
Test name
Test status
Simulation time 2097209799 ps
CPU time 3.23 seconds
Started Jul 05 05:09:40 PM PDT 24
Finished Jul 05 05:09:44 PM PDT 24
Peak memory 201924 kb
Host smart-bc4fbeed-487c-4e83-b6ad-6681c4d241f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670614486 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3670614486
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.736220304
Short name T312
Test name
Test status
Simulation time 2056656466 ps
CPU time 5.98 seconds
Started Jul 05 05:09:40 PM PDT 24
Finished Jul 05 05:09:47 PM PDT 24
Peak memory 201856 kb
Host smart-23aa7ac7-7fef-4b27-bff6-bfeb96c9e540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736220304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_r
w.736220304
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.732054660
Short name T880
Test name
Test status
Simulation time 2012760301 ps
CPU time 5.88 seconds
Started Jul 05 05:09:55 PM PDT 24
Finished Jul 05 05:10:03 PM PDT 24
Peak memory 201692 kb
Host smart-75597c56-81e1-4596-9f20-8d45fae106f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732054660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.732054660
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3251913168
Short name T812
Test name
Test status
Simulation time 7532669679 ps
CPU time 8.8 seconds
Started Jul 05 05:09:56 PM PDT 24
Finished Jul 05 05:10:06 PM PDT 24
Peak memory 202216 kb
Host smart-dacfa9d2-99bc-497b-8960-b861bddd2729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251913168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.3251913168
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1066468521
Short name T852
Test name
Test status
Simulation time 2165135098 ps
CPU time 2.59 seconds
Started Jul 05 05:09:56 PM PDT 24
Finished Jul 05 05:10:00 PM PDT 24
Peak memory 202252 kb
Host smart-1093f42f-898c-4b67-b8a0-e449ba047532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066468521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.1066468521
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3571337371
Short name T867
Test name
Test status
Simulation time 42687820581 ps
CPU time 45.48 seconds
Started Jul 05 05:09:39 PM PDT 24
Finished Jul 05 05:10:26 PM PDT 24
Peak memory 202328 kb
Host smart-13c66cff-0a43-44fb-9f4b-e490731042c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571337371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3571337371
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2872852436
Short name T850
Test name
Test status
Simulation time 2088746059 ps
CPU time 5.9 seconds
Started Jul 05 05:09:40 PM PDT 24
Finished Jul 05 05:09:47 PM PDT 24
Peak memory 202036 kb
Host smart-5dc98bda-8e75-4437-a366-d686aea5d7dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872852436 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2872852436
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.110765160
Short name T901
Test name
Test status
Simulation time 2077160113 ps
CPU time 2.01 seconds
Started Jul 05 05:09:41 PM PDT 24
Finished Jul 05 05:09:44 PM PDT 24
Peak memory 201976 kb
Host smart-b7246778-1c4a-4278-8fa1-d2d02713bf66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110765160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r
w.110765160
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2904128972
Short name T903
Test name
Test status
Simulation time 2031315396 ps
CPU time 1.96 seconds
Started Jul 05 05:09:56 PM PDT 24
Finished Jul 05 05:09:59 PM PDT 24
Peak memory 201724 kb
Host smart-79e6a629-66ad-49ff-8ef9-478cf03ac6ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904128972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2904128972
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.327579778
Short name T21
Test name
Test status
Simulation time 10113196540 ps
CPU time 7.55 seconds
Started Jul 05 05:09:40 PM PDT 24
Finished Jul 05 05:09:49 PM PDT 24
Peak memory 202328 kb
Host smart-d2cacaf5-a6e6-491b-9b30-5f8adefceb37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327579778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.sysrst_ctrl_same_csr_outstanding.327579778
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4272666032
Short name T95
Test name
Test status
Simulation time 2637164043 ps
CPU time 3.75 seconds
Started Jul 05 05:09:41 PM PDT 24
Finished Jul 05 05:09:46 PM PDT 24
Peak memory 202272 kb
Host smart-97d6fc6f-bef9-4d70-8089-aef69a1bdbb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272666032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.4272666032
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2308852520
Short name T90
Test name
Test status
Simulation time 43169995564 ps
CPU time 20.64 seconds
Started Jul 05 05:09:39 PM PDT 24
Finished Jul 05 05:10:01 PM PDT 24
Peak memory 202212 kb
Host smart-b44db33e-51aa-4c7f-b83d-4d247347ec6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308852520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.2308852520
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.415524837
Short name T822
Test name
Test status
Simulation time 2073700762 ps
CPU time 2.25 seconds
Started Jul 05 05:09:49 PM PDT 24
Finished Jul 05 05:09:52 PM PDT 24
Peak memory 201956 kb
Host smart-6f3b97bf-0678-4382-a944-31b438ad7265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415524837 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.415524837
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3794092343
Short name T311
Test name
Test status
Simulation time 2050660788 ps
CPU time 5.81 seconds
Started Jul 05 05:09:50 PM PDT 24
Finished Jul 05 05:09:57 PM PDT 24
Peak memory 201972 kb
Host smart-fb7bd18a-f3cc-4c04-88f3-5e29b52b4de9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794092343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.3794092343
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.581143145
Short name T805
Test name
Test status
Simulation time 2013278060 ps
CPU time 5.72 seconds
Started Jul 05 05:09:51 PM PDT 24
Finished Jul 05 05:09:58 PM PDT 24
Peak memory 201772 kb
Host smart-0329428a-7985-4136-866a-f0b684032dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581143145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_tes
t.581143145
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.20193695
Short name T889
Test name
Test status
Simulation time 10400654666 ps
CPU time 23.94 seconds
Started Jul 05 05:09:54 PM PDT 24
Finished Jul 05 05:10:19 PM PDT 24
Peak memory 202332 kb
Host smart-990494eb-7926-4868-9070-d40b14310d9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20193695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=
sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
sysrst_ctrl_same_csr_outstanding.20193695
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.639883961
Short name T811
Test name
Test status
Simulation time 2049102068 ps
CPU time 8.15 seconds
Started Jul 05 05:09:48 PM PDT 24
Finished Jul 05 05:09:57 PM PDT 24
Peak memory 210368 kb
Host smart-d3bb470b-64f7-4abd-8a2e-fc9d6c5da445
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639883961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.639883961
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.4100464389
Short name T841
Test name
Test status
Simulation time 42423592142 ps
CPU time 86.82 seconds
Started Jul 05 05:09:49 PM PDT 24
Finished Jul 05 05:11:17 PM PDT 24
Peak memory 202240 kb
Host smart-8dd06085-f5ae-4ef9-82e7-27083fe6dd41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100464389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.4100464389
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.364211712
Short name T30
Test name
Test status
Simulation time 2146626009 ps
CPU time 2.04 seconds
Started Jul 05 05:09:49 PM PDT 24
Finished Jul 05 05:09:52 PM PDT 24
Peak memory 201880 kb
Host smart-00aa033b-449c-4629-af34-c7e86f3ea15d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364211712 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.364211712
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.573770734
Short name T864
Test name
Test status
Simulation time 2046191354 ps
CPU time 3.47 seconds
Started Jul 05 05:09:50 PM PDT 24
Finished Jul 05 05:09:54 PM PDT 24
Peak memory 201972 kb
Host smart-cc8a7a7f-ebbd-44e7-ac8d-bc0421f575f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573770734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.573770734
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1458455146
Short name T897
Test name
Test status
Simulation time 2012962951 ps
CPU time 5.84 seconds
Started Jul 05 05:09:49 PM PDT 24
Finished Jul 05 05:09:57 PM PDT 24
Peak memory 201868 kb
Host smart-c30f7216-8078-4977-b47f-d28f8c9738de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458455146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1458455146
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.170130274
Short name T843
Test name
Test status
Simulation time 9666672262 ps
CPU time 7.13 seconds
Started Jul 05 05:09:48 PM PDT 24
Finished Jul 05 05:09:57 PM PDT 24
Peak memory 202252 kb
Host smart-a34a6855-cc29-416a-9224-b63d20985f33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170130274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_same_csr_outstanding.170130274
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2413969977
Short name T99
Test name
Test status
Simulation time 2043633024 ps
CPU time 6.9 seconds
Started Jul 05 05:09:47 PM PDT 24
Finished Jul 05 05:09:55 PM PDT 24
Peak memory 210276 kb
Host smart-ffdec01b-a061-47bb-9495-b55362e33523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413969977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2413969977
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1995192959
Short name T869
Test name
Test status
Simulation time 2215631650 ps
CPU time 2.36 seconds
Started Jul 05 05:09:56 PM PDT 24
Finished Jul 05 05:10:00 PM PDT 24
Peak memory 202056 kb
Host smart-96c17076-b05f-43ed-a68e-747ce6b4ae58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995192959 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1995192959
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1804454548
Short name T313
Test name
Test status
Simulation time 2072290585 ps
CPU time 1.59 seconds
Started Jul 05 05:09:48 PM PDT 24
Finished Jul 05 05:09:51 PM PDT 24
Peak memory 201908 kb
Host smart-bd988f9a-abc5-412a-a4f5-2adadde85ff3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804454548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1804454548
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.491094616
Short name T798
Test name
Test status
Simulation time 2014383186 ps
CPU time 5.24 seconds
Started Jul 05 05:09:49 PM PDT 24
Finished Jul 05 05:09:55 PM PDT 24
Peak memory 201744 kb
Host smart-49c8651b-b52d-4590-abb5-6165b70b51a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491094616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_tes
t.491094616
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1738850500
Short name T904
Test name
Test status
Simulation time 4816132394 ps
CPU time 3.02 seconds
Started Jul 05 05:09:49 PM PDT 24
Finished Jul 05 05:09:53 PM PDT 24
Peak memory 202004 kb
Host smart-b5680d71-37e4-4a4a-aca1-b9cb41621689
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738850500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.1738850500
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2388237268
Short name T873
Test name
Test status
Simulation time 2109024779 ps
CPU time 7.89 seconds
Started Jul 05 05:09:53 PM PDT 24
Finished Jul 05 05:10:01 PM PDT 24
Peak memory 202188 kb
Host smart-1e20ab59-ec33-4e2c-aa0e-407e9415db67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388237268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.2388237268
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2948661906
Short name T854
Test name
Test status
Simulation time 2124979068 ps
CPU time 3.85 seconds
Started Jul 05 05:10:02 PM PDT 24
Finished Jul 05 05:10:07 PM PDT 24
Peak memory 202024 kb
Host smart-81aa3cd7-5c53-47e3-832a-9930273caf48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948661906 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2948661906
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.181136163
Short name T800
Test name
Test status
Simulation time 2034192426 ps
CPU time 6.23 seconds
Started Jul 05 05:09:56 PM PDT 24
Finished Jul 05 05:10:04 PM PDT 24
Peak memory 201940 kb
Host smart-657329c0-71df-4583-93e9-c92819cbfbe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181136163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_r
w.181136163
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.342922921
Short name T807
Test name
Test status
Simulation time 2020473458 ps
CPU time 3.12 seconds
Started Jul 05 05:10:03 PM PDT 24
Finished Jul 05 05:10:07 PM PDT 24
Peak memory 201688 kb
Host smart-4f2b1965-b9dc-4e39-b4a8-3387316e43e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342922921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_tes
t.342922921
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.4108490025
Short name T804
Test name
Test status
Simulation time 9305050541 ps
CPU time 22.3 seconds
Started Jul 05 05:09:58 PM PDT 24
Finished Jul 05 05:10:21 PM PDT 24
Peak memory 202284 kb
Host smart-2aeb9510-cfbd-466c-a089-2a199beb18ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108490025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.4108490025
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.781335122
Short name T865
Test name
Test status
Simulation time 22391914017 ps
CPU time 16.23 seconds
Started Jul 05 05:10:01 PM PDT 24
Finished Jul 05 05:10:19 PM PDT 24
Peak memory 202276 kb
Host smart-227813a0-f087-4de6-ba69-19088cf1f3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781335122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_tl_intg_err.781335122
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.697873455
Short name T814
Test name
Test status
Simulation time 2130250894 ps
CPU time 1.85 seconds
Started Jul 05 05:09:57 PM PDT 24
Finished Jul 05 05:10:00 PM PDT 24
Peak memory 201836 kb
Host smart-a745ce83-c573-4dd0-a44d-6010c4ed4dbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697873455 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.697873455
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1351614332
Short name T860
Test name
Test status
Simulation time 2038882981 ps
CPU time 6.01 seconds
Started Jul 05 05:10:02 PM PDT 24
Finished Jul 05 05:10:09 PM PDT 24
Peak memory 201880 kb
Host smart-edd59080-4850-4d11-b282-de6421947d55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351614332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.1351614332
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3228829872
Short name T872
Test name
Test status
Simulation time 2012162431 ps
CPU time 5.97 seconds
Started Jul 05 05:09:59 PM PDT 24
Finished Jul 05 05:10:06 PM PDT 24
Peak memory 201700 kb
Host smart-6beafd08-d13a-47f0-84c7-61617736b5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228829872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3228829872
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.208015469
Short name T896
Test name
Test status
Simulation time 9401906917 ps
CPU time 42.94 seconds
Started Jul 05 05:09:54 PM PDT 24
Finished Jul 05 05:10:38 PM PDT 24
Peak memory 202160 kb
Host smart-e41b091c-c949-481e-a4b3-fbeae7fc400a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208015469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.208015469
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1730519917
Short name T870
Test name
Test status
Simulation time 2264142675 ps
CPU time 2.87 seconds
Started Jul 05 05:10:01 PM PDT 24
Finished Jul 05 05:10:05 PM PDT 24
Peak memory 202272 kb
Host smart-46c67924-ae52-4475-a119-2c9c6b23e3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730519917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.1730519917
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.577346933
Short name T835
Test name
Test status
Simulation time 22452943131 ps
CPU time 15.68 seconds
Started Jul 05 05:09:56 PM PDT 24
Finished Jul 05 05:10:13 PM PDT 24
Peak memory 202192 kb
Host smart-21a6f0fb-6b42-4cf6-a2f6-81a011726126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577346933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.577346933
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1337975622
Short name T801
Test name
Test status
Simulation time 2101663589 ps
CPU time 6.19 seconds
Started Jul 05 05:10:03 PM PDT 24
Finished Jul 05 05:10:10 PM PDT 24
Peak memory 202100 kb
Host smart-0989b390-5918-4752-9ec2-6ccfc7517618
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337975622 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1337975622
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.383952773
Short name T305
Test name
Test status
Simulation time 2060308761 ps
CPU time 1.84 seconds
Started Jul 05 05:10:06 PM PDT 24
Finished Jul 05 05:10:09 PM PDT 24
Peak memory 201892 kb
Host smart-ccdfa05d-0c88-4a77-a223-0551b4abf60e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383952773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_r
w.383952773
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2534800551
Short name T828
Test name
Test status
Simulation time 2023383103 ps
CPU time 3.21 seconds
Started Jul 05 05:09:55 PM PDT 24
Finished Jul 05 05:09:59 PM PDT 24
Peak memory 201756 kb
Host smart-19834069-b1fe-42b5-8878-17f0165313b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534800551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2534800551
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.246415182
Short name T837
Test name
Test status
Simulation time 7252972987 ps
CPU time 5.77 seconds
Started Jul 05 05:10:04 PM PDT 24
Finished Jul 05 05:10:11 PM PDT 24
Peak memory 202192 kb
Host smart-4df44833-5dd3-4727-a04d-495ec0b06056
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246415182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.sysrst_ctrl_same_csr_outstanding.246415182
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.719380517
Short name T794
Test name
Test status
Simulation time 2135248603 ps
CPU time 3.53 seconds
Started Jul 05 05:09:57 PM PDT 24
Finished Jul 05 05:10:01 PM PDT 24
Peak memory 202092 kb
Host smart-741c2b87-2b41-4496-bd75-b768ff06b091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719380517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_error
s.719380517
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1477041446
Short name T343
Test name
Test status
Simulation time 43498214085 ps
CPU time 15.62 seconds
Started Jul 05 05:10:03 PM PDT 24
Finished Jul 05 05:10:20 PM PDT 24
Peak memory 202276 kb
Host smart-2d895888-adb8-4cdf-9583-057a430d5f25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477041446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.1477041446
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3869974019
Short name T846
Test name
Test status
Simulation time 2088755418 ps
CPU time 6.11 seconds
Started Jul 05 05:10:04 PM PDT 24
Finished Jul 05 05:10:11 PM PDT 24
Peak memory 201848 kb
Host smart-f415505e-26c6-4024-9509-b6f9e1ec3acc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869974019 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3869974019
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1607320127
Short name T314
Test name
Test status
Simulation time 2079720663 ps
CPU time 2.02 seconds
Started Jul 05 05:10:05 PM PDT 24
Finished Jul 05 05:10:08 PM PDT 24
Peak memory 201804 kb
Host smart-137d0680-f952-4477-ac16-aeb3782e1f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607320127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.1607320127
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.706936790
Short name T842
Test name
Test status
Simulation time 2012619916 ps
CPU time 5.58 seconds
Started Jul 05 05:10:05 PM PDT 24
Finished Jul 05 05:10:12 PM PDT 24
Peak memory 201860 kb
Host smart-c4709f1e-cd06-450c-b05f-2b75ed5d4ef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706936790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_tes
t.706936790
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3420121468
Short name T803
Test name
Test status
Simulation time 9881795325 ps
CPU time 30.63 seconds
Started Jul 05 05:10:06 PM PDT 24
Finished Jul 05 05:10:38 PM PDT 24
Peak memory 202248 kb
Host smart-f767083f-9cdc-4041-be83-865b3a7bf342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420121468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.3420121468
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2605167806
Short name T85
Test name
Test status
Simulation time 2055850680 ps
CPU time 4.03 seconds
Started Jul 05 05:10:05 PM PDT 24
Finished Jul 05 05:10:10 PM PDT 24
Peak memory 202080 kb
Host smart-68828dba-34e7-4c8f-8aee-933f57918e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605167806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.2605167806
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2847816276
Short name T341
Test name
Test status
Simulation time 42808862518 ps
CPU time 29.56 seconds
Started Jul 05 05:10:04 PM PDT 24
Finished Jul 05 05:10:34 PM PDT 24
Peak memory 202272 kb
Host smart-25f80c21-cc7d-4362-b160-ef341f333f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847816276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2847816276
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2729325417
Short name T825
Test name
Test status
Simulation time 3466993546 ps
CPU time 5.37 seconds
Started Jul 05 05:09:01 PM PDT 24
Finished Jul 05 05:09:07 PM PDT 24
Peak memory 202260 kb
Host smart-1b94e803-ddbb-425f-82b2-42cc45af06ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729325417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.2729325417
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1071588816
Short name T315
Test name
Test status
Simulation time 39814286520 ps
CPU time 73.18 seconds
Started Jul 05 05:09:20 PM PDT 24
Finished Jul 05 05:10:34 PM PDT 24
Peak memory 202256 kb
Host smart-dc709659-835d-4d32-bca3-b19708529f95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071588816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.1071588816
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3473358770
Short name T306
Test name
Test status
Simulation time 6037328181 ps
CPU time 8.87 seconds
Started Jul 05 05:09:02 PM PDT 24
Finished Jul 05 05:09:11 PM PDT 24
Peak memory 202092 kb
Host smart-11340909-dfbd-408e-89bb-064b910f1cd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473358770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.3473358770
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.4224904413
Short name T365
Test name
Test status
Simulation time 2478813994 ps
CPU time 1.23 seconds
Started Jul 05 05:09:01 PM PDT 24
Finished Jul 05 05:09:03 PM PDT 24
Peak memory 201968 kb
Host smart-af9e7ed0-75d8-4e42-826d-f510574d6cb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224904413 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.4224904413
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1482176955
Short name T826
Test name
Test status
Simulation time 2040692255 ps
CPU time 2.99 seconds
Started Jul 05 05:09:01 PM PDT 24
Finished Jul 05 05:09:04 PM PDT 24
Peak memory 201908 kb
Host smart-bc762170-4b8c-4020-8e1e-fbdda81f771e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482176955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.1482176955
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1060193522
Short name T810
Test name
Test status
Simulation time 2018425676 ps
CPU time 3.15 seconds
Started Jul 05 05:09:02 PM PDT 24
Finished Jul 05 05:09:06 PM PDT 24
Peak memory 201704 kb
Host smart-1732790b-02da-4eeb-ae67-03ed9ea16283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060193522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.1060193522
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1271211276
Short name T806
Test name
Test status
Simulation time 5079070345 ps
CPU time 10.93 seconds
Started Jul 05 05:08:59 PM PDT 24
Finished Jul 05 05:09:10 PM PDT 24
Peak memory 202308 kb
Host smart-86ba30ce-9e27-4e3f-ae1f-e11ec6681f4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271211276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.1271211276
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1085584789
Short name T809
Test name
Test status
Simulation time 2143775638 ps
CPU time 3.61 seconds
Started Jul 05 05:08:51 PM PDT 24
Finished Jul 05 05:08:55 PM PDT 24
Peak memory 202012 kb
Host smart-0c110dca-d2c7-4ca9-bba1-9297a081dc17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085584789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.1085584789
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2209844072
Short name T831
Test name
Test status
Simulation time 22772948982 ps
CPU time 10.39 seconds
Started Jul 05 05:08:59 PM PDT 24
Finished Jul 05 05:09:10 PM PDT 24
Peak memory 202272 kb
Host smart-169c9508-68b6-47a6-9272-02c625fddc31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209844072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.2209844072
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.4227159943
Short name T830
Test name
Test status
Simulation time 2011807921 ps
CPU time 5.41 seconds
Started Jul 05 05:10:06 PM PDT 24
Finished Jul 05 05:10:12 PM PDT 24
Peak memory 201792 kb
Host smart-c14f334c-af9f-4387-9129-9f0e73ec9189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227159943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.4227159943
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1507576946
Short name T832
Test name
Test status
Simulation time 2009874981 ps
CPU time 4.8 seconds
Started Jul 05 05:10:02 PM PDT 24
Finished Jul 05 05:10:09 PM PDT 24
Peak memory 201696 kb
Host smart-2d7938f5-fcbd-4e8d-a171-ad886875f394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507576946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.1507576946
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2894112930
Short name T885
Test name
Test status
Simulation time 2015849446 ps
CPU time 4.47 seconds
Started Jul 05 05:10:10 PM PDT 24
Finished Jul 05 05:10:15 PM PDT 24
Peak memory 201692 kb
Host smart-d1e3c450-d0cc-4e4d-a1b8-94fd9d1286f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894112930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2894112930
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2326721220
Short name T893
Test name
Test status
Simulation time 2013419053 ps
CPU time 5.75 seconds
Started Jul 05 05:10:12 PM PDT 24
Finished Jul 05 05:10:18 PM PDT 24
Peak memory 201844 kb
Host smart-d3ced17e-1bab-4c74-933e-8f1b0bb2dc7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326721220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.2326721220
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1398112552
Short name T791
Test name
Test status
Simulation time 2028916575 ps
CPU time 1.93 seconds
Started Jul 05 05:10:10 PM PDT 24
Finished Jul 05 05:10:13 PM PDT 24
Peak memory 201768 kb
Host smart-01f9b312-2b8e-453e-8706-672455f86719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398112552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1398112552
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3499141924
Short name T902
Test name
Test status
Simulation time 2013530668 ps
CPU time 5.65 seconds
Started Jul 05 05:10:11 PM PDT 24
Finished Jul 05 05:10:17 PM PDT 24
Peak memory 201868 kb
Host smart-7ae69d5b-ff5e-44e5-9cac-e6367f0f8cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499141924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.3499141924
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.151719422
Short name T829
Test name
Test status
Simulation time 2022615224 ps
CPU time 3.19 seconds
Started Jul 05 05:10:13 PM PDT 24
Finished Jul 05 05:10:17 PM PDT 24
Peak memory 201872 kb
Host smart-28558798-8aa9-479d-a330-89c5ef89d470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151719422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_tes
t.151719422
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.766078592
Short name T857
Test name
Test status
Simulation time 2020142463 ps
CPU time 3.16 seconds
Started Jul 05 05:10:12 PM PDT 24
Finished Jul 05 05:10:16 PM PDT 24
Peak memory 201688 kb
Host smart-28f4960e-5080-41f8-a1d7-9b99744465fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766078592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_tes
t.766078592
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1147330795
Short name T866
Test name
Test status
Simulation time 2049888568 ps
CPU time 1.75 seconds
Started Jul 05 05:10:11 PM PDT 24
Finished Jul 05 05:10:13 PM PDT 24
Peak memory 201828 kb
Host smart-a0faeff9-44d9-4900-8522-ef3f292adb64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147330795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.1147330795
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3119971417
Short name T789
Test name
Test status
Simulation time 2034734738 ps
CPU time 2.65 seconds
Started Jul 05 05:10:11 PM PDT 24
Finished Jul 05 05:10:14 PM PDT 24
Peak memory 201824 kb
Host smart-7470e23d-7afb-41b6-bb7b-a5c606c43d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119971417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.3119971417
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3524832457
Short name T316
Test name
Test status
Simulation time 2707058823 ps
CPU time 4.51 seconds
Started Jul 05 05:09:09 PM PDT 24
Finished Jul 05 05:09:14 PM PDT 24
Peak memory 202148 kb
Host smart-b1d4a39a-8ab4-40da-8587-60e9f58fce78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524832457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.3524832457
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3355914715
Short name T840
Test name
Test status
Simulation time 39685919170 ps
CPU time 59.91 seconds
Started Jul 05 05:09:07 PM PDT 24
Finished Jul 05 05:10:08 PM PDT 24
Peak memory 202248 kb
Host smart-0ac74149-dd50-457f-ab68-5fc231849af8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355914715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3355914715
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1481181323
Short name T307
Test name
Test status
Simulation time 4028620443 ps
CPU time 7.19 seconds
Started Jul 05 05:09:05 PM PDT 24
Finished Jul 05 05:09:13 PM PDT 24
Peak memory 202080 kb
Host smart-6bd6e853-3488-4d07-810f-0ad06cebed7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481181323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1481181323
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3008011941
Short name T367
Test name
Test status
Simulation time 2109712276 ps
CPU time 2.34 seconds
Started Jul 05 05:09:13 PM PDT 24
Finished Jul 05 05:09:16 PM PDT 24
Peak memory 201912 kb
Host smart-8587225e-89ed-45c8-aec2-befc95048bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008011941 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3008011941
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2687083097
Short name T323
Test name
Test status
Simulation time 2038947087 ps
CPU time 3.25 seconds
Started Jul 05 05:09:08 PM PDT 24
Finished Jul 05 05:09:12 PM PDT 24
Peak memory 201896 kb
Host smart-e3bb3315-3af3-4d98-9417-c941b1e7883b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687083097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.2687083097
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1340763331
Short name T815
Test name
Test status
Simulation time 2018895575 ps
CPU time 3.01 seconds
Started Jul 05 05:09:08 PM PDT 24
Finished Jul 05 05:09:12 PM PDT 24
Peak memory 201728 kb
Host smart-3735f672-9482-416c-9225-2fb84764e8a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340763331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1340763331
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.722930227
Short name T318
Test name
Test status
Simulation time 5256538799 ps
CPU time 4.35 seconds
Started Jul 05 05:09:15 PM PDT 24
Finished Jul 05 05:09:20 PM PDT 24
Peak memory 202196 kb
Host smart-f2f49dc1-33f4-4fdb-ae77-685869293635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722930227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
sysrst_ctrl_same_csr_outstanding.722930227
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1961232188
Short name T817
Test name
Test status
Simulation time 2167719955 ps
CPU time 3.69 seconds
Started Jul 05 05:09:10 PM PDT 24
Finished Jul 05 05:09:14 PM PDT 24
Peak memory 210420 kb
Host smart-a15efdeb-9d23-4d75-ad87-e2788adbf0a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961232188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.1961232188
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2572765041
Short name T853
Test name
Test status
Simulation time 22655548080 ps
CPU time 11.43 seconds
Started Jul 05 05:09:06 PM PDT 24
Finished Jul 05 05:09:18 PM PDT 24
Peak memory 202188 kb
Host smart-a2f99818-3eac-4397-b583-309f1e8aab2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572765041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.2572765041
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.347738437
Short name T862
Test name
Test status
Simulation time 2031344070 ps
CPU time 1.94 seconds
Started Jul 05 05:10:11 PM PDT 24
Finished Jul 05 05:10:14 PM PDT 24
Peak memory 201868 kb
Host smart-774b0cf8-f161-4cf6-95c2-0dcd702425a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347738437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_tes
t.347738437
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2510460268
Short name T886
Test name
Test status
Simulation time 2011621873 ps
CPU time 5.76 seconds
Started Jul 05 05:10:12 PM PDT 24
Finished Jul 05 05:10:18 PM PDT 24
Peak memory 201660 kb
Host smart-3575fd3d-d9a6-410b-8a22-d1a70f6939dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510460268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2510460268
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1259249223
Short name T871
Test name
Test status
Simulation time 2030590832 ps
CPU time 2.89 seconds
Started Jul 05 05:10:11 PM PDT 24
Finished Jul 05 05:10:15 PM PDT 24
Peak memory 201708 kb
Host smart-a09fad6d-33f2-4c19-8666-dfebdcc07ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259249223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.1259249223
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4154558319
Short name T813
Test name
Test status
Simulation time 2028481710 ps
CPU time 1.76 seconds
Started Jul 05 05:10:13 PM PDT 24
Finished Jul 05 05:10:15 PM PDT 24
Peak memory 201660 kb
Host smart-8c1f0c25-4c2f-400d-aae0-e99e185b9075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154558319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.4154558319
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2497833615
Short name T847
Test name
Test status
Simulation time 2041962893 ps
CPU time 1.95 seconds
Started Jul 05 05:10:10 PM PDT 24
Finished Jul 05 05:10:13 PM PDT 24
Peak memory 201780 kb
Host smart-6b6697d4-ceb9-4a36-8eeb-a0fc60b16401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497833615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.2497833615
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2183424134
Short name T820
Test name
Test status
Simulation time 2016333822 ps
CPU time 5.29 seconds
Started Jul 05 05:10:10 PM PDT 24
Finished Jul 05 05:10:16 PM PDT 24
Peak memory 201844 kb
Host smart-9f94c119-e4d8-46b0-ae0e-ebe3c05151f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183424134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2183424134
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1542832398
Short name T796
Test name
Test status
Simulation time 2011586854 ps
CPU time 5.6 seconds
Started Jul 05 05:10:23 PM PDT 24
Finished Jul 05 05:10:29 PM PDT 24
Peak memory 201608 kb
Host smart-1feae7d1-c619-4930-b785-dd13fa5a4d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542832398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.1542832398
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2756620635
Short name T838
Test name
Test status
Simulation time 2012624956 ps
CPU time 5.5 seconds
Started Jul 05 05:10:16 PM PDT 24
Finished Jul 05 05:10:22 PM PDT 24
Peak memory 201708 kb
Host smart-70349aa0-925f-410a-acfc-c887fd3c7ed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756620635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.2756620635
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.811295942
Short name T799
Test name
Test status
Simulation time 2024273078 ps
CPU time 3.2 seconds
Started Jul 05 05:10:16 PM PDT 24
Finished Jul 05 05:10:20 PM PDT 24
Peak memory 201680 kb
Host smart-b44055da-b19b-427a-834d-71e6eb2804f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811295942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_tes
t.811295942
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.4072811496
Short name T802
Test name
Test status
Simulation time 2010933942 ps
CPU time 5.59 seconds
Started Jul 05 05:10:18 PM PDT 24
Finished Jul 05 05:10:24 PM PDT 24
Peak memory 201620 kb
Host smart-9e832fb2-f46e-47b6-9342-41d63176bba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072811496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.4072811496
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.172225879
Short name T317
Test name
Test status
Simulation time 2534674296 ps
CPU time 10.06 seconds
Started Jul 05 05:09:20 PM PDT 24
Finished Jul 05 05:09:30 PM PDT 24
Peak memory 202308 kb
Host smart-4d155a1f-27a3-4e6e-a605-ced6f8e79048
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172225879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_aliasing.172225879
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2050679686
Short name T308
Test name
Test status
Simulation time 49352785628 ps
CPU time 113.18 seconds
Started Jul 05 05:09:19 PM PDT 24
Finished Jul 05 05:11:12 PM PDT 24
Peak memory 202328 kb
Host smart-df8be3e9-3089-42a8-b05d-c83384cb6376
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050679686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2050679686
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2605690637
Short name T858
Test name
Test status
Simulation time 4036120084 ps
CPU time 3.27 seconds
Started Jul 05 05:09:21 PM PDT 24
Finished Jul 05 05:09:25 PM PDT 24
Peak memory 202020 kb
Host smart-66c5705c-d683-4651-9995-48cf5cd1a86c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605690637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.2605690637
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.158327507
Short name T29
Test name
Test status
Simulation time 2145744816 ps
CPU time 6.5 seconds
Started Jul 05 05:09:19 PM PDT 24
Finished Jul 05 05:09:26 PM PDT 24
Peak memory 201956 kb
Host smart-450923f2-2c7e-4062-ab30-034df638fde9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158327507 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.158327507
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3947694654
Short name T816
Test name
Test status
Simulation time 2046084079 ps
CPU time 3.35 seconds
Started Jul 05 05:09:19 PM PDT 24
Finished Jul 05 05:09:23 PM PDT 24
Peak memory 201972 kb
Host smart-f77dec9d-b463-412d-a852-be4c6239e074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947694654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3947694654
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.492841199
Short name T792
Test name
Test status
Simulation time 2015053730 ps
CPU time 5.83 seconds
Started Jul 05 05:09:16 PM PDT 24
Finished Jul 05 05:09:23 PM PDT 24
Peak memory 201696 kb
Host smart-0b3cce41-3fba-4d49-a0c8-dc5bff724d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492841199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test
.492841199
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2188889687
Short name T906
Test name
Test status
Simulation time 4720621282 ps
CPU time 10.13 seconds
Started Jul 05 05:09:19 PM PDT 24
Finished Jul 05 05:09:29 PM PDT 24
Peak memory 202228 kb
Host smart-3e31279a-5458-45b9-b2be-0efc53811712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188889687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2188889687
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1003819573
Short name T855
Test name
Test status
Simulation time 2117796572 ps
CPU time 7.67 seconds
Started Jul 05 05:09:14 PM PDT 24
Finished Jul 05 05:09:22 PM PDT 24
Peak memory 202120 kb
Host smart-94948253-5e5d-4889-9678-04906f68b3af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003819573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.1003819573
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.818737409
Short name T342
Test name
Test status
Simulation time 22233435143 ps
CPU time 57.04 seconds
Started Jul 05 05:09:16 PM PDT 24
Finished Jul 05 05:10:14 PM PDT 24
Peak memory 202296 kb
Host smart-b9656dcf-b7d7-4225-988d-c31b353b8dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818737409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_tl_intg_err.818737409
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2847174777
Short name T884
Test name
Test status
Simulation time 2028882154 ps
CPU time 1.88 seconds
Started Jul 05 05:10:53 PM PDT 24
Finished Jul 05 05:10:56 PM PDT 24
Peak memory 201728 kb
Host smart-ab3e2118-6b3c-4749-be6c-ddcca87b5cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847174777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.2847174777
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2980097198
Short name T859
Test name
Test status
Simulation time 2032976785 ps
CPU time 1.89 seconds
Started Jul 05 05:10:22 PM PDT 24
Finished Jul 05 05:10:25 PM PDT 24
Peak memory 201700 kb
Host smart-07be5699-4aac-4986-90c4-e6fe04e1ed5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980097198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.2980097198
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3367993625
Short name T887
Test name
Test status
Simulation time 2026837872 ps
CPU time 1.91 seconds
Started Jul 05 05:10:16 PM PDT 24
Finished Jul 05 05:10:19 PM PDT 24
Peak memory 201848 kb
Host smart-33acf783-3671-40e2-a7db-360a711ef542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367993625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.3367993625
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.582243061
Short name T895
Test name
Test status
Simulation time 2040462876 ps
CPU time 1.99 seconds
Started Jul 05 05:10:26 PM PDT 24
Finished Jul 05 05:10:29 PM PDT 24
Peak memory 201744 kb
Host smart-02e04c2a-8213-4284-ad3a-821b72bf35c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582243061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.582243061
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3460648963
Short name T797
Test name
Test status
Simulation time 2095645386 ps
CPU time 1.09 seconds
Started Jul 05 05:10:19 PM PDT 24
Finished Jul 05 05:10:21 PM PDT 24
Peak memory 201684 kb
Host smart-96a1b375-8f34-4997-8c75-ab84edca2d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460648963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.3460648963
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.4150382377
Short name T888
Test name
Test status
Simulation time 2015047545 ps
CPU time 5.4 seconds
Started Jul 05 05:10:23 PM PDT 24
Finished Jul 05 05:10:29 PM PDT 24
Peak memory 201748 kb
Host smart-bedfc307-e41d-4cc4-bf8f-d3f7f573df25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150382377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.4150382377
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3427307260
Short name T851
Test name
Test status
Simulation time 2011428223 ps
CPU time 5.66 seconds
Started Jul 05 05:10:21 PM PDT 24
Finished Jul 05 05:10:27 PM PDT 24
Peak memory 201752 kb
Host smart-9f344716-c87b-4251-adce-c845a7fc1a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427307260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.3427307260
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2979822674
Short name T824
Test name
Test status
Simulation time 2021195438 ps
CPU time 3.04 seconds
Started Jul 05 05:10:25 PM PDT 24
Finished Jul 05 05:10:28 PM PDT 24
Peak memory 201752 kb
Host smart-e423976d-d2c1-41a0-94cb-2a74341306d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979822674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.2979822674
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2028286832
Short name T868
Test name
Test status
Simulation time 2016578136 ps
CPU time 5.92 seconds
Started Jul 05 05:10:21 PM PDT 24
Finished Jul 05 05:10:28 PM PDT 24
Peak memory 201852 kb
Host smart-b4befa0a-7074-45b5-bf7f-ccb506a7d1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028286832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.2028286832
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1590718401
Short name T818
Test name
Test status
Simulation time 2032458126 ps
CPU time 1.83 seconds
Started Jul 05 05:10:16 PM PDT 24
Finished Jul 05 05:10:19 PM PDT 24
Peak memory 201744 kb
Host smart-227a8f7c-4f6a-4d3c-86ae-3e5eba68402c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590718401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1590718401
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2969048211
Short name T823
Test name
Test status
Simulation time 2237799425 ps
CPU time 2.53 seconds
Started Jul 05 05:09:27 PM PDT 24
Finished Jul 05 05:09:31 PM PDT 24
Peak memory 202168 kb
Host smart-00c6b8b4-d725-401d-a25b-11b849e6669b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969048211 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2969048211
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3328230780
Short name T907
Test name
Test status
Simulation time 2053706182 ps
CPU time 6.15 seconds
Started Jul 05 05:09:28 PM PDT 24
Finished Jul 05 05:09:35 PM PDT 24
Peak memory 201972 kb
Host smart-c6182f55-efca-4502-a26f-fd608cd8edeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328230780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.3328230780
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1186173549
Short name T844
Test name
Test status
Simulation time 2011377681 ps
CPU time 5.94 seconds
Started Jul 05 05:09:31 PM PDT 24
Finished Jul 05 05:09:37 PM PDT 24
Peak memory 201644 kb
Host smart-1c01cd18-89d6-4f30-846a-5b3b68c29068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186173549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.1186173549
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2835771489
Short name T877
Test name
Test status
Simulation time 8542288751 ps
CPU time 20.16 seconds
Started Jul 05 05:09:25 PM PDT 24
Finished Jul 05 05:09:46 PM PDT 24
Peak memory 202264 kb
Host smart-5b9d36b6-d7a1-4004-aac3-c001d3e66d04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835771489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.2835771489
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3842614279
Short name T100
Test name
Test status
Simulation time 2216734133 ps
CPU time 4.97 seconds
Started Jul 05 05:09:20 PM PDT 24
Finished Jul 05 05:09:25 PM PDT 24
Peak memory 202252 kb
Host smart-73f3a6bf-6747-42d6-a4b0-83a5d79dd428
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842614279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.3842614279
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2721167514
Short name T892
Test name
Test status
Simulation time 42579362533 ps
CPU time 58.23 seconds
Started Jul 05 05:13:02 PM PDT 24
Finished Jul 05 05:14:02 PM PDT 24
Peak memory 202280 kb
Host smart-11747f0b-7339-45ba-bc9e-adfad743dc62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721167514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.2721167514
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1919507550
Short name T898
Test name
Test status
Simulation time 2128643709 ps
CPU time 2.07 seconds
Started Jul 05 05:09:30 PM PDT 24
Finished Jul 05 05:09:33 PM PDT 24
Peak memory 201832 kb
Host smart-f1aaf828-60b0-4f79-9fec-c505c5573686
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919507550 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1919507550
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.2381199486
Short name T320
Test name
Test status
Simulation time 2046402701 ps
CPU time 5.89 seconds
Started Jul 05 05:09:27 PM PDT 24
Finished Jul 05 05:09:34 PM PDT 24
Peak memory 201816 kb
Host smart-9d9eccbd-b1bd-4a0a-ad97-cfe6ed6577da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381199486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.2381199486
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3051523160
Short name T863
Test name
Test status
Simulation time 2051526388 ps
CPU time 2.14 seconds
Started Jul 05 05:09:30 PM PDT 24
Finished Jul 05 05:09:33 PM PDT 24
Peak memory 201732 kb
Host smart-4d560eec-9695-457c-a4e6-412f90f9fb35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051523160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.3051523160
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3394373535
Short name T20
Test name
Test status
Simulation time 8527405068 ps
CPU time 2.73 seconds
Started Jul 05 05:09:39 PM PDT 24
Finished Jul 05 05:09:43 PM PDT 24
Peak memory 202288 kb
Host smart-bf9b1cac-65d9-4379-91d7-f08ed05455b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394373535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3394373535
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.933590983
Short name T881
Test name
Test status
Simulation time 2045546192 ps
CPU time 3.15 seconds
Started Jul 05 05:09:26 PM PDT 24
Finished Jul 05 05:09:30 PM PDT 24
Peak memory 202024 kb
Host smart-3d20afa0-3095-42ff-9878-d9189a888ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933590983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors
.933590983
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3460116290
Short name T848
Test name
Test status
Simulation time 22199495313 ps
CPU time 30.06 seconds
Started Jul 05 05:09:30 PM PDT 24
Finished Jul 05 05:10:00 PM PDT 24
Peak memory 202320 kb
Host smart-a8cd3ab7-18c3-4988-b0b9-9c684774f1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460116290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3460116290
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3584040718
Short name T875
Test name
Test status
Simulation time 2150866628 ps
CPU time 2.26 seconds
Started Jul 05 05:09:28 PM PDT 24
Finished Jul 05 05:09:31 PM PDT 24
Peak memory 202028 kb
Host smart-b26004cf-97be-4a47-9324-949bd8cb415a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584040718 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3584040718
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2309945873
Short name T878
Test name
Test status
Simulation time 2101150120 ps
CPU time 1.49 seconds
Started Jul 05 05:09:26 PM PDT 24
Finished Jul 05 05:09:28 PM PDT 24
Peak memory 201900 kb
Host smart-a7cb3a93-0258-4e1b-8734-9b48cc7c39cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309945873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.2309945873
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.652512137
Short name T874
Test name
Test status
Simulation time 2071177274 ps
CPU time 1.22 seconds
Started Jul 05 05:09:26 PM PDT 24
Finished Jul 05 05:09:28 PM PDT 24
Peak memory 201672 kb
Host smart-39c29d97-5a47-48c5-ae39-71915e4cd8c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652512137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test
.652512137
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1678916717
Short name T821
Test name
Test status
Simulation time 7693918007 ps
CPU time 9.28 seconds
Started Jul 05 05:09:29 PM PDT 24
Finished Jul 05 05:09:39 PM PDT 24
Peak memory 202252 kb
Host smart-8dbaef78-c2d1-4372-a0a2-ea40a8c4d44e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678916717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.1678916717
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1644900294
Short name T905
Test name
Test status
Simulation time 2043986851 ps
CPU time 7.72 seconds
Started Jul 05 05:09:28 PM PDT 24
Finished Jul 05 05:09:36 PM PDT 24
Peak memory 202000 kb
Host smart-87a45017-2aa1-44f3-bbd7-b29d5f609c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644900294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1644900294
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.79801995
Short name T883
Test name
Test status
Simulation time 22207708251 ps
CPU time 29.41 seconds
Started Jul 05 05:09:26 PM PDT 24
Finished Jul 05 05:09:56 PM PDT 24
Peak memory 202228 kb
Host smart-834c3bc2-13f3-400e-b056-eb80d9cc0840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79801995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_tl_intg_err.79801995
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2345024405
Short name T795
Test name
Test status
Simulation time 2125831934 ps
CPU time 2.29 seconds
Started Jul 05 05:09:34 PM PDT 24
Finished Jul 05 05:09:37 PM PDT 24
Peak memory 201988 kb
Host smart-a475d200-5e21-4a8e-9c17-216fd5d51b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345024405 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2345024405
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.1336162739
Short name T319
Test name
Test status
Simulation time 2031426301 ps
CPU time 6.35 seconds
Started Jul 05 05:09:34 PM PDT 24
Finished Jul 05 05:09:41 PM PDT 24
Peak memory 201876 kb
Host smart-a8d78b83-136c-41a9-81de-494fdcf0886c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336162739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.1336162739
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2190360284
Short name T808
Test name
Test status
Simulation time 2013974128 ps
CPU time 5.45 seconds
Started Jul 05 05:09:55 PM PDT 24
Finished Jul 05 05:10:02 PM PDT 24
Peak memory 201852 kb
Host smart-fcec3324-3fcb-4b56-b313-e148c674f717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190360284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.2190360284
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.903067968
Short name T827
Test name
Test status
Simulation time 4692722056 ps
CPU time 8.33 seconds
Started Jul 05 05:10:24 PM PDT 24
Finished Jul 05 05:10:33 PM PDT 24
Peak memory 202052 kb
Host smart-8699e73a-29b8-42e5-a26d-4635bce0c0df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903067968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
sysrst_ctrl_same_csr_outstanding.903067968
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2873010955
Short name T833
Test name
Test status
Simulation time 2048022744 ps
CPU time 6.3 seconds
Started Jul 05 05:09:31 PM PDT 24
Finished Jul 05 05:09:38 PM PDT 24
Peak memory 202016 kb
Host smart-26571b2a-ce28-4ea7-b048-db963c97b352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873010955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.2873010955
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3354009154
Short name T849
Test name
Test status
Simulation time 22208419809 ps
CPU time 49.17 seconds
Started Jul 05 05:09:55 PM PDT 24
Finished Jul 05 05:10:44 PM PDT 24
Peak memory 202288 kb
Host smart-bd01076b-6d2b-491e-9e8f-ca0c9efcf488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354009154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.3354009154
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3683980157
Short name T900
Test name
Test status
Simulation time 2122229327 ps
CPU time 3.79 seconds
Started Jul 05 05:09:36 PM PDT 24
Finished Jul 05 05:09:41 PM PDT 24
Peak memory 201932 kb
Host smart-70183e83-52e6-4b9a-9696-4ba6a3fb57a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683980157 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3683980157
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2895320138
Short name T310
Test name
Test status
Simulation time 2056557841 ps
CPU time 2.22 seconds
Started Jul 05 05:09:33 PM PDT 24
Finished Jul 05 05:09:36 PM PDT 24
Peak memory 201972 kb
Host smart-b335e667-77e0-46b3-9fa2-2b79feec61e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895320138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.2895320138
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.375712022
Short name T845
Test name
Test status
Simulation time 2021091107 ps
CPU time 3.17 seconds
Started Jul 05 05:09:55 PM PDT 24
Finished Jul 05 05:09:58 PM PDT 24
Peak memory 201680 kb
Host smart-eaee8de9-0443-41d3-8873-f78bf531665f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375712022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test
.375712022
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3686938010
Short name T19
Test name
Test status
Simulation time 8566517916 ps
CPU time 21.09 seconds
Started Jul 05 05:09:32 PM PDT 24
Finished Jul 05 05:09:54 PM PDT 24
Peak memory 202264 kb
Host smart-c4df5714-de18-4faa-9509-e2d05fcba7f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686938010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.3686938010
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3931040112
Short name T86
Test name
Test status
Simulation time 22455305681 ps
CPU time 16.09 seconds
Started Jul 05 05:09:34 PM PDT 24
Finished Jul 05 05:09:51 PM PDT 24
Peak memory 202304 kb
Host smart-7266bbde-085d-4ca3-b372-05e6c4c1394c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931040112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.3931040112
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.389054452
Short name T538
Test name
Test status
Simulation time 3517048511 ps
CPU time 2.5 seconds
Started Jul 05 05:30:28 PM PDT 24
Finished Jul 05 05:30:31 PM PDT 24
Peak memory 201632 kb
Host smart-4067f95b-61d7-4056-ab5b-4fa60a9de95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389054452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.389054452
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2862496295
Short name T332
Test name
Test status
Simulation time 52022029959 ps
CPU time 135.88 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:32:43 PM PDT 24
Peak memory 201872 kb
Host smart-0c47f4b7-9b3c-4a69-8199-d39710b269ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862496295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.2862496295
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3425013908
Short name T243
Test name
Test status
Simulation time 2204506467 ps
CPU time 3.32 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:24 PM PDT 24
Peak memory 201636 kb
Host smart-b625083c-026e-4882-b480-43f5dd4136e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425013908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.3425013908
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2954150430
Short name T46
Test name
Test status
Simulation time 2544696743 ps
CPU time 2.6 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 201668 kb
Host smart-9381e324-bd13-49c0-8b1b-59db76cf2ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954150430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2954150430
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.387906936
Short name T668
Test name
Test status
Simulation time 4124149441 ps
CPU time 3.28 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:24 PM PDT 24
Peak memory 201644 kb
Host smart-8b0d9142-b714-4f05-85d9-652c363e559e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387906936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ec_pwr_on_rst.387906936
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2670107514
Short name T194
Test name
Test status
Simulation time 4090295501 ps
CPU time 7.84 seconds
Started Jul 05 05:30:18 PM PDT 24
Finished Jul 05 05:30:26 PM PDT 24
Peak memory 201656 kb
Host smart-6f20eb6c-650b-40d2-ae84-c26713374505
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670107514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.2670107514
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1500999125
Short name T381
Test name
Test status
Simulation time 2609981342 ps
CPU time 7.14 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:30:34 PM PDT 24
Peak memory 201556 kb
Host smart-84208d09-7cf4-4d2b-804b-c578dac5442d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500999125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1500999125
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3041538372
Short name T460
Test name
Test status
Simulation time 2460088211 ps
CPU time 3.82 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:25 PM PDT 24
Peak memory 201644 kb
Host smart-8caf3693-8fe2-481e-ade0-b6ddb4105989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041538372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3041538372
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.380450648
Short name T676
Test name
Test status
Simulation time 2268005693 ps
CPU time 3.46 seconds
Started Jul 05 05:30:21 PM PDT 24
Finished Jul 05 05:30:25 PM PDT 24
Peak memory 201648 kb
Host smart-341b22d2-db19-4413-b3f0-c9c183adedd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380450648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.380450648
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.2005308768
Short name T485
Test name
Test status
Simulation time 2509423940 ps
CPU time 6.67 seconds
Started Jul 05 05:30:22 PM PDT 24
Finished Jul 05 05:30:29 PM PDT 24
Peak memory 201536 kb
Host smart-10183891-d8a0-45b9-8181-9a785fdd227e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005308768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2005308768
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1351105617
Short name T288
Test name
Test status
Simulation time 22011547647 ps
CPU time 55.07 seconds
Started Jul 05 05:30:22 PM PDT 24
Finished Jul 05 05:31:17 PM PDT 24
Peak memory 221120 kb
Host smart-6d47da6c-d93a-4ce9-bbd3-d76222256b5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351105617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1351105617
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.1435360572
Short name T497
Test name
Test status
Simulation time 2115743723 ps
CPU time 3.17 seconds
Started Jul 05 05:30:19 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 201536 kb
Host smart-e768432c-acba-401d-a3e8-2b4cfae6f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435360572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.1435360572
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.3376176467
Short name T261
Test name
Test status
Simulation time 53073755990 ps
CPU time 37.81 seconds
Started Jul 05 05:30:24 PM PDT 24
Finished Jul 05 05:31:03 PM PDT 24
Peak memory 201928 kb
Host smart-8bc9c912-29a4-470e-aba6-d03e1e55d224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376176467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.3376176467
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1899587961
Short name T224
Test name
Test status
Simulation time 257327467014 ps
CPU time 121.9 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:32:29 PM PDT 24
Peak memory 218404 kb
Host smart-657a8c6c-5158-4e1c-895f-bea0a07f209e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899587961 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.1899587961
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3078937010
Short name T524
Test name
Test status
Simulation time 10300677173 ps
CPU time 4.5 seconds
Started Jul 05 05:30:18 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 201644 kb
Host smart-42d24229-9643-435e-b0ab-c45d1b4b7af1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078937010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.3078937010
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.2885327044
Short name T97
Test name
Test status
Simulation time 2059688622 ps
CPU time 1.38 seconds
Started Jul 05 05:30:27 PM PDT 24
Finished Jul 05 05:30:29 PM PDT 24
Peak memory 201644 kb
Host smart-7decafa3-f2dd-456b-9730-8e628314a6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885327044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.2885327044
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.492044070
Short name T710
Test name
Test status
Simulation time 61954419958 ps
CPU time 39.08 seconds
Started Jul 05 05:30:25 PM PDT 24
Finished Jul 05 05:31:05 PM PDT 24
Peak memory 201736 kb
Host smart-00ee5561-b135-4e02-a276-77a92335b567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492044070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.492044070
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3164206219
Short name T280
Test name
Test status
Simulation time 116003575382 ps
CPU time 40.2 seconds
Started Jul 05 05:30:24 PM PDT 24
Finished Jul 05 05:31:05 PM PDT 24
Peak memory 201896 kb
Host smart-40513c09-1b97-475f-9dc1-86c4afff78b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164206219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.3164206219
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1433838257
Short name T386
Test name
Test status
Simulation time 2414832503 ps
CPU time 3.55 seconds
Started Jul 05 05:30:19 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 201660 kb
Host smart-1a346bd0-36dc-4225-9436-6e53dd672aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433838257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1433838257
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1275130145
Short name T45
Test name
Test status
Simulation time 2589936228 ps
CPU time 1.09 seconds
Started Jul 05 05:30:25 PM PDT 24
Finished Jul 05 05:30:27 PM PDT 24
Peak memory 201600 kb
Host smart-5f07afda-fcd1-4cd6-aafb-3297b439f246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275130145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1275130145
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2073741510
Short name T717
Test name
Test status
Simulation time 26508956829 ps
CPU time 8.23 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:30:35 PM PDT 24
Peak memory 201912 kb
Host smart-c463700b-62ec-429d-942f-3eee7eacee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073741510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2073741510
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.450544639
Short name T763
Test name
Test status
Simulation time 2974309869 ps
CPU time 1.4 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:22 PM PDT 24
Peak memory 201636 kb
Host smart-0f52f1bc-f70e-413e-befb-cb1b8adc5cdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450544639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_ec_pwr_on_rst.450544639
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.546518572
Short name T75
Test name
Test status
Simulation time 2652256776 ps
CPU time 1.7 seconds
Started Jul 05 05:30:20 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 201652 kb
Host smart-f8ffcb3b-1fcf-4427-9b3d-25b3672e105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546518572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.546518572
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3975153877
Short name T514
Test name
Test status
Simulation time 2448566510 ps
CPU time 4.14 seconds
Started Jul 05 05:30:23 PM PDT 24
Finished Jul 05 05:30:28 PM PDT 24
Peak memory 201640 kb
Host smart-95efeaf0-98e1-4a8b-88da-4727fb67294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975153877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3975153877
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3043065354
Short name T496
Test name
Test status
Simulation time 2200873319 ps
CPU time 1.93 seconds
Started Jul 05 05:30:25 PM PDT 24
Finished Jul 05 05:30:28 PM PDT 24
Peak memory 201564 kb
Host smart-8c519442-8150-4ffb-91d4-8a4fc27d5deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043065354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.3043065354
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.2161466673
Short name T265
Test name
Test status
Simulation time 2511204512 ps
CPU time 7.42 seconds
Started Jul 05 05:30:18 PM PDT 24
Finished Jul 05 05:30:26 PM PDT 24
Peak memory 201644 kb
Host smart-d7066dca-5f73-4eb6-b96a-01c304b8a076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161466673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.2161466673
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.495833814
Short name T501
Test name
Test status
Simulation time 2128089104 ps
CPU time 1.72 seconds
Started Jul 05 05:30:21 PM PDT 24
Finished Jul 05 05:30:23 PM PDT 24
Peak memory 201516 kb
Host smart-e8862d10-59b7-4aad-9f8c-19667ef0072a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495833814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.495833814
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.723850590
Short name T754
Test name
Test status
Simulation time 10147697605 ps
CPU time 24.13 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:30:51 PM PDT 24
Peak memory 201704 kb
Host smart-847d4f8c-63f1-4189-bf98-a1ee9c44f5c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723850590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_str
ess_all.723850590
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3539129304
Short name T146
Test name
Test status
Simulation time 282452684971 ps
CPU time 29.57 seconds
Started Jul 05 05:30:22 PM PDT 24
Finished Jul 05 05:30:53 PM PDT 24
Peak memory 210356 kb
Host smart-f26071c5-2026-487a-adf5-477870caba22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539129304 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.3539129304
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3284114113
Short name T697
Test name
Test status
Simulation time 3949879401 ps
CPU time 1.84 seconds
Started Jul 05 05:30:23 PM PDT 24
Finished Jul 05 05:30:25 PM PDT 24
Peak memory 201652 kb
Host smart-42100283-01ee-4536-b024-753db08d64e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284114113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.3284114113
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.2633253389
Short name T786
Test name
Test status
Simulation time 2052276148 ps
CPU time 1.31 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:30:55 PM PDT 24
Peak memory 201660 kb
Host smart-62b16708-e9cb-47ec-bd50-2657120cf6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633253389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.2633253389
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3923357765
Short name T287
Test name
Test status
Simulation time 104793387474 ps
CPU time 33.19 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:31:28 PM PDT 24
Peak memory 201928 kb
Host smart-d49ca64d-c179-4313-acc1-7f349f3b2964
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923357765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.3923357765
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.821387320
Short name T237
Test name
Test status
Simulation time 37527804119 ps
CPU time 50.3 seconds
Started Jul 05 05:30:59 PM PDT 24
Finished Jul 05 05:31:50 PM PDT 24
Peak memory 201968 kb
Host smart-f1f12717-e949-4630-826d-c5929b8bf5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821387320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_wi
th_pre_cond.821387320
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2513846588
Short name T772
Test name
Test status
Simulation time 4227401777 ps
CPU time 10.04 seconds
Started Jul 05 05:30:46 PM PDT 24
Finished Jul 05 05:30:57 PM PDT 24
Peak memory 201616 kb
Host smart-9da58479-31f5-4073-93be-b8540cea56bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513846588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.2513846588
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.2773434857
Short name T225
Test name
Test status
Simulation time 2779643471 ps
CPU time 7.39 seconds
Started Jul 05 05:30:56 PM PDT 24
Finished Jul 05 05:31:04 PM PDT 24
Peak memory 201608 kb
Host smart-a5bba481-79fb-4f7a-bb3c-b8a9130355b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773434857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.2773434857
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.796723130
Short name T262
Test name
Test status
Simulation time 2621307406 ps
CPU time 4.18 seconds
Started Jul 05 05:30:49 PM PDT 24
Finished Jul 05 05:30:53 PM PDT 24
Peak memory 201660 kb
Host smart-89f4ec39-8a76-4247-b287-0b54dbfcea88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796723130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.796723130
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1489968087
Short name T464
Test name
Test status
Simulation time 2486583939 ps
CPU time 2.13 seconds
Started Jul 05 05:30:44 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201572 kb
Host smart-865aa299-3df8-46ed-8e1f-a956318f1286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489968087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1489968087
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3062856148
Short name T149
Test name
Test status
Simulation time 2178984300 ps
CPU time 0.9 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:46 PM PDT 24
Peak memory 201608 kb
Host smart-2bd11e3c-805a-4d9d-9d23-23cc29b2e86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062856148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3062856148
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3938214167
Short name T296
Test name
Test status
Simulation time 2519385463 ps
CPU time 4.21 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:49 PM PDT 24
Peak memory 201660 kb
Host smart-5b6bcd34-e4d5-437f-a2e8-b2804506d830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938214167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3938214167
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.437383948
Short name T427
Test name
Test status
Simulation time 2113937513 ps
CPU time 6.13 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:51 PM PDT 24
Peak memory 201576 kb
Host smart-d454931e-3be1-4a21-991e-4660044a7317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437383948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.437383948
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.2727695160
Short name T292
Test name
Test status
Simulation time 13143041586 ps
CPU time 8.73 seconds
Started Jul 05 05:30:55 PM PDT 24
Finished Jul 05 05:31:05 PM PDT 24
Peak memory 201576 kb
Host smart-678d20b9-25ef-404d-b7a5-fd79352b59d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727695160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.2727695160
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1866840748
Short name T73
Test name
Test status
Simulation time 54839650145 ps
CPU time 136.79 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:33:11 PM PDT 24
Peak memory 218408 kb
Host smart-063954d5-c340-4255-aeb4-9ebab30ebb52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866840748 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1866840748
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3394090628
Short name T663
Test name
Test status
Simulation time 996405686368 ps
CPU time 53.33 seconds
Started Jul 05 05:30:51 PM PDT 24
Finished Jul 05 05:31:45 PM PDT 24
Peak memory 201596 kb
Host smart-9a3cf3be-0ce7-4028-9e4f-02ad7efa3b10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394090628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.3394090628
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1296067825
Short name T436
Test name
Test status
Simulation time 2020493048 ps
CPU time 3.72 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:30:57 PM PDT 24
Peak memory 201668 kb
Host smart-f1ae34e4-2715-4c20-af0a-484c17ce25e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296067825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1296067825
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.921656224
Short name T660
Test name
Test status
Simulation time 4018368531 ps
CPU time 5.49 seconds
Started Jul 05 05:30:51 PM PDT 24
Finished Jul 05 05:30:58 PM PDT 24
Peak memory 201728 kb
Host smart-1009de7a-4b03-4de3-b702-0b2d2006e49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921656224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.921656224
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1393535128
Short name T127
Test name
Test status
Simulation time 23431020836 ps
CPU time 64.33 seconds
Started Jul 05 05:30:55 PM PDT 24
Finished Jul 05 05:32:01 PM PDT 24
Peak memory 201808 kb
Host smart-9945173d-25d0-40da-b7a0-1a9ff7f43b98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393535128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.1393535128
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1249357950
Short name T632
Test name
Test status
Simulation time 40258294092 ps
CPU time 95.36 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:32:28 PM PDT 24
Peak memory 201832 kb
Host smart-f52f21f5-00e6-4a52-bd7a-89ee318bd6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249357950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.1249357950
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2575414845
Short name T721
Test name
Test status
Simulation time 2844173790 ps
CPU time 4.07 seconds
Started Jul 05 05:30:54 PM PDT 24
Finished Jul 05 05:31:00 PM PDT 24
Peak memory 201640 kb
Host smart-68f53650-909f-4a32-bbca-4eb53b3f7d3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575414845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.2575414845
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1034983252
Short name T692
Test name
Test status
Simulation time 2589810977 ps
CPU time 3.37 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:30:58 PM PDT 24
Peak memory 201652 kb
Host smart-c21141ef-a4a7-478d-a197-3e9c9dd286ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034983252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.1034983252
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1805050190
Short name T621
Test name
Test status
Simulation time 2614080199 ps
CPU time 7.86 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:31:01 PM PDT 24
Peak memory 201552 kb
Host smart-0f903b9c-6851-420d-9921-e11766936746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805050190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1805050190
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1916809132
Short name T677
Test name
Test status
Simulation time 2455003390 ps
CPU time 8.01 seconds
Started Jul 05 05:30:59 PM PDT 24
Finished Jul 05 05:31:08 PM PDT 24
Peak memory 201660 kb
Host smart-e52a8a93-14bc-49e2-9215-4db605fa8f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916809132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1916809132
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.414982121
Short name T445
Test name
Test status
Simulation time 2205637943 ps
CPU time 2.09 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:30:57 PM PDT 24
Peak memory 201648 kb
Host smart-42e424ae-01fc-47cd-923f-bb49fea0295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414982121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.414982121
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4179091733
Short name T564
Test name
Test status
Simulation time 2514434093 ps
CPU time 3.75 seconds
Started Jul 05 05:30:51 PM PDT 24
Finished Jul 05 05:30:56 PM PDT 24
Peak memory 201668 kb
Host smart-f4ec00b0-4e51-4bdf-9a2c-1117cbfa1e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179091733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.4179091733
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.1967532443
Short name T592
Test name
Test status
Simulation time 2112982854 ps
CPU time 5.82 seconds
Started Jul 05 05:30:51 PM PDT 24
Finished Jul 05 05:30:57 PM PDT 24
Peak memory 201528 kb
Host smart-9fc823a5-fb12-4799-8ed8-110322dbbc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967532443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.1967532443
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.2448488897
Short name T326
Test name
Test status
Simulation time 231793949938 ps
CPU time 149.01 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:33:23 PM PDT 24
Peak memory 201936 kb
Host smart-aeeb8978-3db7-42c6-96f9-e19f478ad379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448488897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.2448488897
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2329299649
Short name T577
Test name
Test status
Simulation time 12956109970 ps
CPU time 34.46 seconds
Started Jul 05 05:30:51 PM PDT 24
Finished Jul 05 05:31:26 PM PDT 24
Peak memory 218444 kb
Host smart-90a0a269-b4af-4339-b3e5-51ff7f92a655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329299649 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2329299649
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.992202020
Short name T475
Test name
Test status
Simulation time 5932441747 ps
CPU time 3 seconds
Started Jul 05 05:30:56 PM PDT 24
Finished Jul 05 05:31:00 PM PDT 24
Peak memory 201644 kb
Host smart-e5ff9a3d-3639-47e4-afbe-be19c8000c7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992202020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ultra_low_pwr.992202020
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1316133869
Short name T725
Test name
Test status
Simulation time 2010163871 ps
CPU time 5.89 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:31:00 PM PDT 24
Peak memory 201640 kb
Host smart-b9794f08-57fe-48e7-b60a-7c7cf22fe140
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316133869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1316133869
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3699847624
Short name T220
Test name
Test status
Simulation time 3721057182 ps
CPU time 5.68 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:31:00 PM PDT 24
Peak memory 201728 kb
Host smart-07154d50-726e-4b7b-88ca-a20693df5309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699847624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3
699847624
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.3822813258
Short name T63
Test name
Test status
Simulation time 90774117818 ps
CPU time 14.74 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:31:07 PM PDT 24
Peak memory 201920 kb
Host smart-19ebafe8-987d-449f-86cf-79cac30384e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822813258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.3822813258
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.274434292
Short name T391
Test name
Test status
Simulation time 3491726570 ps
CPU time 3 seconds
Started Jul 05 05:30:54 PM PDT 24
Finished Jul 05 05:30:59 PM PDT 24
Peak memory 201652 kb
Host smart-bac5affe-5272-4e56-a4eb-dce1d9ea2108
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274434292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ec_pwr_on_rst.274434292
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.252527741
Short name T231
Test name
Test status
Simulation time 4005704754 ps
CPU time 6.89 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:31:01 PM PDT 24
Peak memory 201624 kb
Host smart-9ed442f0-b50a-43e3-9191-54276eb21797
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252527741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctr
l_edge_detect.252527741
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.4213131469
Short name T480
Test name
Test status
Simulation time 2477761467 ps
CPU time 2.44 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:30:56 PM PDT 24
Peak memory 201660 kb
Host smart-c3f3b4e5-e8c7-4be7-9fce-19f3ca08c3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213131469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.4213131469
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.2787265873
Short name T443
Test name
Test status
Simulation time 2155741640 ps
CPU time 3.4 seconds
Started Jul 05 05:30:56 PM PDT 24
Finished Jul 05 05:31:01 PM PDT 24
Peak memory 201496 kb
Host smart-ff3318f9-5a49-4b08-a567-6af436f033c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787265873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.2787265873
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2492985540
Short name T673
Test name
Test status
Simulation time 2526743747 ps
CPU time 2.24 seconds
Started Jul 05 05:30:54 PM PDT 24
Finished Jul 05 05:30:58 PM PDT 24
Peak memory 201672 kb
Host smart-171409f5-369e-4cc9-a89a-8d75750d4d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492985540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.2492985540
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.537838670
Short name T581
Test name
Test status
Simulation time 2119174458 ps
CPU time 3.57 seconds
Started Jul 05 05:30:51 PM PDT 24
Finished Jul 05 05:30:55 PM PDT 24
Peak memory 201528 kb
Host smart-b80d0d6f-850e-4a02-ba3d-6b3801d1a6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537838670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.537838670
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.3017917524
Short name T105
Test name
Test status
Simulation time 316052121169 ps
CPU time 401.81 seconds
Started Jul 05 05:30:55 PM PDT 24
Finished Jul 05 05:37:38 PM PDT 24
Peak memory 201696 kb
Host smart-cf918c29-3c88-4859-9547-f06d32367da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017917524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.3017917524
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2832943649
Short name T440
Test name
Test status
Simulation time 7466436099 ps
CPU time 6.47 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:31:01 PM PDT 24
Peak memory 201568 kb
Host smart-78bb2e7b-e162-4fad-b461-f26dbff57f23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832943649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.2832943649
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.4228107771
Short name T394
Test name
Test status
Simulation time 2039742515 ps
CPU time 1.85 seconds
Started Jul 05 05:31:03 PM PDT 24
Finished Jul 05 05:31:07 PM PDT 24
Peak memory 201668 kb
Host smart-1f9df6c2-8aaf-47d6-a043-68d458d9da15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228107771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.4228107771
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.814743951
Short name T671
Test name
Test status
Simulation time 3893944053 ps
CPU time 6.24 seconds
Started Jul 05 05:30:52 PM PDT 24
Finished Jul 05 05:31:00 PM PDT 24
Peak memory 201732 kb
Host smart-58399172-03a2-449c-ae0c-37ae36a6b5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814743951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.814743951
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.2419374680
Short name T361
Test name
Test status
Simulation time 94127005846 ps
CPU time 238.1 seconds
Started Jul 05 05:30:56 PM PDT 24
Finished Jul 05 05:34:55 PM PDT 24
Peak memory 201880 kb
Host smart-40301030-327b-4b3c-8513-728eb59ae6fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419374680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.2419374680
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1529356582
Short name T554
Test name
Test status
Simulation time 27107447570 ps
CPU time 11.52 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:14 PM PDT 24
Peak memory 201920 kb
Host smart-bcb2dd38-2b94-4eef-bffe-c9aa47eb24a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529356582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.1529356582
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.119902139
Short name T602
Test name
Test status
Simulation time 4120880802 ps
CPU time 5.87 seconds
Started Jul 05 05:30:58 PM PDT 24
Finished Jul 05 05:31:04 PM PDT 24
Peak memory 201624 kb
Host smart-20f73b5a-cbd5-428d-9221-39da081e7d17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119902139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_ec_pwr_on_rst.119902139
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2150623027
Short name T736
Test name
Test status
Simulation time 3021438328 ps
CPU time 3.36 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:06 PM PDT 24
Peak memory 201664 kb
Host smart-113234f7-a121-4e85-8985-97d41e3f5453
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150623027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.2150623027
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.531586253
Short name T390
Test name
Test status
Simulation time 2618300178 ps
CPU time 4.15 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:30:58 PM PDT 24
Peak memory 201632 kb
Host smart-fd775982-7a0a-4934-a53c-ab1a6f567be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531586253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.531586253
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.2484377780
Short name T456
Test name
Test status
Simulation time 2450452336 ps
CPU time 7.66 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:31:03 PM PDT 24
Peak memory 201660 kb
Host smart-3dc2096a-5ccb-4910-b196-d9c1acb7b12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484377780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.2484377780
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1777610529
Short name T395
Test name
Test status
Simulation time 2160374861 ps
CPU time 5.38 seconds
Started Jul 05 05:30:50 PM PDT 24
Finished Jul 05 05:30:56 PM PDT 24
Peak memory 201628 kb
Host smart-27780ec7-0ce9-42e3-8bea-bbc491409467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777610529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1777610529
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1925223179
Short name T173
Test name
Test status
Simulation time 2760725186 ps
CPU time 1.13 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:30:56 PM PDT 24
Peak memory 201640 kb
Host smart-1b56cc11-019c-42bd-ab63-23ebaf2372da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925223179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1925223179
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.680041330
Short name T147
Test name
Test status
Simulation time 2113555137 ps
CPU time 6.05 seconds
Started Jul 05 05:30:54 PM PDT 24
Finished Jul 05 05:31:02 PM PDT 24
Peak memory 201524 kb
Host smart-77338660-a239-49f2-9cf4-b45dc646413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680041330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.680041330
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.92327417
Short name T628
Test name
Test status
Simulation time 6859851478 ps
CPU time 1.73 seconds
Started Jul 05 05:31:03 PM PDT 24
Finished Jul 05 05:31:07 PM PDT 24
Peak memory 201564 kb
Host smart-4bf7c489-7809-4d27-839e-a04e6e4bea95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92327417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_str
ess_all.92327417
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1809142324
Short name T298
Test name
Test status
Simulation time 209745075574 ps
CPU time 130.06 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:33:15 PM PDT 24
Peak memory 210364 kb
Host smart-df4b2528-97f1-4b9a-93af-5768068074f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809142324 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.1809142324
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.320054551
Short name T67
Test name
Test status
Simulation time 4551707914 ps
CPU time 6.48 seconds
Started Jul 05 05:30:53 PM PDT 24
Finished Jul 05 05:31:01 PM PDT 24
Peak memory 201640 kb
Host smart-09a53e72-42fc-4c1f-8d26-6874d20ff3ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320054551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_ultra_low_pwr.320054551
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2882962484
Short name T696
Test name
Test status
Simulation time 2016646387 ps
CPU time 5.72 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:11 PM PDT 24
Peak memory 201564 kb
Host smart-986a5fa1-5b4d-4862-b109-514c35af4a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882962484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2882962484
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3403032763
Short name T269
Test name
Test status
Simulation time 3193909895 ps
CPU time 2.72 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:05 PM PDT 24
Peak memory 201684 kb
Host smart-2ab91cae-ce6f-4a43-9d34-ec181b40a429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403032763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.3
403032763
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1446430732
Short name T640
Test name
Test status
Simulation time 113089055862 ps
CPU time 79.11 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:32:22 PM PDT 24
Peak memory 201928 kb
Host smart-17576827-1f8a-4e65-acef-5af48543b9f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446430732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1446430732
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2177928484
Short name T407
Test name
Test status
Simulation time 4575437495 ps
CPU time 3.59 seconds
Started Jul 05 05:31:00 PM PDT 24
Finished Jul 05 05:31:05 PM PDT 24
Peak memory 201628 kb
Host smart-19718595-a7f0-48dc-a093-422e04a3ab42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177928484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.2177928484
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2788782876
Short name T534
Test name
Test status
Simulation time 3199192621 ps
CPU time 1.61 seconds
Started Jul 05 05:31:04 PM PDT 24
Finished Jul 05 05:31:07 PM PDT 24
Peak memory 201612 kb
Host smart-64f3e038-9d03-4c9f-bcba-9e6c6e6e7231
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788782876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2788782876
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2817272065
Short name T76
Test name
Test status
Simulation time 2630118593 ps
CPU time 2.26 seconds
Started Jul 05 05:31:11 PM PDT 24
Finished Jul 05 05:31:14 PM PDT 24
Peak memory 201640 kb
Host smart-f9dd4a01-e326-428f-a6b2-aa5301ebc08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817272065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.2817272065
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.245826360
Short name T70
Test name
Test status
Simulation time 2464907832 ps
CPU time 6.76 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:11 PM PDT 24
Peak memory 201644 kb
Host smart-fd5c7ee2-270d-4f6b-9700-193e6c075ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245826360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.245826360
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3556830176
Short name T266
Test name
Test status
Simulation time 2192263895 ps
CPU time 6.34 seconds
Started Jul 05 05:31:00 PM PDT 24
Finished Jul 05 05:31:08 PM PDT 24
Peak memory 201608 kb
Host smart-120749d1-c5ac-4000-9929-698fe16cfb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556830176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3556830176
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2386944550
Short name T658
Test name
Test status
Simulation time 2516867396 ps
CPU time 3.11 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:08 PM PDT 24
Peak memory 201636 kb
Host smart-f4025f6d-232d-4aff-87c6-6d63e40ecb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386944550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.2386944550
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.4230785098
Short name T590
Test name
Test status
Simulation time 2111542024 ps
CPU time 6.36 seconds
Started Jul 05 05:31:00 PM PDT 24
Finished Jul 05 05:31:08 PM PDT 24
Peak memory 201528 kb
Host smart-4781cf68-f9fc-4c97-88be-e4296e5294cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230785098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.4230785098
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.913707519
Short name T226
Test name
Test status
Simulation time 11798554129 ps
CPU time 7.72 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201592 kb
Host smart-c822ef2c-c61a-4ad2-9066-fb993ded9602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913707519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_st
ress_all.913707519
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1395056745
Short name T130
Test name
Test status
Simulation time 65107925738 ps
CPU time 43.62 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:46 PM PDT 24
Peak memory 212536 kb
Host smart-7ff23e08-8ec9-4f00-9cf9-e2fe4fbfb370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395056745 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.1395056745
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2931844654
Short name T374
Test name
Test status
Simulation time 815909174585 ps
CPU time 6.66 seconds
Started Jul 05 05:31:03 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201640 kb
Host smart-527d74c9-fd09-4e76-beca-b486cf2c1796
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931844654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.2931844654
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.364617770
Short name T98
Test name
Test status
Simulation time 2011184173 ps
CPU time 5.78 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:08 PM PDT 24
Peak memory 201660 kb
Host smart-1728b912-8534-40f7-9c9e-9f8bb35a92d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364617770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.364617770
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.4228398655
Short name T533
Test name
Test status
Simulation time 3105117818 ps
CPU time 8.62 seconds
Started Jul 05 05:31:00 PM PDT 24
Finished Jul 05 05:31:10 PM PDT 24
Peak memory 201708 kb
Host smart-1ec92221-4302-42f2-8f7e-b5261a2e8233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228398655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.4
228398655
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.284463913
Short name T354
Test name
Test status
Simulation time 55137678276 ps
CPU time 37.49 seconds
Started Jul 05 05:31:03 PM PDT 24
Finished Jul 05 05:31:42 PM PDT 24
Peak memory 201844 kb
Host smart-92f15700-e257-45a9-9a52-867200bcc326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284463913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi
th_pre_cond.284463913
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3730511651
Short name T730
Test name
Test status
Simulation time 3420422516 ps
CPU time 2.64 seconds
Started Jul 05 05:31:11 PM PDT 24
Finished Jul 05 05:31:14 PM PDT 24
Peak memory 201648 kb
Host smart-01eddce4-b934-488e-9363-ba5bdd68797c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730511651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.3730511651
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.1578625499
Short name T193
Test name
Test status
Simulation time 3127596313 ps
CPU time 2.73 seconds
Started Jul 05 05:31:12 PM PDT 24
Finished Jul 05 05:31:15 PM PDT 24
Peak memory 201672 kb
Host smart-00c49c18-ed0f-4447-87aa-2076b5554dc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578625499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.1578625499
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.580729616
Short name T413
Test name
Test status
Simulation time 2616757524 ps
CPU time 4.22 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:06 PM PDT 24
Peak memory 201580 kb
Host smart-83922816-a9b1-46d2-9da9-f2f46eb0be66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580729616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.580729616
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1914244085
Short name T666
Test name
Test status
Simulation time 2459144026 ps
CPU time 4.39 seconds
Started Jul 05 05:31:00 PM PDT 24
Finished Jul 05 05:31:05 PM PDT 24
Peak memory 201648 kb
Host smart-f9201c69-4eef-4984-a3e6-81e6c33f34d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914244085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1914244085
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.227381541
Short name T428
Test name
Test status
Simulation time 2129970940 ps
CPU time 6.07 seconds
Started Jul 05 05:31:03 PM PDT 24
Finished Jul 05 05:31:11 PM PDT 24
Peak memory 201440 kb
Host smart-3d710266-ff84-425c-8dcf-bc3404fe14ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227381541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.227381541
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.3934009717
Short name T420
Test name
Test status
Simulation time 2608435026 ps
CPU time 1.19 seconds
Started Jul 05 05:31:05 PM PDT 24
Finished Jul 05 05:31:07 PM PDT 24
Peak memory 201640 kb
Host smart-bf782ddb-da76-488b-93ab-e68dc233ed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934009717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.3934009717
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.1387585333
Short name T711
Test name
Test status
Simulation time 2143008821 ps
CPU time 1.34 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:03 PM PDT 24
Peak memory 201500 kb
Host smart-01230297-7f93-48d7-b920-2aeb2754bda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387585333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.1387585333
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.3028318453
Short name T372
Test name
Test status
Simulation time 13647191843 ps
CPU time 9.54 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 201680 kb
Host smart-5dd36116-2d65-4fd1-a545-69264117a38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028318453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.3028318453
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2661144622
Short name T255
Test name
Test status
Simulation time 8361536684 ps
CPU time 2.49 seconds
Started Jul 05 05:31:00 PM PDT 24
Finished Jul 05 05:31:03 PM PDT 24
Peak memory 201640 kb
Host smart-e36194a6-fba7-493e-a101-567899cd624c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661144622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.2661144622
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.978344547
Short name T457
Test name
Test status
Simulation time 2012183357 ps
CPU time 5.66 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:15 PM PDT 24
Peak memory 201664 kb
Host smart-c6baed36-ffac-42e7-9c29-4f954383bf04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978344547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.978344547
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.736218641
Short name T51
Test name
Test status
Simulation time 3305644364 ps
CPU time 8.6 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:11 PM PDT 24
Peak memory 201728 kb
Host smart-dca53366-41e2-4e57-9506-0c74962eae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736218641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.736218641
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2489890077
Short name T198
Test name
Test status
Simulation time 94949678781 ps
CPU time 50.21 seconds
Started Jul 05 05:31:12 PM PDT 24
Finished Jul 05 05:32:03 PM PDT 24
Peak memory 201848 kb
Host smart-aa120a28-dd71-492c-a614-f42385da146b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489890077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.2489890077
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1849062550
Short name T368
Test name
Test status
Simulation time 17598430131 ps
CPU time 13.28 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:18 PM PDT 24
Peak memory 201812 kb
Host smart-4b806c65-e8e1-4d38-b276-a97c8c699ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849062550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.1849062550
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1370502420
Short name T455
Test name
Test status
Simulation time 3986231769 ps
CPU time 1.99 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:07 PM PDT 24
Peak memory 201628 kb
Host smart-21e5e5f2-e3d6-47d1-a703-8f50dbee700f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370502420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.1370502420
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.2020997649
Short name T36
Test name
Test status
Simulation time 5629928921 ps
CPU time 3.77 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:09 PM PDT 24
Peak memory 201668 kb
Host smart-31ee6fa7-2a79-4af3-b6fa-72ba4097973b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020997649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.2020997649
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2947254669
Short name T382
Test name
Test status
Simulation time 2622174618 ps
CPU time 2.31 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:05 PM PDT 24
Peak memory 201660 kb
Host smart-c47ca396-0b60-4c38-ad06-96bd1a93edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947254669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.2947254669
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2217884409
Short name T739
Test name
Test status
Simulation time 2492965230 ps
CPU time 1.99 seconds
Started Jul 05 05:31:11 PM PDT 24
Finished Jul 05 05:31:14 PM PDT 24
Peak memory 201640 kb
Host smart-38daff48-ea36-46fd-9ce7-9684ed7d1f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217884409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2217884409
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1144961512
Short name T56
Test name
Test status
Simulation time 2130598824 ps
CPU time 6.19 seconds
Started Jul 05 05:31:02 PM PDT 24
Finished Jul 05 05:31:10 PM PDT 24
Peak memory 201580 kb
Host smart-bca68412-38dc-4522-af68-62e2b5389089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144961512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1144961512
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.3813447714
Short name T691
Test name
Test status
Simulation time 2511977591 ps
CPU time 5.64 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:08 PM PDT 24
Peak memory 201536 kb
Host smart-1eb6e0ac-a2ad-4290-84f1-8ba79f71e957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813447714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3813447714
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2465238400
Short name T650
Test name
Test status
Simulation time 2128324811 ps
CPU time 1.99 seconds
Started Jul 05 05:31:03 PM PDT 24
Finished Jul 05 05:31:07 PM PDT 24
Peak memory 201556 kb
Host smart-bf212990-56d7-4171-bda2-e05fd3ad0c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465238400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2465238400
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.3478102202
Short name T201
Test name
Test status
Simulation time 10932862290 ps
CPU time 5.04 seconds
Started Jul 05 05:31:01 PM PDT 24
Finished Jul 05 05:31:08 PM PDT 24
Peak memory 201664 kb
Host smart-cf59192a-e3fb-4a5d-bdf9-db09d87dac12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478102202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.3478102202
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2972252397
Short name T733
Test name
Test status
Simulation time 75595860667 ps
CPU time 47.19 seconds
Started Jul 05 05:31:06 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 218408 kb
Host smart-f89a5e05-0574-4ce9-b3a4-ef1bb591c335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972252397 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.2972252397
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1113594889
Short name T109
Test name
Test status
Simulation time 429985009650 ps
CPU time 12.36 seconds
Started Jul 05 05:31:04 PM PDT 24
Finished Jul 05 05:31:18 PM PDT 24
Peak memory 201640 kb
Host smart-007ebac8-9109-449d-8394-8434ad3e8032
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113594889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.1113594889
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1032671361
Short name T458
Test name
Test status
Simulation time 2023754136 ps
CPU time 1.91 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:31:17 PM PDT 24
Peak memory 201656 kb
Host smart-59ca24ed-744d-47ee-af2a-9d3598797364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032671361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1032671361
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3445220305
Short name T172
Test name
Test status
Simulation time 3544844293 ps
CPU time 9.16 seconds
Started Jul 05 05:31:10 PM PDT 24
Finished Jul 05 05:31:20 PM PDT 24
Peak memory 201712 kb
Host smart-fdd71fee-8b20-476a-b486-f4347ccdead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445220305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.3
445220305
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.1275293875
Short name T126
Test name
Test status
Simulation time 83266297848 ps
CPU time 218.41 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:34:54 PM PDT 24
Peak memory 201804 kb
Host smart-fa561989-7de3-4ad8-9030-a1e3cf4acafe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275293875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.1275293875
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2643174342
Short name T414
Test name
Test status
Simulation time 3178568035 ps
CPU time 8.49 seconds
Started Jul 05 05:31:09 PM PDT 24
Finished Jul 05 05:31:18 PM PDT 24
Peak memory 201620 kb
Host smart-6b37d91d-be3e-4135-bf25-7092e48b13a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643174342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.2643174342
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.859548021
Short name T259
Test name
Test status
Simulation time 3912644760 ps
CPU time 2.15 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201696 kb
Host smart-4cd4c376-3d71-499f-a0b4-8ad96985f2c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859548021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctr
l_edge_detect.859548021
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.272584227
Short name T744
Test name
Test status
Simulation time 2617435131 ps
CPU time 4.07 seconds
Started Jul 05 05:31:10 PM PDT 24
Finished Jul 05 05:31:15 PM PDT 24
Peak memory 201656 kb
Host smart-cdf7a447-9293-4253-a0b5-f5405026caf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272584227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.272584227
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1187141268
Short name T412
Test name
Test status
Simulation time 2466426370 ps
CPU time 7.73 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:31:23 PM PDT 24
Peak memory 201644 kb
Host smart-43df05de-9440-4dce-9d30-903186efd69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187141268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.1187141268
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3272561376
Short name T667
Test name
Test status
Simulation time 2212980066 ps
CPU time 2.05 seconds
Started Jul 05 05:31:10 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 201652 kb
Host smart-389e43ac-ebc9-47a5-9134-65bc76121f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272561376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3272561376
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2406712966
Short name T587
Test name
Test status
Simulation time 2525759772 ps
CPU time 2.44 seconds
Started Jul 05 05:31:10 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 201644 kb
Host smart-655fe639-7575-484d-bdbd-967aa8ec0f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406712966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2406712966
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.2694994382
Short name T572
Test name
Test status
Simulation time 2117660447 ps
CPU time 3.95 seconds
Started Jul 05 05:31:09 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 201436 kb
Host smart-8244315f-fa6b-4b3d-bcd7-ea08722d80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694994382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.2694994382
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.644384283
Short name T140
Test name
Test status
Simulation time 7085642471 ps
CPU time 1.51 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:10 PM PDT 24
Peak memory 201636 kb
Host smart-3457a6b0-13cf-43b5-b0b8-65f22e052a7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644384283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ultra_low_pwr.644384283
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3839851484
Short name T58
Test name
Test status
Simulation time 2010982346 ps
CPU time 5.23 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:14 PM PDT 24
Peak memory 201632 kb
Host smart-6cab1716-0920-4132-866f-db6fcbab09e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839851484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3839851484
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3594714798
Short name T558
Test name
Test status
Simulation time 3705391905 ps
CPU time 2.15 seconds
Started Jul 05 05:31:09 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201728 kb
Host smart-b4fa78d5-bbe1-42a8-9269-b717f1a44827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594714798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.3
594714798
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3766695849
Short name T286
Test name
Test status
Simulation time 84541968804 ps
CPU time 108.7 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:32:58 PM PDT 24
Peak memory 201872 kb
Host smart-3996d2d8-2337-47fe-ad37-c1f4a6c69413
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766695849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3766695849
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.4286774433
Short name T500
Test name
Test status
Simulation time 3736474524 ps
CPU time 9.66 seconds
Started Jul 05 05:31:09 PM PDT 24
Finished Jul 05 05:31:20 PM PDT 24
Peak memory 201660 kb
Host smart-ba5b9f79-87a2-4b5a-ac2e-7455049a5a7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286774433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.4286774433
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.2995916526
Short name T188
Test name
Test status
Simulation time 3085763684 ps
CPU time 6.65 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:31:22 PM PDT 24
Peak memory 201644 kb
Host smart-7e5479a7-520c-499d-8723-e1bf0d4886ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995916526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.2995916526
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2765076683
Short name T519
Test name
Test status
Simulation time 2628453124 ps
CPU time 2.4 seconds
Started Jul 05 05:31:09 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201648 kb
Host smart-d75b5560-5752-4adf-a296-64285c822d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765076683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.2765076683
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2348895557
Short name T702
Test name
Test status
Simulation time 2491470412 ps
CPU time 2.01 seconds
Started Jul 05 05:31:15 PM PDT 24
Finished Jul 05 05:31:18 PM PDT 24
Peak memory 201648 kb
Host smart-16670cf1-15fd-49f2-a8b6-bc0aec788bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348895557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.2348895557
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.795743488
Short name T396
Test name
Test status
Simulation time 2078434607 ps
CPU time 1.84 seconds
Started Jul 05 05:31:10 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 201580 kb
Host smart-9fe7e0fb-4afe-467a-955d-eca0c55e52a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795743488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.795743488
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.998740175
Short name T645
Test name
Test status
Simulation time 2507968472 ps
CPU time 7.35 seconds
Started Jul 05 05:31:09 PM PDT 24
Finished Jul 05 05:31:17 PM PDT 24
Peak memory 201628 kb
Host smart-243ea428-e843-4c90-8af3-2635ad14fbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998740175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.998740175
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.595641630
Short name T760
Test name
Test status
Simulation time 2113516705 ps
CPU time 3.34 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:11 PM PDT 24
Peak memory 201464 kb
Host smart-eaccb574-4a86-4fd1-8b0c-709e8d5a0b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595641630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.595641630
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.1158625063
Short name T776
Test name
Test status
Simulation time 7119692747 ps
CPU time 2.11 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:11 PM PDT 24
Peak memory 201656 kb
Host smart-1d863acc-4b46-486d-8846-4e874265a406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158625063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.1158625063
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2571010887
Short name T169
Test name
Test status
Simulation time 21604368718 ps
CPU time 25.4 seconds
Started Jul 05 05:31:07 PM PDT 24
Finished Jul 05 05:31:33 PM PDT 24
Peak memory 210208 kb
Host smart-84a7d5f1-201e-4916-bcaa-2794d5307c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571010887 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.2571010887
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2571434844
Short name T11
Test name
Test status
Simulation time 9701407595 ps
CPU time 2.53 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201644 kb
Host smart-5d14e65a-16dc-45df-9851-a1486d28a819
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571434844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.2571434844
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.3829828839
Short name T520
Test name
Test status
Simulation time 2009475072 ps
CPU time 5.58 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:31:25 PM PDT 24
Peak memory 201620 kb
Host smart-c9f739a1-d357-4402-8496-a15fa1fdd223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829828839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.3829828839
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3910107312
Short name T700
Test name
Test status
Simulation time 3507251094 ps
CPU time 2.79 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201780 kb
Host smart-beb2e29d-d444-43e4-8e53-32638761a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910107312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3
910107312
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.840448488
Short name T585
Test name
Test status
Simulation time 4655438649 ps
CPU time 3.76 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 201600 kb
Host smart-31c5df5d-7aea-476a-82a7-202d4a929946
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840448488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.840448488
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.606377326
Short name T150
Test name
Test status
Simulation time 3036599452 ps
CPU time 2.53 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:31:17 PM PDT 24
Peak memory 201684 kb
Host smart-7627b731-e13f-4638-b4db-9a568d31aef2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606377326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctr
l_edge_detect.606377326
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2203563993
Short name T459
Test name
Test status
Simulation time 2618971291 ps
CPU time 3.69 seconds
Started Jul 05 05:31:07 PM PDT 24
Finished Jul 05 05:31:11 PM PDT 24
Peak memory 201664 kb
Host smart-f5a1808f-85d9-4325-a860-17b7ef6d06a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203563993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2203563993
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1671908772
Short name T434
Test name
Test status
Simulation time 2496440682 ps
CPU time 2.43 seconds
Started Jul 05 05:31:09 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201664 kb
Host smart-64cc25f6-024b-4951-805d-37ca1331d03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671908772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1671908772
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.3347018884
Short name T690
Test name
Test status
Simulation time 2114120691 ps
CPU time 2.03 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:31:17 PM PDT 24
Peak memory 201592 kb
Host smart-a748e2b7-9849-46d2-8ec5-6f9d2344a34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347018884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3347018884
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1479946771
Short name T57
Test name
Test status
Simulation time 2740097315 ps
CPU time 1.19 seconds
Started Jul 05 05:31:15 PM PDT 24
Finished Jul 05 05:31:17 PM PDT 24
Peak memory 201648 kb
Host smart-b8073585-7ae2-4cdf-8e69-0622002a3a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479946771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.1479946771
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.3136633550
Short name T633
Test name
Test status
Simulation time 2115159704 ps
CPU time 6.17 seconds
Started Jul 05 05:31:08 PM PDT 24
Finished Jul 05 05:31:14 PM PDT 24
Peak memory 201412 kb
Host smart-0670a699-98d8-4da5-81cc-1585bf1679f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136633550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3136633550
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.2542435907
Short name T675
Test name
Test status
Simulation time 110454181685 ps
CPU time 152.78 seconds
Started Jul 05 05:31:07 PM PDT 24
Finished Jul 05 05:33:40 PM PDT 24
Peak memory 201896 kb
Host smart-fb2c7289-3dbc-42d7-be59-ed03bf82ae0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542435907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.2542435907
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.386375627
Short name T449
Test name
Test status
Simulation time 7769252326 ps
CPU time 6.75 seconds
Started Jul 05 05:31:14 PM PDT 24
Finished Jul 05 05:31:21 PM PDT 24
Peak memory 201640 kb
Host smart-a5328cf2-e1f0-4bb4-af1a-0dc3bfdf4807
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386375627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ultra_low_pwr.386375627
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1521563910
Short name T144
Test name
Test status
Simulation time 2021699805 ps
CPU time 3.28 seconds
Started Jul 05 05:30:31 PM PDT 24
Finished Jul 05 05:30:36 PM PDT 24
Peak memory 201580 kb
Host smart-6bb30379-f293-44a9-adf0-cb6d124a87d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521563910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1521563910
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.4179525960
Short name T516
Test name
Test status
Simulation time 3651357129 ps
CPU time 5.39 seconds
Started Jul 05 05:30:29 PM PDT 24
Finished Jul 05 05:30:35 PM PDT 24
Peak memory 201764 kb
Host smart-a5317f04-e36c-4177-969f-e8b82260060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179525960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.4179525960
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.168016935
Short name T327
Test name
Test status
Simulation time 176483889438 ps
CPU time 460.25 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:38:07 PM PDT 24
Peak memory 201876 kb
Host smart-cba60446-cbac-4ebb-b993-531d96eeae11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168016935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_combo_detect.168016935
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.50486256
Short name T28
Test name
Test status
Simulation time 2268958107 ps
CPU time 1.55 seconds
Started Jul 05 05:30:27 PM PDT 24
Finished Jul 05 05:30:30 PM PDT 24
Peak memory 201660 kb
Host smart-11204b96-554c-4f0a-9303-188687931d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50486256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.50486256
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3321189446
Short name T462
Test name
Test status
Simulation time 2515117199 ps
CPU time 3.61 seconds
Started Jul 05 05:30:27 PM PDT 24
Finished Jul 05 05:30:31 PM PDT 24
Peak memory 201620 kb
Host smart-707c3333-5bc2-479b-a571-1f4911ad3808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321189446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3321189446
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.684937525
Short name T461
Test name
Test status
Simulation time 5122136120 ps
CPU time 14.09 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:30:41 PM PDT 24
Peak memory 201608 kb
Host smart-f168c284-cc26-4da0-a1a6-69e70bac1236
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684937525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ec_pwr_on_rst.684937525
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.2119953732
Short name T78
Test name
Test status
Simulation time 2490481720 ps
CPU time 7.05 seconds
Started Jul 05 05:30:33 PM PDT 24
Finished Jul 05 05:30:41 PM PDT 24
Peak memory 201620 kb
Host smart-baafb2b0-2ead-4534-9d90-f695a3a2e417
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119953732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.2119953732
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1714745694
Short name T573
Test name
Test status
Simulation time 2615615167 ps
CPU time 3.6 seconds
Started Jul 05 05:30:33 PM PDT 24
Finished Jul 05 05:30:37 PM PDT 24
Peak memory 201620 kb
Host smart-dd1282ff-813c-4a4c-bb89-b940b610ea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714745694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1714745694
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.2455930753
Short name T515
Test name
Test status
Simulation time 2477852299 ps
CPU time 2.4 seconds
Started Jul 05 05:30:29 PM PDT 24
Finished Jul 05 05:30:32 PM PDT 24
Peak memory 201568 kb
Host smart-fad16c93-b747-43a3-9572-399a8b327398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455930753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2455930753
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.498726879
Short name T384
Test name
Test status
Simulation time 2052927587 ps
CPU time 5.39 seconds
Started Jul 05 05:30:34 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201536 kb
Host smart-eac2788e-f8c4-4a22-8eaa-b9fd6f616414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498726879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.498726879
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1867651622
Short name T699
Test name
Test status
Simulation time 2544112878 ps
CPU time 1.77 seconds
Started Jul 05 05:30:28 PM PDT 24
Finished Jul 05 05:30:31 PM PDT 24
Peak memory 201552 kb
Host smart-2b100519-b208-4c50-a30c-5bec312c4251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867651622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1867651622
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2464277710
Short name T89
Test name
Test status
Simulation time 22010904586 ps
CPU time 60.34 seconds
Started Jul 05 05:30:32 PM PDT 24
Finished Jul 05 05:31:33 PM PDT 24
Peak memory 221096 kb
Host smart-b2ffd775-4e60-4701-b166-6901bc442063
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464277710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2464277710
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.680364004
Short name T222
Test name
Test status
Simulation time 2107672404 ps
CPU time 5.59 seconds
Started Jul 05 05:30:31 PM PDT 24
Finished Jul 05 05:30:37 PM PDT 24
Peak memory 201460 kb
Host smart-b5e2dc4d-120c-4baf-8d99-d7d56afb4688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680364004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.680364004
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.52031283
Short name T136
Test name
Test status
Simulation time 14217536090 ps
CPU time 30.19 seconds
Started Jul 05 05:30:31 PM PDT 24
Finished Jul 05 05:31:02 PM PDT 24
Peak memory 201660 kb
Host smart-6d9f4082-7b78-45a7-a320-3935385d1093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52031283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stre
ss_all.52031283
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.917556348
Short name T143
Test name
Test status
Simulation time 711643251946 ps
CPU time 61.25 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:31:28 PM PDT 24
Peak memory 210232 kb
Host smart-d19f5718-cafc-4a40-a96d-38be4a58da06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917556348 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.917556348
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2455945461
Short name T670
Test name
Test status
Simulation time 3801581931 ps
CPU time 6.33 seconds
Started Jul 05 05:30:28 PM PDT 24
Finished Jul 05 05:30:35 PM PDT 24
Peak memory 201628 kb
Host smart-caf8db15-fea9-473c-a4fd-9aca9a0a2d9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455945461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.2455945461
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3069369144
Short name T512
Test name
Test status
Simulation time 2110651703 ps
CPU time 0.96 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:31:20 PM PDT 24
Peak memory 201664 kb
Host smart-82891026-6263-494d-8a03-372e91218603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069369144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3069369144
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2490884065
Short name T399
Test name
Test status
Simulation time 3588119223 ps
CPU time 2.95 seconds
Started Jul 05 05:31:19 PM PDT 24
Finished Jul 05 05:31:23 PM PDT 24
Peak memory 201636 kb
Host smart-f666fce6-3682-43c0-8d4e-1e8d72bb014e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490884065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.2
490884065
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.3180719214
Short name T283
Test name
Test status
Simulation time 156109340655 ps
CPU time 102.21 seconds
Started Jul 05 05:31:16 PM PDT 24
Finished Jul 05 05:32:58 PM PDT 24
Peak memory 201868 kb
Host smart-9a497a29-0d40-43c6-ac04-440b99848878
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180719214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.3180719214
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3272519072
Short name T546
Test name
Test status
Simulation time 658413730073 ps
CPU time 426.54 seconds
Started Jul 05 05:31:19 PM PDT 24
Finished Jul 05 05:38:26 PM PDT 24
Peak memory 201588 kb
Host smart-a8aad98b-5a4d-40ed-9bc4-c8b3b95a1a0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272519072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3272519072
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1722141494
Short name T753
Test name
Test status
Simulation time 2610113396 ps
CPU time 7.62 seconds
Started Jul 05 05:31:17 PM PDT 24
Finished Jul 05 05:31:26 PM PDT 24
Peak memory 201664 kb
Host smart-b81228ab-c3c8-4ffc-83eb-71b18195177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722141494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.1722141494
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3106738537
Short name T661
Test name
Test status
Simulation time 2501107985 ps
CPU time 2.48 seconds
Started Jul 05 05:31:16 PM PDT 24
Finished Jul 05 05:31:19 PM PDT 24
Peak memory 201612 kb
Host smart-3e6b4f15-3e37-4c90-8c24-aa4d04973deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106738537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3106738537
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.829696658
Short name T612
Test name
Test status
Simulation time 2225416402 ps
CPU time 3.75 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:31:23 PM PDT 24
Peak memory 201488 kb
Host smart-2d528853-1b1e-44dc-82be-added08fbfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829696658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.829696658
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3072898359
Short name T174
Test name
Test status
Simulation time 2534015145 ps
CPU time 2.45 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:31:22 PM PDT 24
Peak memory 201660 kb
Host smart-8d8e336a-d3b6-434f-9b15-57dabd085508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072898359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.3072898359
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1941314115
Short name T764
Test name
Test status
Simulation time 2124878916 ps
CPU time 1.9 seconds
Started Jul 05 05:31:17 PM PDT 24
Finished Jul 05 05:31:20 PM PDT 24
Peak memory 201492 kb
Host smart-16b8e8e5-886c-4047-b85c-32d5a78d2c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941314115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1941314115
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.3526417855
Short name T654
Test name
Test status
Simulation time 6227956993 ps
CPU time 16.29 seconds
Started Jul 05 05:31:17 PM PDT 24
Finished Jul 05 05:31:34 PM PDT 24
Peak memory 201632 kb
Host smart-2437cb4d-57e2-46dc-9048-80250acb43d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526417855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.3526417855
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.3683691969
Short name T138
Test name
Test status
Simulation time 7797271954 ps
CPU time 2.24 seconds
Started Jul 05 05:31:16 PM PDT 24
Finished Jul 05 05:31:18 PM PDT 24
Peak memory 201624 kb
Host smart-aecdd278-cb70-40e4-b57f-f6b7d7757768
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683691969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.3683691969
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.2381598416
Short name T502
Test name
Test status
Simulation time 2012488593 ps
CPU time 5.46 seconds
Started Jul 05 05:31:19 PM PDT 24
Finished Jul 05 05:31:26 PM PDT 24
Peak memory 201584 kb
Host smart-0db8097a-4ba6-4df9-bf6f-302d63c4d8b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381598416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.2381598416
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1169385642
Short name T473
Test name
Test status
Simulation time 3066119495 ps
CPU time 2.67 seconds
Started Jul 05 05:31:16 PM PDT 24
Finished Jul 05 05:31:20 PM PDT 24
Peak memory 201704 kb
Host smart-ae55d439-daeb-4ec0-9600-dda8bbc4605a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169385642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1
169385642
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.242033249
Short name T218
Test name
Test status
Simulation time 93681095966 ps
CPU time 56.63 seconds
Started Jul 05 05:31:15 PM PDT 24
Finished Jul 05 05:32:12 PM PDT 24
Peak memory 201872 kb
Host smart-9a638e7f-413b-4c69-82c8-e63ff1057cce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242033249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_combo_detect.242033249
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1960969497
Short name T550
Test name
Test status
Simulation time 3510741338 ps
CPU time 4.93 seconds
Started Jul 05 05:31:17 PM PDT 24
Finished Jul 05 05:31:22 PM PDT 24
Peak memory 201308 kb
Host smart-7e84785c-9f05-4365-a72d-9dec3c998d00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960969497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.1960969497
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.77123347
Short name T40
Test name
Test status
Simulation time 2789431808 ps
CPU time 3.98 seconds
Started Jul 05 05:31:16 PM PDT 24
Finished Jul 05 05:31:21 PM PDT 24
Peak memory 201568 kb
Host smart-f9ccbd4f-d6af-4b24-bae4-dc8a49ca13bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77123347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl
_edge_detect.77123347
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.2432745523
Short name T578
Test name
Test status
Simulation time 2608361040 ps
CPU time 7.18 seconds
Started Jul 05 05:31:17 PM PDT 24
Finished Jul 05 05:31:25 PM PDT 24
Peak memory 201260 kb
Host smart-5a211ced-d6ed-4d7e-a4c7-a77710bdb59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432745523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.2432745523
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.314094731
Short name T235
Test name
Test status
Simulation time 2465609169 ps
CPU time 6.35 seconds
Started Jul 05 05:31:16 PM PDT 24
Finished Jul 05 05:31:24 PM PDT 24
Peak memory 201604 kb
Host smart-48feab70-0306-4149-b2aa-d6ed32429160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314094731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.314094731
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2562645062
Short name T116
Test name
Test status
Simulation time 2249564804 ps
CPU time 3.59 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:31:23 PM PDT 24
Peak memory 201644 kb
Host smart-33af9d32-4194-4736-91be-4c782ce81668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562645062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2562645062
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1594552388
Short name T705
Test name
Test status
Simulation time 2510703399 ps
CPU time 7.11 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:31:26 PM PDT 24
Peak memory 201660 kb
Host smart-0f9940f7-726c-4f06-a48a-c322fbabfcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594552388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.1594552388
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.2769574164
Short name T766
Test name
Test status
Simulation time 2127798078 ps
CPU time 1.92 seconds
Started Jul 05 05:31:17 PM PDT 24
Finished Jul 05 05:31:20 PM PDT 24
Peak memory 201536 kb
Host smart-fdf4d50e-b7a1-4185-83d8-78e7981cb840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769574164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2769574164
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.3821096263
Short name T282
Test name
Test status
Simulation time 121624046357 ps
CPU time 296.77 seconds
Started Jul 05 05:31:17 PM PDT 24
Finished Jul 05 05:36:15 PM PDT 24
Peak memory 201860 kb
Host smart-738b94c5-4977-4787-a2df-75b8237cf312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821096263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.3821096263
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1381026658
Short name T373
Test name
Test status
Simulation time 1230891789330 ps
CPU time 7.53 seconds
Started Jul 05 05:31:16 PM PDT 24
Finished Jul 05 05:31:25 PM PDT 24
Peak memory 201556 kb
Host smart-ca6ff492-8625-4434-a2ef-43bedfa92834
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381026658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.1381026658
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.2277201306
Short name T454
Test name
Test status
Simulation time 2036255389 ps
CPU time 1.77 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:31:28 PM PDT 24
Peak memory 201904 kb
Host smart-b2bd2a57-6f7c-4473-b3cb-50a7ccc65773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277201306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.2277201306
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2832782782
Short name T489
Test name
Test status
Simulation time 3657278032 ps
CPU time 10.41 seconds
Started Jul 05 05:31:29 PM PDT 24
Finished Jul 05 05:31:40 PM PDT 24
Peak memory 201740 kb
Host smart-17c06d8d-2d9e-4308-bd3b-d5adbb1fedb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832782782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2
832782782
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1444729067
Short name T652
Test name
Test status
Simulation time 92556343501 ps
CPU time 118.04 seconds
Started Jul 05 05:31:28 PM PDT 24
Finished Jul 05 05:33:27 PM PDT 24
Peak memory 201760 kb
Host smart-39d06f8a-82df-4410-989e-7cbcfd184f78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444729067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1444729067
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2386335640
Short name T273
Test name
Test status
Simulation time 58363912501 ps
CPU time 35.82 seconds
Started Jul 05 05:31:24 PM PDT 24
Finished Jul 05 05:32:01 PM PDT 24
Peak memory 201928 kb
Host smart-97cc3651-1cfe-4d5c-94ed-5546576bfe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386335640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.2386335640
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.2946174047
Short name T204
Test name
Test status
Simulation time 3476374348 ps
CPU time 5.54 seconds
Started Jul 05 05:31:24 PM PDT 24
Finished Jul 05 05:31:31 PM PDT 24
Peak memory 201636 kb
Host smart-12b75740-c4e0-40e4-8d3f-9ed8ef4bc37c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946174047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.2946174047
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.1780253616
Short name T595
Test name
Test status
Simulation time 3409298869 ps
CPU time 8.76 seconds
Started Jul 05 05:31:28 PM PDT 24
Finished Jul 05 05:31:38 PM PDT 24
Peak memory 201660 kb
Host smart-b72d9bf9-1007-4fc6-ad03-63ef53aad302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780253616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.1780253616
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.2400537615
Short name T492
Test name
Test status
Simulation time 2631114635 ps
CPU time 2.32 seconds
Started Jul 05 05:31:28 PM PDT 24
Finished Jul 05 05:31:31 PM PDT 24
Peak memory 201668 kb
Host smart-aa82b461-d814-4dde-a3d5-3ec820c5141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400537615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.2400537615
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.4006537238
Short name T294
Test name
Test status
Simulation time 2500481985 ps
CPU time 1.21 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:37 PM PDT 24
Peak memory 201636 kb
Host smart-269ee70c-1da9-416a-b170-fbe1d8ca6003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006537238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.4006537238
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2335805319
Short name T115
Test name
Test status
Simulation time 2158996608 ps
CPU time 1.99 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:31:29 PM PDT 24
Peak memory 201576 kb
Host smart-ac753339-f8c8-4021-916f-876b61bf4763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335805319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.2335805319
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1063070948
Short name T59
Test name
Test status
Simulation time 2510880010 ps
CPU time 7.15 seconds
Started Jul 05 05:31:24 PM PDT 24
Finished Jul 05 05:31:33 PM PDT 24
Peak memory 201612 kb
Host smart-7f82c681-19c2-4f14-89a4-bcebc88e422d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063070948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.1063070948
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.1752567230
Short name T438
Test name
Test status
Simulation time 2122872200 ps
CPU time 1.99 seconds
Started Jul 05 05:31:18 PM PDT 24
Finished Jul 05 05:31:21 PM PDT 24
Peak memory 201528 kb
Host smart-72b9c49c-9d59-4a45-897e-e30a2906747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752567230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1752567230
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.130350042
Short name T522
Test name
Test status
Simulation time 9636887718 ps
CPU time 26.5 seconds
Started Jul 05 05:31:30 PM PDT 24
Finished Jul 05 05:31:57 PM PDT 24
Peak memory 201656 kb
Host smart-3ddde236-f4bf-448c-8916-11f4fe521b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130350042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.130350042
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.4137717075
Short name T505
Test name
Test status
Simulation time 32682271060 ps
CPU time 15.56 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:31:49 PM PDT 24
Peak memory 210272 kb
Host smart-f86576b6-fe06-4f0c-9484-9939c5c3ae2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137717075 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.4137717075
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.191446429
Short name T152
Test name
Test status
Simulation time 7796470605 ps
CPU time 8.41 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201644 kb
Host smart-c1ff40ed-0924-40db-8f97-9948bec85a05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191446429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ultra_low_pwr.191446429
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.2777909003
Short name T254
Test name
Test status
Simulation time 2010352028 ps
CPU time 5.82 seconds
Started Jul 05 05:31:26 PM PDT 24
Finished Jul 05 05:31:33 PM PDT 24
Peak memory 201336 kb
Host smart-b3f1eb9f-0b17-400f-98fc-9d52fda05660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777909003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.2777909003
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2727534568
Short name T159
Test name
Test status
Simulation time 68881057199 ps
CPU time 177.21 seconds
Started Jul 05 05:31:24 PM PDT 24
Finished Jul 05 05:34:23 PM PDT 24
Peak memory 201636 kb
Host smart-8d06adb4-7afc-4530-974d-30cab584ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727534568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
727534568
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.1931499710
Short name T117
Test name
Test status
Simulation time 58560821001 ps
CPU time 38.53 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:32:05 PM PDT 24
Peak memory 201848 kb
Host smart-c31a3760-f292-4f04-8e82-ed691016303a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931499710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.1931499710
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.356743480
Short name T270
Test name
Test status
Simulation time 24579167999 ps
CPU time 65.99 seconds
Started Jul 05 05:31:27 PM PDT 24
Finished Jul 05 05:32:34 PM PDT 24
Peak memory 201912 kb
Host smart-d9d0f7f9-802f-4241-95ff-f3c7ec46b40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356743480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_wi
th_pre_cond.356743480
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3606840707
Short name T13
Test name
Test status
Simulation time 2634116832 ps
CPU time 7.43 seconds
Started Jul 05 05:31:29 PM PDT 24
Finished Jul 05 05:31:38 PM PDT 24
Peak memory 201640 kb
Host smart-7e092d6b-dc37-4085-a57e-83162e269dea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606840707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.3606840707
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2768020170
Short name T217
Test name
Test status
Simulation time 5790776332 ps
CPU time 3.45 seconds
Started Jul 05 05:31:27 PM PDT 24
Finished Jul 05 05:31:31 PM PDT 24
Peak memory 201656 kb
Host smart-dc65506c-79b6-43b0-b5ea-8591edb03018
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768020170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.2768020170
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.42363168
Short name T726
Test name
Test status
Simulation time 2632495163 ps
CPU time 2.41 seconds
Started Jul 05 05:31:27 PM PDT 24
Finished Jul 05 05:31:31 PM PDT 24
Peak memory 201640 kb
Host smart-15499bcc-b9d7-4a88-8a71-0440368708e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42363168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.42363168
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3059541785
Short name T767
Test name
Test status
Simulation time 2453308899 ps
CPU time 7.18 seconds
Started Jul 05 05:31:26 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201668 kb
Host smart-01da2a66-6a90-4f3f-894a-650712fdfa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059541785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.3059541785
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.416311995
Short name T253
Test name
Test status
Simulation time 2133084125 ps
CPU time 1.24 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:31:28 PM PDT 24
Peak memory 201524 kb
Host smart-4c7c6405-dd7f-403f-952a-08dbba919a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416311995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.416311995
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.79148975
Short name T715
Test name
Test status
Simulation time 2127545694 ps
CPU time 1.59 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:31:28 PM PDT 24
Peak memory 201508 kb
Host smart-c0cc22f7-b1d9-4d75-bc48-76530782deab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79148975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.79148975
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.861901296
Short name T474
Test name
Test status
Simulation time 5153648605 ps
CPU time 5.79 seconds
Started Jul 05 05:31:23 PM PDT 24
Finished Jul 05 05:31:29 PM PDT 24
Peak memory 201636 kb
Host smart-8c9765fc-7862-4389-807d-6460769de656
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861901296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ultra_low_pwr.861901296
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.3218816650
Short name T600
Test name
Test status
Simulation time 2038284558 ps
CPU time 1.95 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:38 PM PDT 24
Peak memory 201668 kb
Host smart-515d11a6-24f4-4de4-bc7c-987cbaab6462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218816650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.3218816650
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1483471928
Short name T52
Test name
Test status
Simulation time 272503655565 ps
CPU time 694.85 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:43:01 PM PDT 24
Peak memory 201712 kb
Host smart-e8415e78-67a4-4409-94d9-b1e75b2294ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483471928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.1
483471928
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2565999783
Short name T123
Test name
Test status
Simulation time 79508830733 ps
CPU time 193.67 seconds
Started Jul 05 05:31:30 PM PDT 24
Finished Jul 05 05:34:45 PM PDT 24
Peak memory 201920 kb
Host smart-0906218f-f832-4edf-86a6-a821887296c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565999783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2565999783
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.4050920975
Short name T684
Test name
Test status
Simulation time 26830870757 ps
CPU time 72.23 seconds
Started Jul 05 05:31:29 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201912 kb
Host smart-f1b7616b-942d-428c-95a0-d6b82fbae5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050920975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.4050920975
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1036289855
Short name T400
Test name
Test status
Simulation time 3834642689 ps
CPU time 6.66 seconds
Started Jul 05 05:31:38 PM PDT 24
Finished Jul 05 05:31:46 PM PDT 24
Peak memory 201644 kb
Host smart-4eab5f5e-42b8-40b4-bb2d-02e561bbfa22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036289855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.1036289855
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.207492210
Short name T757
Test name
Test status
Simulation time 2608803801 ps
CPU time 7.37 seconds
Started Jul 05 05:31:27 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201660 kb
Host smart-12e75d64-4794-41ac-bf44-e3d2bb065c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207492210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.207492210
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.776288479
Short name T22
Test name
Test status
Simulation time 2479971353 ps
CPU time 2.3 seconds
Started Jul 05 05:31:28 PM PDT 24
Finished Jul 05 05:31:31 PM PDT 24
Peak memory 201552 kb
Host smart-c1f3b86d-e68c-414a-9e12-2d8993de1dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776288479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.776288479
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.623655968
Short name T579
Test name
Test status
Simulation time 2331186022 ps
CPU time 1.09 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201648 kb
Host smart-2142b9f4-eac9-4a60-ac38-b92ffd88a1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623655968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.623655968
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.1496854847
Short name T212
Test name
Test status
Simulation time 2511075183 ps
CPU time 3.95 seconds
Started Jul 05 05:31:24 PM PDT 24
Finished Jul 05 05:31:29 PM PDT 24
Peak memory 201604 kb
Host smart-a0511e61-7534-480d-b125-d210a8c0b348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496854847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1496854847
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.3881326054
Short name T507
Test name
Test status
Simulation time 2119020182 ps
CPU time 2.7 seconds
Started Jul 05 05:31:24 PM PDT 24
Finished Jul 05 05:31:27 PM PDT 24
Peak memory 201528 kb
Host smart-693cfd9d-2eb2-4352-93f2-96e146b9dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881326054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.3881326054
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.3876232548
Short name T688
Test name
Test status
Simulation time 2034271206 ps
CPU time 1.92 seconds
Started Jul 05 05:31:35 PM PDT 24
Finished Jul 05 05:31:38 PM PDT 24
Peak memory 201672 kb
Host smart-29cd3ced-1eb0-445d-8506-ccc920e2dfbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876232548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.3876232548
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.66168807
Short name T55
Test name
Test status
Simulation time 3889852958 ps
CPU time 5.19 seconds
Started Jul 05 05:31:29 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201780 kb
Host smart-7bddfe71-befc-4081-b65e-f90cfd0ed687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66168807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.66168807
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1117185311
Short name T360
Test name
Test status
Simulation time 140146728127 ps
CPU time 68.53 seconds
Started Jul 05 05:31:28 PM PDT 24
Finished Jul 05 05:32:38 PM PDT 24
Peak memory 201936 kb
Host smart-25467d69-d692-4d4b-a427-e14a172cebfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117185311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1117185311
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.4129413339
Short name T773
Test name
Test status
Simulation time 98355820976 ps
CPU time 59.4 seconds
Started Jul 05 05:31:26 PM PDT 24
Finished Jul 05 05:32:27 PM PDT 24
Peak memory 201852 kb
Host smart-f8330d93-7a91-44ec-bef5-63567420e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129413339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.4129413339
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1719152425
Short name T437
Test name
Test status
Simulation time 2523476524 ps
CPU time 2.33 seconds
Started Jul 05 05:31:24 PM PDT 24
Finished Jul 05 05:31:27 PM PDT 24
Peak memory 201644 kb
Host smart-40b06294-984a-4308-ae0c-6a5bbcea74bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719152425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.1719152425
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2154815673
Short name T164
Test name
Test status
Simulation time 4489299009 ps
CPU time 1.8 seconds
Started Jul 05 05:31:30 PM PDT 24
Finished Jul 05 05:31:33 PM PDT 24
Peak memory 201632 kb
Host smart-5d503924-0bd8-445d-a64e-9e38230df6e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154815673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.2154815673
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1068376307
Short name T728
Test name
Test status
Simulation time 2638744845 ps
CPU time 2.11 seconds
Started Jul 05 05:31:25 PM PDT 24
Finished Jul 05 05:31:29 PM PDT 24
Peak memory 201664 kb
Host smart-e57221c6-cb10-44c3-af6c-ae7c3a451c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068376307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1068376307
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1468691063
Short name T751
Test name
Test status
Simulation time 2500176651 ps
CPU time 1.76 seconds
Started Jul 05 05:31:27 PM PDT 24
Finished Jul 05 05:31:30 PM PDT 24
Peak memory 201664 kb
Host smart-ede1de99-58a0-4af4-8c9c-4d4e692a4bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468691063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1468691063
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2038606236
Short name T549
Test name
Test status
Simulation time 2146133132 ps
CPU time 2.23 seconds
Started Jul 05 05:31:29 PM PDT 24
Finished Jul 05 05:31:32 PM PDT 24
Peak memory 201584 kb
Host smart-2acc93ca-771b-4880-bd1b-23d978e5ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038606236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2038606236
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2775470025
Short name T160
Test name
Test status
Simulation time 2509269533 ps
CPU time 6.98 seconds
Started Jul 05 05:31:27 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201664 kb
Host smart-2c514176-8fe0-41cd-b729-870f1ec98376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775470025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.2775470025
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2291401999
Short name T781
Test name
Test status
Simulation time 2110228339 ps
CPU time 5.53 seconds
Started Jul 05 05:31:26 PM PDT 24
Finished Jul 05 05:31:33 PM PDT 24
Peak memory 201588 kb
Host smart-2d993130-3d22-45a0-a6fc-5f7282b32281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291401999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2291401999
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.2178437563
Short name T606
Test name
Test status
Simulation time 6339484037 ps
CPU time 15.91 seconds
Started Jul 05 05:31:32 PM PDT 24
Finished Jul 05 05:31:49 PM PDT 24
Peak memory 201640 kb
Host smart-7f4bd16a-081f-4c87-b03a-60e144524676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178437563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.2178437563
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1634005053
Short name T664
Test name
Test status
Simulation time 2028023610 ps
CPU time 1.93 seconds
Started Jul 05 05:31:35 PM PDT 24
Finished Jul 05 05:31:38 PM PDT 24
Peak memory 201576 kb
Host smart-40ca83ee-9d40-4f5a-9d07-d379c50b5b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634005053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1634005053
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1282740059
Short name T547
Test name
Test status
Simulation time 3297325043 ps
CPU time 1.6 seconds
Started Jul 05 05:31:36 PM PDT 24
Finished Jul 05 05:31:39 PM PDT 24
Peak memory 201724 kb
Host smart-de743267-41c3-4d6d-ba08-857fa39814af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282740059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.1
282740059
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.4265626308
Short name T278
Test name
Test status
Simulation time 72457018206 ps
CPU time 46.19 seconds
Started Jul 05 05:31:32 PM PDT 24
Finished Jul 05 05:32:18 PM PDT 24
Peak memory 201884 kb
Host smart-048d4f9e-01e2-4036-ae9b-4568c3dc5403
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265626308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.4265626308
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2107860999
Short name T548
Test name
Test status
Simulation time 140835085193 ps
CPU time 167.35 seconds
Started Jul 05 05:31:35 PM PDT 24
Finished Jul 05 05:34:24 PM PDT 24
Peak memory 201604 kb
Host smart-0b9fd88a-443e-48f2-b7b2-06ff3c813bdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107860999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.2107860999
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2881684166
Short name T613
Test name
Test status
Simulation time 2616386204 ps
CPU time 7.51 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:43 PM PDT 24
Peak memory 201664 kb
Host smart-4eac7cf3-9761-4168-b5e9-4b6d3b0256ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881684166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2881684166
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.534252286
Short name T77
Test name
Test status
Simulation time 2657742746 ps
CPU time 1.31 seconds
Started Jul 05 05:31:31 PM PDT 24
Finished Jul 05 05:31:33 PM PDT 24
Peak memory 201640 kb
Host smart-019d7234-33c2-4f5d-857d-109f1ce635f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534252286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.534252286
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.4118981431
Short name T639
Test name
Test status
Simulation time 2514444611 ps
CPU time 1.42 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201660 kb
Host smart-3cea63ea-e8d8-4008-8a23-9f941bf32961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118981431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.4118981431
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3024195437
Short name T466
Test name
Test status
Simulation time 2173098856 ps
CPU time 6.25 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:31:40 PM PDT 24
Peak memory 201560 kb
Host smart-1197c5c7-4bdb-4e39-9299-ad918b2ca09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024195437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3024195437
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3119930878
Short name T709
Test name
Test status
Simulation time 2551782766 ps
CPU time 1.76 seconds
Started Jul 05 05:31:36 PM PDT 24
Finished Jul 05 05:31:39 PM PDT 24
Peak memory 201648 kb
Host smart-2bfd6033-bbee-42ef-838b-610c45a0ec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119930878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3119930878
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.333624106
Short name T214
Test name
Test status
Simulation time 2108652193 ps
CPU time 5.88 seconds
Started Jul 05 05:31:35 PM PDT 24
Finished Jul 05 05:31:43 PM PDT 24
Peak memory 201592 kb
Host smart-ce61edc6-6c99-4fe8-b249-5d8fa1029adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333624106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.333624106
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.3999029705
Short name T530
Test name
Test status
Simulation time 12607466375 ps
CPU time 33.14 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:32:08 PM PDT 24
Peak memory 201724 kb
Host smart-4714df2b-d638-4937-a989-f81a1e2b4d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999029705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.3999029705
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1352618243
Short name T279
Test name
Test status
Simulation time 40667356638 ps
CPU time 98.15 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:33:13 PM PDT 24
Peak memory 210176 kb
Host smart-9d2fa3fa-a851-4330-9020-692fa4c35dd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352618243 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.1352618243
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.192113209
Short name T65
Test name
Test status
Simulation time 2757633882 ps
CPU time 1 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:31:35 PM PDT 24
Peak memory 201636 kb
Host smart-6c5873d2-7ec2-4b48-877b-c34fc12e7efc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192113209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.192113209
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.717240736
Short name T131
Test name
Test status
Simulation time 2012368895 ps
CPU time 5.61 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:41 PM PDT 24
Peak memory 201624 kb
Host smart-96561660-62d7-438d-bd10-d9adebc38f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717240736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_tes
t.717240736
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.187949809
Short name T291
Test name
Test status
Simulation time 3864128306 ps
CPU time 5.29 seconds
Started Jul 05 05:31:36 PM PDT 24
Finished Jul 05 05:31:43 PM PDT 24
Peak memory 201728 kb
Host smart-668be328-46b7-4625-8fee-0d8949969b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187949809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.187949809
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3297104978
Short name T284
Test name
Test status
Simulation time 128224501460 ps
CPU time 178.87 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:34:33 PM PDT 24
Peak memory 201828 kb
Host smart-882026be-5b59-4b33-9f0d-2ed20c7890df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297104978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.3297104978
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.1383758210
Short name T223
Test name
Test status
Simulation time 2840989645 ps
CPU time 1.96 seconds
Started Jul 05 05:31:37 PM PDT 24
Finished Jul 05 05:31:40 PM PDT 24
Peak memory 201632 kb
Host smart-6d5e6580-38e7-420e-95e7-eb7d6d4c7d28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383758210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.1383758210
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.2962652116
Short name T689
Test name
Test status
Simulation time 5593128946 ps
CPU time 4.2 seconds
Started Jul 05 05:31:37 PM PDT 24
Finished Jul 05 05:31:42 PM PDT 24
Peak memory 201656 kb
Host smart-56f94b92-dbda-4171-b00f-835e4b4d84c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962652116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.2962652116
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3400671979
Short name T541
Test name
Test status
Simulation time 2637640508 ps
CPU time 2.44 seconds
Started Jul 05 05:33:03 PM PDT 24
Finished Jul 05 05:33:06 PM PDT 24
Peak memory 201660 kb
Host smart-39b3725d-70c8-4360-a00f-332d51e4c868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400671979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.3400671979
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.873115110
Short name T207
Test name
Test status
Simulation time 2471385980 ps
CPU time 2.43 seconds
Started Jul 05 05:31:35 PM PDT 24
Finished Jul 05 05:31:39 PM PDT 24
Peak memory 201644 kb
Host smart-dde3495f-a349-47f9-abba-94d777cc0f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873115110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.873115110
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.2424426159
Short name T409
Test name
Test status
Simulation time 2084659467 ps
CPU time 6.34 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:42 PM PDT 24
Peak memory 201552 kb
Host smart-78dbd150-11a5-491d-8851-9fa746e24c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424426159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.2424426159
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.933438046
Short name T672
Test name
Test status
Simulation time 2513531158 ps
CPU time 7.02 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:43 PM PDT 24
Peak memory 201636 kb
Host smart-9477cdce-3f3c-4ad0-95bb-503335226686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933438046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.933438046
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.3876766080
Short name T387
Test name
Test status
Simulation time 2122702405 ps
CPU time 3.49 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:39 PM PDT 24
Peak memory 201548 kb
Host smart-573b2ebf-f3ba-4953-adde-ebee4aa6406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876766080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3876766080
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.2235365504
Short name T609
Test name
Test status
Simulation time 13731578409 ps
CPU time 9.56 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:55 PM PDT 24
Peak memory 201880 kb
Host smart-7fa1defb-719b-4f2c-a652-66bb55fb824f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235365504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.2235365504
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3332262400
Short name T704
Test name
Test status
Simulation time 24093371915 ps
CPU time 13.96 seconds
Started Jul 05 05:31:33 PM PDT 24
Finished Jul 05 05:31:48 PM PDT 24
Peak memory 218380 kb
Host smart-37fd97fe-abd6-4bc2-aa79-e9b4b6c6bbd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332262400 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.3332262400
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3923130779
Short name T135
Test name
Test status
Simulation time 3577023767 ps
CPU time 1.29 seconds
Started Jul 05 05:31:35 PM PDT 24
Finished Jul 05 05:31:38 PM PDT 24
Peak memory 201668 kb
Host smart-b9cbb666-0588-4852-a46a-c688189c8f49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923130779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.3923130779
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.2480539629
Short name T203
Test name
Test status
Simulation time 2048172909 ps
CPU time 1.34 seconds
Started Jul 05 05:31:46 PM PDT 24
Finished Jul 05 05:31:48 PM PDT 24
Peak memory 201672 kb
Host smart-850fcfb1-fd1c-4435-a1ef-e13c13b9dddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480539629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.2480539629
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.8288539
Short name T634
Test name
Test status
Simulation time 3666560090 ps
CPU time 10.53 seconds
Started Jul 05 05:31:35 PM PDT 24
Finished Jul 05 05:31:47 PM PDT 24
Peak memory 201756 kb
Host smart-9fcef8cd-626e-4c18-abc0-c8dd4c567f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8288539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.8288539
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.4131157462
Short name T680
Test name
Test status
Simulation time 147522674868 ps
CPU time 345.45 seconds
Started Jul 05 05:31:38 PM PDT 24
Finished Jul 05 05:37:25 PM PDT 24
Peak memory 201864 kb
Host smart-e59ad116-5bb8-4563-bc90-78eb43751abd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131157462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.4131157462
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.579966405
Short name T26
Test name
Test status
Simulation time 25105957016 ps
CPU time 16.65 seconds
Started Jul 05 05:31:39 PM PDT 24
Finished Jul 05 05:31:56 PM PDT 24
Peak memory 201864 kb
Host smart-2ba66852-217e-423e-b922-f151400728dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579966405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_wi
th_pre_cond.579966405
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2852911365
Short name T398
Test name
Test status
Simulation time 3152977862 ps
CPU time 2.32 seconds
Started Jul 05 05:31:36 PM PDT 24
Finished Jul 05 05:31:40 PM PDT 24
Peak memory 201608 kb
Host smart-d27451a9-c088-4563-b143-4ab07bb0ef38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852911365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.2852911365
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3092674802
Short name T35
Test name
Test status
Simulation time 4324674263 ps
CPU time 2.24 seconds
Started Jul 05 05:31:38 PM PDT 24
Finished Jul 05 05:31:41 PM PDT 24
Peak memory 201696 kb
Host smart-0852c1f2-f55f-40e2-a699-41b23b0e7b41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092674802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.3092674802
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2097634939
Short name T556
Test name
Test status
Simulation time 2613327203 ps
CPU time 7.98 seconds
Started Jul 05 05:31:31 PM PDT 24
Finished Jul 05 05:31:39 PM PDT 24
Peak memory 201572 kb
Host smart-12a3c82d-3285-4a1e-995d-480d8858c0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097634939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2097634939
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.3648471230
Short name T593
Test name
Test status
Simulation time 2514550823 ps
CPU time 1.22 seconds
Started Jul 05 05:31:38 PM PDT 24
Finished Jul 05 05:31:40 PM PDT 24
Peak memory 201656 kb
Host smart-e937c569-4587-4e47-81e9-99b45cef1554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648471230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.3648471230
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1400374077
Short name T467
Test name
Test status
Simulation time 2227270627 ps
CPU time 1.91 seconds
Started Jul 05 05:31:38 PM PDT 24
Finished Jul 05 05:31:41 PM PDT 24
Peak memory 201580 kb
Host smart-3a99dfbb-47ac-4bc6-a7ea-0f149d1641a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400374077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.1400374077
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2193175555
Short name T569
Test name
Test status
Simulation time 2512298307 ps
CPU time 7.36 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:43 PM PDT 24
Peak memory 201664 kb
Host smart-03c15f69-bd99-405f-b072-779a028602e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193175555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2193175555
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.3779012284
Short name T234
Test name
Test status
Simulation time 2118553613 ps
CPU time 3.56 seconds
Started Jul 05 05:31:34 PM PDT 24
Finished Jul 05 05:31:40 PM PDT 24
Peak memory 201600 kb
Host smart-63ca3aee-f517-41d6-9525-da2c4a5d8a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779012284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3779012284
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3388970204
Short name T761
Test name
Test status
Simulation time 15060888482 ps
CPU time 8.95 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:53 PM PDT 24
Peak memory 201656 kb
Host smart-d048bab5-d395-43d1-a7e5-3579e1979403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388970204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3388970204
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3501196817
Short name T738
Test name
Test status
Simulation time 3939441140 ps
CPU time 3.58 seconds
Started Jul 05 05:31:36 PM PDT 24
Finished Jul 05 05:31:40 PM PDT 24
Peak memory 201672 kb
Host smart-f7445010-6a24-47d8-9baa-1d4a0ddc458a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501196817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.3501196817
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.3902295868
Short name T681
Test name
Test status
Simulation time 2155657775 ps
CPU time 0.9 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:46 PM PDT 24
Peak memory 201724 kb
Host smart-4de71ddc-f194-4a2f-b5bf-61913f15de24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902295868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.3902295868
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3257901416
Short name T647
Test name
Test status
Simulation time 3244489322 ps
CPU time 4.58 seconds
Started Jul 05 05:31:45 PM PDT 24
Finished Jul 05 05:31:51 PM PDT 24
Peak memory 201668 kb
Host smart-cd7df146-c62c-43fe-b530-8b83ec6797b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257901416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3
257901416
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.315364548
Short name T568
Test name
Test status
Simulation time 154334568543 ps
CPU time 380.51 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:38:06 PM PDT 24
Peak memory 201928 kb
Host smart-ff4052b8-9a27-49cc-8a19-a5148db4bf6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315364548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_combo_detect.315364548
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1639604702
Short name T608
Test name
Test status
Simulation time 3064991357 ps
CPU time 9.03 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:32:02 PM PDT 24
Peak memory 201568 kb
Host smart-09b27366-617d-4a1b-9886-2087cb575c6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639604702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.1639604702
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2676725708
Short name T552
Test name
Test status
Simulation time 5496021559 ps
CPU time 6.06 seconds
Started Jul 05 05:31:47 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 201660 kb
Host smart-44f5480f-1ef1-469a-890a-33d87da5c36f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676725708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.2676725708
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3504701497
Short name T134
Test name
Test status
Simulation time 2623323028 ps
CPU time 2.19 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:47 PM PDT 24
Peak memory 201648 kb
Host smart-c6f941e3-3988-400a-992f-84a33ebbea61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504701497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3504701497
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.4162922720
Short name T566
Test name
Test status
Simulation time 2461640065 ps
CPU time 7.61 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:31:53 PM PDT 24
Peak memory 201656 kb
Host smart-707ba1f2-a4ea-4d9c-84fa-4c71c99cab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162922720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.4162922720
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.903645209
Short name T423
Test name
Test status
Simulation time 2131436343 ps
CPU time 1.97 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:31:47 PM PDT 24
Peak memory 201456 kb
Host smart-3bcfa769-b98b-4255-a77d-e9ff982aa4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903645209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.903645209
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3288178662
Short name T248
Test name
Test status
Simulation time 2517097225 ps
CPU time 4.02 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:31:50 PM PDT 24
Peak memory 201536 kb
Host smart-faf31d2b-a133-463d-9046-ebd22f2a13e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288178662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3288178662
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.2845168081
Short name T504
Test name
Test status
Simulation time 2112289419 ps
CPU time 6.12 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:31:52 PM PDT 24
Peak memory 201388 kb
Host smart-b88adc29-29b4-4359-9492-e96dd5d94f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845168081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.2845168081
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1343849664
Short name T358
Test name
Test status
Simulation time 35467148378 ps
CPU time 43.17 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:32:28 PM PDT 24
Peak memory 202096 kb
Host smart-ee65579d-9d38-4494-b479-bac68711918f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343849664 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1343849664
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3925290846
Short name T106
Test name
Test status
Simulation time 7152006614 ps
CPU time 4.02 seconds
Started Jul 05 05:31:45 PM PDT 24
Finished Jul 05 05:31:50 PM PDT 24
Peak memory 201644 kb
Host smart-6a9a4273-c776-4603-8ab2-1bbe02b35e6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925290846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.3925290846
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.2847696409
Short name T713
Test name
Test status
Simulation time 2014054363 ps
CPU time 5.42 seconds
Started Jul 05 05:30:29 PM PDT 24
Finished Jul 05 05:30:35 PM PDT 24
Peak memory 201668 kb
Host smart-9dd4c92d-9471-4a5e-9b15-fd1ebe59e14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847696409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.2847696409
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1392669839
Short name T114
Test name
Test status
Simulation time 3748601054 ps
CPU time 2.08 seconds
Started Jul 05 05:30:31 PM PDT 24
Finished Jul 05 05:30:35 PM PDT 24
Peak memory 201720 kb
Host smart-10aaf670-7ff1-4a64-8a2b-35fd88ef52b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392669839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1392669839
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.2108718003
Short name T678
Test name
Test status
Simulation time 155451206819 ps
CPU time 42.22 seconds
Started Jul 05 05:30:29 PM PDT 24
Finished Jul 05 05:31:12 PM PDT 24
Peak memory 201948 kb
Host smart-a4a6e468-d610-4a2e-87f1-91ce515d2093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108718003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.2108718003
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3850517547
Short name T494
Test name
Test status
Simulation time 2289716509 ps
CPU time 1.13 seconds
Started Jul 05 05:30:31 PM PDT 24
Finished Jul 05 05:30:33 PM PDT 24
Peak memory 201612 kb
Host smart-111e9c02-53ce-4145-a695-c7db4c74a33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850517547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3850517547
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1020199431
Short name T553
Test name
Test status
Simulation time 2311972156 ps
CPU time 6.43 seconds
Started Jul 05 05:30:30 PM PDT 24
Finished Jul 05 05:30:37 PM PDT 24
Peak memory 201664 kb
Host smart-3f1d8ea1-927f-460c-9969-12df42f94558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020199431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1020199431
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3077715147
Short name T277
Test name
Test status
Simulation time 26359241045 ps
CPU time 17.45 seconds
Started Jul 05 05:30:29 PM PDT 24
Finished Jul 05 05:30:47 PM PDT 24
Peak memory 201912 kb
Host smart-4ea38f4b-8e36-4d4f-b1d5-bae9220d1d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077715147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.3077715147
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.4117573588
Short name T714
Test name
Test status
Simulation time 2777265905 ps
CPU time 4.29 seconds
Started Jul 05 05:30:27 PM PDT 24
Finished Jul 05 05:30:33 PM PDT 24
Peak memory 201640 kb
Host smart-f1880103-238c-4f52-87f2-246a902ce449
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117573588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.4117573588
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3422130655
Short name T177
Test name
Test status
Simulation time 4342741794 ps
CPU time 6.06 seconds
Started Jul 05 05:30:33 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 201612 kb
Host smart-621e1608-1ec1-41c2-9de2-3dcbb129bfb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422130655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.3422130655
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.72380762
Short name T551
Test name
Test status
Simulation time 2618867368 ps
CPU time 4.07 seconds
Started Jul 05 05:30:29 PM PDT 24
Finished Jul 05 05:30:34 PM PDT 24
Peak memory 201644 kb
Host smart-f59c44c3-a0ea-424b-b574-10ba6b7d0fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72380762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.72380762
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.4055034115
Short name T526
Test name
Test status
Simulation time 2499310753 ps
CPU time 2.26 seconds
Started Jul 05 05:30:25 PM PDT 24
Finished Jul 05 05:30:28 PM PDT 24
Peak memory 201608 kb
Host smart-0e8bba03-919c-4eb7-b8f2-294366486e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055034115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.4055034115
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1583046735
Short name T610
Test name
Test status
Simulation time 2116196742 ps
CPU time 1.94 seconds
Started Jul 05 05:30:28 PM PDT 24
Finished Jul 05 05:30:31 PM PDT 24
Peak memory 201456 kb
Host smart-23d8d6ac-c32d-40ec-84b7-48efedf252d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583046735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.1583046735
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2451718985
Short name T565
Test name
Test status
Simulation time 2512689150 ps
CPU time 7.06 seconds
Started Jul 05 05:30:33 PM PDT 24
Finished Jul 05 05:30:41 PM PDT 24
Peak memory 201596 kb
Host smart-2c30d43e-9f84-4ce8-993c-09a8f0786fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451718985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2451718985
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2271926961
Short name T289
Test name
Test status
Simulation time 42011086352 ps
CPU time 100.96 seconds
Started Jul 05 05:30:32 PM PDT 24
Finished Jul 05 05:32:14 PM PDT 24
Peak memory 221004 kb
Host smart-2d3a20b0-3abe-4e21-b169-2e2d4da7952f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271926961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.2271926961
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.3621495615
Short name T646
Test name
Test status
Simulation time 2126838628 ps
CPU time 1.85 seconds
Started Jul 05 05:30:30 PM PDT 24
Finished Jul 05 05:30:33 PM PDT 24
Peak memory 201496 kb
Host smart-893993eb-c489-4c51-9265-a4f657833b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621495615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.3621495615
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1771873583
Short name T209
Test name
Test status
Simulation time 43976800591 ps
CPU time 57.05 seconds
Started Jul 05 05:30:30 PM PDT 24
Finished Jul 05 05:31:28 PM PDT 24
Peak memory 218336 kb
Host smart-24dd4b37-9603-4d52-8893-ffcf40b96511
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771873583 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1771873583
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2255348686
Short name T746
Test name
Test status
Simulation time 413331128723 ps
CPU time 41.97 seconds
Started Jul 05 05:30:32 PM PDT 24
Finished Jul 05 05:31:15 PM PDT 24
Peak memory 201504 kb
Host smart-b3b99e1d-b0f4-41ae-856d-79c1c434adc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255348686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2255348686
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.1915190753
Short name T510
Test name
Test status
Simulation time 2049550888 ps
CPU time 1.85 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:31:47 PM PDT 24
Peak memory 201672 kb
Host smart-c3b808e4-7d8a-490d-b647-68a54eab6b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915190753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.1915190753
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2981864840
Short name T737
Test name
Test status
Simulation time 3920584310 ps
CPU time 10.8 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:56 PM PDT 24
Peak memory 201700 kb
Host smart-e0108317-d200-4555-92b7-e61b7e875728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981864840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
981864840
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.1500543313
Short name T185
Test name
Test status
Simulation time 83890597300 ps
CPU time 116.17 seconds
Started Jul 05 05:31:42 PM PDT 24
Finished Jul 05 05:33:40 PM PDT 24
Peak memory 201852 kb
Host smart-4f30a5ac-6eef-404d-8221-a5357891ad28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500543313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.1500543313
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1022785543
Short name T120
Test name
Test status
Simulation time 52583250323 ps
CPU time 104.86 seconds
Started Jul 05 05:31:41 PM PDT 24
Finished Jul 05 05:33:27 PM PDT 24
Peak memory 201916 kb
Host smart-977207bd-9b3b-4b3e-87a3-7741e7a8a7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022785543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1022785543
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1032939516
Short name T607
Test name
Test status
Simulation time 2567889164 ps
CPU time 2.01 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:31:47 PM PDT 24
Peak memory 201644 kb
Host smart-c4a055a5-8f5d-4a74-9878-5ec68439780a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032939516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.1032939516
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.2998608459
Short name T603
Test name
Test status
Simulation time 4090444189 ps
CPU time 5.7 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:51 PM PDT 24
Peak memory 201696 kb
Host smart-ef60df8a-a218-4470-a8de-d4d2ed79584f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998608459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.2998608459
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.2702243623
Short name T392
Test name
Test status
Simulation time 2622094472 ps
CPU time 2.28 seconds
Started Jul 05 05:31:41 PM PDT 24
Finished Jul 05 05:31:44 PM PDT 24
Peak memory 201656 kb
Host smart-5b328374-7fbe-4aa6-88b9-fcd9f18187f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702243623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.2702243623
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.4123653605
Short name T576
Test name
Test status
Simulation time 2467333614 ps
CPU time 3.58 seconds
Started Jul 05 05:31:42 PM PDT 24
Finished Jul 05 05:31:47 PM PDT 24
Peak memory 201644 kb
Host smart-14daf33e-a555-41de-81c8-0520d52b3443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123653605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.4123653605
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.1065718451
Short name T686
Test name
Test status
Simulation time 2135466104 ps
CPU time 5.71 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:51 PM PDT 24
Peak memory 201588 kb
Host smart-b486a1cb-b702-4869-9f27-b79589d69bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065718451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.1065718451
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1770223974
Short name T596
Test name
Test status
Simulation time 2515319866 ps
CPU time 7.33 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:31:53 PM PDT 24
Peak memory 201548 kb
Host smart-d535b6ba-9fe7-45f0-aeb8-e00c1f7bcb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770223974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1770223974
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.1730361213
Short name T615
Test name
Test status
Simulation time 2111604029 ps
CPU time 6.23 seconds
Started Jul 05 05:31:42 PM PDT 24
Finished Jul 05 05:31:49 PM PDT 24
Peak memory 201596 kb
Host smart-1e7d6518-f139-4275-a89c-e4e712873199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730361213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1730361213
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2787122284
Short name T371
Test name
Test status
Simulation time 139734651286 ps
CPU time 360.96 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:37:47 PM PDT 24
Peak memory 201720 kb
Host smart-9ed5f839-def5-4705-bc43-aa5e17b03db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787122284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2787122284
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1027675624
Short name T82
Test name
Test status
Simulation time 8994420488 ps
CPU time 6.91 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:51 PM PDT 24
Peak memory 201644 kb
Host smart-8627f734-d079-406e-81a9-45bacf42c414
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027675624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.1027675624
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.2732063023
Short name T748
Test name
Test status
Simulation time 2050651012 ps
CPU time 1.78 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:31:56 PM PDT 24
Peak memory 201592 kb
Host smart-bbf95a21-cdb4-479e-8289-8e9625d46997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732063023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.2732063023
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.2937469731
Short name T252
Test name
Test status
Simulation time 39302533692 ps
CPU time 27.41 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:32:19 PM PDT 24
Peak memory 201624 kb
Host smart-7bf45923-0f33-4d74-98f5-8b8d56e27099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937469731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.2
937469731
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3540141256
Short name T669
Test name
Test status
Simulation time 56199634187 ps
CPU time 25.98 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:32:19 PM PDT 24
Peak memory 201836 kb
Host smart-405fabf3-594a-4d5f-bffd-fc1ea8c52b55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540141256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.3540141256
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1014872867
Short name T47
Test name
Test status
Simulation time 34010613374 ps
CPU time 86.83 seconds
Started Jul 05 05:31:54 PM PDT 24
Finished Jul 05 05:33:23 PM PDT 24
Peak memory 201944 kb
Host smart-ca3f69bb-4ed8-443a-886f-743606efeaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014872867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.1014872867
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.810776823
Short name T495
Test name
Test status
Simulation time 2556341205 ps
CPU time 3.76 seconds
Started Jul 05 05:31:42 PM PDT 24
Finished Jul 05 05:31:47 PM PDT 24
Peak memory 201624 kb
Host smart-7cd13490-9c3f-470f-91be-2454a5d639b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810776823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_ec_pwr_on_rst.810776823
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.4006632288
Short name T205
Test name
Test status
Simulation time 2978953306 ps
CPU time 2.7 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:31:57 PM PDT 24
Peak memory 201692 kb
Host smart-17a84997-7236-419d-9a47-041af804bd62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006632288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.4006632288
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.661102634
Short name T268
Test name
Test status
Simulation time 2624990684 ps
CPU time 2.12 seconds
Started Jul 05 05:31:45 PM PDT 24
Finished Jul 05 05:31:48 PM PDT 24
Peak memory 201644 kb
Host smart-6af0d332-d8b1-40f8-8e9c-a7c4bcb1cb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661102634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.661102634
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2354484634
Short name T74
Test name
Test status
Simulation time 2486434028 ps
CPU time 2.24 seconds
Started Jul 05 05:31:43 PM PDT 24
Finished Jul 05 05:31:46 PM PDT 24
Peak memory 201660 kb
Host smart-9afa395c-ce8f-4c03-ae33-6f72055e976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354484634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2354484634
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3538449860
Short name T627
Test name
Test status
Simulation time 2177494330 ps
CPU time 1.54 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:31:53 PM PDT 24
Peak memory 201500 kb
Host smart-49b0c7fc-0873-414e-97c0-cca520a67c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538449860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3538449860
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2345235654
Short name T493
Test name
Test status
Simulation time 2526991888 ps
CPU time 2.45 seconds
Started Jul 05 05:31:41 PM PDT 24
Finished Jul 05 05:31:44 PM PDT 24
Peak memory 201624 kb
Host smart-16efc89b-c12c-469e-b804-1e440b48ed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345235654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.2345235654
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.4263196195
Short name T404
Test name
Test status
Simulation time 2117940766 ps
CPU time 3.39 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 201456 kb
Host smart-24d6d415-6225-4c10-a21e-7690ba21225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263196195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.4263196195
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.4210080398
Short name T619
Test name
Test status
Simulation time 12834844816 ps
CPU time 30.52 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:32:26 PM PDT 24
Peak memory 201724 kb
Host smart-7f82ebf8-a800-4e75-9bb8-51fd7a52fe4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210080398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.4210080398
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.461732035
Short name T693
Test name
Test status
Simulation time 33881631828 ps
CPU time 42.02 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:32:36 PM PDT 24
Peak memory 202016 kb
Host smart-2247b577-6e50-4937-949f-f70a5aba27e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461732035 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.461732035
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1554955910
Short name T698
Test name
Test status
Simulation time 8031152727 ps
CPU time 7.18 seconds
Started Jul 05 05:31:44 PM PDT 24
Finished Jul 05 05:31:53 PM PDT 24
Peak memory 201364 kb
Host smart-e0889c31-6aaa-4c6b-97c4-696e842ae882
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554955910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.1554955910
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.2044104932
Short name T418
Test name
Test status
Simulation time 2032548711 ps
CPU time 1.99 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 201664 kb
Host smart-daf3d5fe-98f7-4070-8c1e-332fc58b34a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044104932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.2044104932
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1716171302
Short name T403
Test name
Test status
Simulation time 3445206271 ps
CPU time 3.08 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:56 PM PDT 24
Peak memory 201620 kb
Host smart-673f3aef-8c6d-46d8-926d-596445fbf551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716171302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.1
716171302
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2460409059
Short name T517
Test name
Test status
Simulation time 3947491171 ps
CPU time 10.61 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:32:06 PM PDT 24
Peak memory 201596 kb
Host smart-e0a1a53c-9b30-43d4-9b30-674f83b2488c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460409059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.2460409059
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.2051348557
Short name T41
Test name
Test status
Simulation time 5744161623 ps
CPU time 5.15 seconds
Started Jul 05 05:31:57 PM PDT 24
Finished Jul 05 05:32:04 PM PDT 24
Peak memory 201584 kb
Host smart-d3ec0a1c-c11b-4633-8142-1a1f588ac81c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051348557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.2051348557
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3141771676
Short name T17
Test name
Test status
Simulation time 2608449219 ps
CPU time 7.52 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:31:58 PM PDT 24
Peak memory 201656 kb
Host smart-1c7185be-eed4-4999-8655-c6bf52f6da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141771676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3141771676
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.2267036441
Short name T659
Test name
Test status
Simulation time 2476199433 ps
CPU time 4.33 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:58 PM PDT 24
Peak memory 201688 kb
Host smart-c12464db-fb4c-4765-9192-e97b8b187126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267036441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.2267036441
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3730017648
Short name T202
Test name
Test status
Simulation time 2034756262 ps
CPU time 2.99 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:56 PM PDT 24
Peak memory 201588 kb
Host smart-4c841ccf-fd04-4c8e-8d0e-9cd237f285fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730017648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3730017648
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1149803021
Short name T506
Test name
Test status
Simulation time 2518384174 ps
CPU time 3.59 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:31:58 PM PDT 24
Peak memory 201636 kb
Host smart-0d5ceaf5-85a7-495f-a292-e0ce7bc6443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149803021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.1149803021
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.3627357437
Short name T388
Test name
Test status
Simulation time 2125483504 ps
CPU time 2.03 seconds
Started Jul 05 05:31:53 PM PDT 24
Finished Jul 05 05:31:58 PM PDT 24
Peak memory 201524 kb
Host smart-481ccc76-4b58-475c-ad13-c875e0f1e128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627357437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3627357437
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.2555057967
Short name T750
Test name
Test status
Simulation time 136697178452 ps
CPU time 162.41 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:34:37 PM PDT 24
Peak memory 201856 kb
Host smart-4642bb06-3869-4ee5-8e41-8582f12f995d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555057967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.2555057967
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.3877593614
Short name T521
Test name
Test status
Simulation time 2011148077 ps
CPU time 5.73 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:31:57 PM PDT 24
Peak memory 201620 kb
Host smart-d0852472-1fc9-4664-8242-30c476dc4756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877593614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.3877593614
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3725147716
Short name T656
Test name
Test status
Simulation time 3478637285 ps
CPU time 4.8 seconds
Started Jul 05 05:31:55 PM PDT 24
Finished Jul 05 05:32:01 PM PDT 24
Peak memory 201740 kb
Host smart-a9fdf2e0-4335-4d8f-87a6-fa0cb57556f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725147716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.3
725147716
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1214050121
Short name T124
Test name
Test status
Simulation time 67848957330 ps
CPU time 88.03 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:33:23 PM PDT 24
Peak memory 201864 kb
Host smart-4bf35610-4069-4a44-a38c-d7bdea3287e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214050121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.1214050121
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.4243965460
Short name T617
Test name
Test status
Simulation time 85061534625 ps
CPU time 25.18 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:32:15 PM PDT 24
Peak memory 201888 kb
Host smart-d914d139-5e19-48e2-acd1-0a662215da28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243965460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.4243965460
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3960248006
Short name T523
Test name
Test status
Simulation time 3198120706 ps
CPU time 8.74 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:32:03 PM PDT 24
Peak memory 201640 kb
Host smart-6454bf28-82a9-42fd-bdeb-06d647f94ab5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960248006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.3960248006
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.2180531408
Short name T230
Test name
Test status
Simulation time 2463734729 ps
CPU time 6.52 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:31:58 PM PDT 24
Peak memory 201664 kb
Host smart-a2c13e1d-0a99-4045-a556-471f73bcb327
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180531408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.2180531408
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1234683983
Short name T635
Test name
Test status
Simulation time 2611518056 ps
CPU time 7.41 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:32:01 PM PDT 24
Peak memory 201648 kb
Host smart-e47383ce-ab17-4340-99a8-622b0e83179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234683983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.1234683983
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3570659942
Short name T562
Test name
Test status
Simulation time 2493289772 ps
CPU time 2.43 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:31:57 PM PDT 24
Peak memory 201632 kb
Host smart-6454a187-214a-4cb5-8b0e-d233df77fc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570659942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.3570659942
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.2973697137
Short name T476
Test name
Test status
Simulation time 2133055082 ps
CPU time 1.31 seconds
Started Jul 05 05:31:57 PM PDT 24
Finished Jul 05 05:32:00 PM PDT 24
Peak memory 201556 kb
Host smart-6aa41ba6-aa26-435d-90bc-cb142acea0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973697137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.2973697137
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1660940907
Short name T405
Test name
Test status
Simulation time 2521772960 ps
CPU time 2.3 seconds
Started Jul 05 05:31:53 PM PDT 24
Finished Jul 05 05:31:57 PM PDT 24
Peak memory 201644 kb
Host smart-471d882c-4eb6-44a6-ab79-b3c0cbc023ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660940907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1660940907
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.1566078857
Short name T559
Test name
Test status
Simulation time 2129044911 ps
CPU time 1.96 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:31:57 PM PDT 24
Peak memory 201556 kb
Host smart-3ec70e61-1bb2-4794-9e4c-1100699700ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566078857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1566078857
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.3765983807
Short name T426
Test name
Test status
Simulation time 10108664088 ps
CPU time 13.96 seconds
Started Jul 05 05:31:54 PM PDT 24
Finished Jul 05 05:32:10 PM PDT 24
Peak memory 201728 kb
Host smart-0547fbc1-7f50-4d68-97c8-1bbb91d596ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765983807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.3765983807
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.2374296977
Short name T586
Test name
Test status
Simulation time 2042947024 ps
CPU time 1.81 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 201664 kb
Host smart-63bc76cd-6ebc-438c-8cc7-e00f6879911f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374296977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.2374296977
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.310112054
Short name T215
Test name
Test status
Simulation time 2973730308 ps
CPU time 8.2 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:32:00 PM PDT 24
Peak memory 201696 kb
Host smart-768433f4-d5c7-4053-aa9c-5102000c8859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310112054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.310112054
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1530363154
Short name T33
Test name
Test status
Simulation time 164521042806 ps
CPU time 398.53 seconds
Started Jul 05 05:31:55 PM PDT 24
Finished Jul 05 05:38:35 PM PDT 24
Peak memory 201932 kb
Host smart-463ae9ee-40a1-4580-8b9b-e802f6c1f6f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530363154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.1530363154
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3527610331
Short name T779
Test name
Test status
Simulation time 34694936720 ps
CPU time 24.25 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:32:19 PM PDT 24
Peak memory 201964 kb
Host smart-b3e187c3-f22e-4475-9af6-6732fe4f8dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527610331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.3527610331
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1513873455
Short name T623
Test name
Test status
Simulation time 2695303012 ps
CPU time 3.86 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:56 PM PDT 24
Peak memory 201636 kb
Host smart-d0a197c4-55ed-4fff-982d-ed9b4d6ac253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513873455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.1513873455
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.3951449432
Short name T181
Test name
Test status
Simulation time 3627992086 ps
CPU time 2.33 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:31:58 PM PDT 24
Peak memory 201688 kb
Host smart-863c8b30-cb59-475c-a140-ae0bfef21af4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951449432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.3951449432
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3610455685
Short name T537
Test name
Test status
Simulation time 2611221361 ps
CPU time 7.26 seconds
Started Jul 05 05:32:14 PM PDT 24
Finished Jul 05 05:32:22 PM PDT 24
Peak memory 201652 kb
Host smart-6b71b9e7-5285-400c-9b28-208a8fd54c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610455685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.3610455685
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.3247907178
Short name T68
Test name
Test status
Simulation time 2488812160 ps
CPU time 2.48 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:55 PM PDT 24
Peak memory 201656 kb
Host smart-39d1f317-e03b-489a-85df-dde07e4a36fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247907178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.3247907178
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2426115444
Short name T752
Test name
Test status
Simulation time 2186275400 ps
CPU time 4.77 seconds
Started Jul 05 05:31:49 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 201552 kb
Host smart-664eb32d-f2b1-4e71-b3a0-b272b89bb203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426115444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2426115444
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.864995183
Short name T518
Test name
Test status
Simulation time 2524108269 ps
CPU time 2.15 seconds
Started Jul 05 05:31:53 PM PDT 24
Finished Jul 05 05:31:58 PM PDT 24
Peak memory 201652 kb
Host smart-814f5e5b-780c-4350-bd35-148da0e98b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864995183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.864995183
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.3730843528
Short name T176
Test name
Test status
Simulation time 2125901614 ps
CPU time 2.02 seconds
Started Jul 05 05:31:49 PM PDT 24
Finished Jul 05 05:31:52 PM PDT 24
Peak memory 201600 kb
Host smart-e366827a-3b9b-4a46-a66b-bc2b1e193beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730843528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3730843528
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.1921133622
Short name T408
Test name
Test status
Simulation time 10449035885 ps
CPU time 28.24 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:32:20 PM PDT 24
Peak memory 201688 kb
Host smart-516b86ec-2ce6-4bb8-b2cf-83b0a8f9e222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921133622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.1921133622
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2136533398
Short name T257
Test name
Test status
Simulation time 516219699317 ps
CPU time 281.76 seconds
Started Jul 05 05:31:55 PM PDT 24
Finished Jul 05 05:36:38 PM PDT 24
Peak memory 210344 kb
Host smart-d16061ee-4e11-4490-ad93-2b0153a1ced1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136533398 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2136533398
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1446030789
Short name T141
Test name
Test status
Simulation time 3749663330 ps
CPU time 3.61 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:57 PM PDT 24
Peak memory 201592 kb
Host smart-9c8aceda-9c43-4607-bce3-e923905cea82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446030789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.1446030789
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.2107087828
Short name T183
Test name
Test status
Simulation time 2014436035 ps
CPU time 5.5 seconds
Started Jul 05 05:32:03 PM PDT 24
Finished Jul 05 05:32:10 PM PDT 24
Peak memory 201664 kb
Host smart-c4c84c23-7d26-4a72-be55-10b6ff52b152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107087828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.2107087828
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.716781182
Short name T643
Test name
Test status
Simulation time 3636319756 ps
CPU time 4.92 seconds
Started Jul 05 05:31:52 PM PDT 24
Finished Jul 05 05:32:00 PM PDT 24
Peak memory 201728 kb
Host smart-d3dd0433-280a-4450-a11a-63235d107c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716781182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.716781182
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.310716405
Short name T175
Test name
Test status
Simulation time 107288873793 ps
CPU time 294.06 seconds
Started Jul 05 05:31:53 PM PDT 24
Finished Jul 05 05:36:50 PM PDT 24
Peak memory 201888 kb
Host smart-1726c13f-feda-4534-946e-963ed4661495
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310716405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.310716405
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1377595032
Short name T687
Test name
Test status
Simulation time 63694799321 ps
CPU time 158.64 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:34:32 PM PDT 24
Peak memory 201852 kb
Host smart-561a0fbd-0709-430f-a4f0-eaf830614abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377595032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.1377595032
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.395160618
Short name T256
Test name
Test status
Simulation time 2970087766 ps
CPU time 1.25 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 201548 kb
Host smart-419b2703-ec33-4ac8-9332-a32960be07c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395160618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ec_pwr_on_rst.395160618
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.3653640056
Short name T108
Test name
Test status
Simulation time 2771899778 ps
CPU time 7.31 seconds
Started Jul 05 05:31:56 PM PDT 24
Finished Jul 05 05:32:04 PM PDT 24
Peak memory 201648 kb
Host smart-b003f098-e8c2-41b8-be18-426e407f71c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653640056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.3653640056
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.4097625196
Short name T389
Test name
Test status
Simulation time 2610701465 ps
CPU time 7.8 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:32:00 PM PDT 24
Peak memory 201616 kb
Host smart-a1a91f7e-1c0e-48bf-a3c0-4679f98dfb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097625196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.4097625196
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1729188434
Short name T419
Test name
Test status
Simulation time 2464350693 ps
CPU time 7.97 seconds
Started Jul 05 05:31:54 PM PDT 24
Finished Jul 05 05:32:04 PM PDT 24
Peak memory 201668 kb
Host smart-11ce38c3-cae6-44b1-a0bd-eb8c2120adab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729188434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1729188434
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1145234354
Short name T249
Test name
Test status
Simulation time 2078941913 ps
CPU time 5.85 seconds
Started Jul 05 05:31:54 PM PDT 24
Finished Jul 05 05:32:02 PM PDT 24
Peak memory 201516 kb
Host smart-cec1fb09-fe19-45aa-ab6f-90534ae8a3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145234354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1145234354
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.4151344138
Short name T471
Test name
Test status
Simulation time 2524363754 ps
CPU time 2.43 seconds
Started Jul 05 05:31:50 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 201664 kb
Host smart-20620cd9-32aa-46ef-b9a9-a96badb09f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151344138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.4151344138
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.3242980558
Short name T653
Test name
Test status
Simulation time 2107616425 ps
CPU time 5.38 seconds
Started Jul 05 05:31:51 PM PDT 24
Finished Jul 05 05:31:58 PM PDT 24
Peak memory 201592 kb
Host smart-22c72cdd-3e9f-4251-a39e-3e650b3333d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242980558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3242980558
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.2066925212
Short name T96
Test name
Test status
Simulation time 15667167081 ps
CPU time 14.3 seconds
Started Jul 05 05:31:54 PM PDT 24
Finished Jul 05 05:32:10 PM PDT 24
Peak memory 201664 kb
Host smart-5db1d5f6-c94f-49f6-92f3-1b619a53373a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066925212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.2066925212
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3123508302
Short name T71
Test name
Test status
Simulation time 24687485671 ps
CPU time 60.52 seconds
Started Jul 05 05:31:57 PM PDT 24
Finished Jul 05 05:32:59 PM PDT 24
Peak memory 213756 kb
Host smart-3fae3bab-3d4a-4d2b-8920-267b6bdad1e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123508302 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.3123508302
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.1473956602
Short name T219
Test name
Test status
Simulation time 5001180129 ps
CPU time 2.02 seconds
Started Jul 05 05:31:53 PM PDT 24
Finished Jul 05 05:31:57 PM PDT 24
Peak memory 201604 kb
Host smart-ff07a162-3ec1-4aef-8fca-76a6ca5fde82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473956602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.1473956602
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.572387579
Short name T178
Test name
Test status
Simulation time 2021742764 ps
CPU time 3.17 seconds
Started Jul 05 05:31:58 PM PDT 24
Finished Jul 05 05:32:03 PM PDT 24
Peak memory 201620 kb
Host smart-e9ecea7b-7356-4ff3-80d0-75f5ec882049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572387579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_tes
t.572387579
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2490465028
Short name T544
Test name
Test status
Simulation time 3663551399 ps
CPU time 4.92 seconds
Started Jul 05 05:32:01 PM PDT 24
Finished Jul 05 05:32:07 PM PDT 24
Peak memory 201616 kb
Host smart-ec73c465-fa1e-4cf5-9476-bc0508613406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490465028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.2
490465028
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.3639112652
Short name T32
Test name
Test status
Simulation time 36057902828 ps
CPU time 47.38 seconds
Started Jul 05 05:31:57 PM PDT 24
Finished Jul 05 05:32:46 PM PDT 24
Peak memory 201916 kb
Host smart-e5c3d2a8-1d2e-4849-8cf0-352090eabc28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639112652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.3639112652
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3043705998
Short name T463
Test name
Test status
Simulation time 5281951205 ps
CPU time 3.85 seconds
Started Jul 05 05:31:58 PM PDT 24
Finished Jul 05 05:32:04 PM PDT 24
Peak memory 201664 kb
Host smart-3fd931e3-c768-4257-aa43-62f64f9802a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043705998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.3043705998
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3321553435
Short name T43
Test name
Test status
Simulation time 2727757305 ps
CPU time 4.39 seconds
Started Jul 05 05:32:01 PM PDT 24
Finished Jul 05 05:32:07 PM PDT 24
Peak memory 201628 kb
Host smart-62b9b32b-3cab-424d-9c33-6e8892568b87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321553435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.3321553435
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1146767301
Short name T536
Test name
Test status
Simulation time 2636761151 ps
CPU time 1.82 seconds
Started Jul 05 05:32:01 PM PDT 24
Finished Jul 05 05:32:05 PM PDT 24
Peak memory 201664 kb
Host smart-2e820dd0-7b4e-4b54-956d-732d0b442628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146767301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1146767301
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2144083015
Short name T567
Test name
Test status
Simulation time 2449225890 ps
CPU time 6.51 seconds
Started Jul 05 05:32:03 PM PDT 24
Finished Jul 05 05:32:10 PM PDT 24
Peak memory 201664 kb
Host smart-107e2fe7-9fe6-415d-9a20-10bc23fdf5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144083015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2144083015
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.991326854
Short name T605
Test name
Test status
Simulation time 2115294960 ps
CPU time 5.83 seconds
Started Jul 05 05:32:00 PM PDT 24
Finished Jul 05 05:32:07 PM PDT 24
Peak memory 201516 kb
Host smart-20579403-882f-4a1a-8f98-18f7d91e08ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991326854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.991326854
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2429786902
Short name T424
Test name
Test status
Simulation time 2542105992 ps
CPU time 1.84 seconds
Started Jul 05 05:32:00 PM PDT 24
Finished Jul 05 05:32:04 PM PDT 24
Peak memory 201556 kb
Host smart-8cc98f66-715a-41a6-b5da-3aaa776f715c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429786902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2429786902
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.4261075824
Short name T429
Test name
Test status
Simulation time 2110612834 ps
CPU time 6.11 seconds
Started Jul 05 05:31:57 PM PDT 24
Finished Jul 05 05:32:06 PM PDT 24
Peak memory 201536 kb
Host smart-1e020d80-15d0-4167-bb2a-554291317a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261075824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.4261075824
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.3018883078
Short name T364
Test name
Test status
Simulation time 7466262042 ps
CPU time 5.43 seconds
Started Jul 05 05:31:58 PM PDT 24
Finished Jul 05 05:32:06 PM PDT 24
Peak memory 201660 kb
Host smart-f87b7b84-557d-4ece-bacb-14294bec4393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018883078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.3018883078
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3106854207
Short name T782
Test name
Test status
Simulation time 6796920538 ps
CPU time 8.25 seconds
Started Jul 05 05:31:58 PM PDT 24
Finished Jul 05 05:32:09 PM PDT 24
Peak memory 201636 kb
Host smart-7f38d27c-ff7a-4230-afb1-fc4e5b6d3997
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106854207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.3106854207
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.2944915210
Short name T451
Test name
Test status
Simulation time 2015930425 ps
CPU time 5.68 seconds
Started Jul 05 05:31:58 PM PDT 24
Finished Jul 05 05:32:06 PM PDT 24
Peak memory 201656 kb
Host smart-5ac985b5-19ca-44b5-a1c9-51151663ddce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944915210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.2944915210
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2666404894
Short name T638
Test name
Test status
Simulation time 3664636871 ps
CPU time 9.47 seconds
Started Jul 05 05:31:58 PM PDT 24
Finished Jul 05 05:32:09 PM PDT 24
Peak memory 201756 kb
Host smart-0cea3e87-d52d-49d3-9ca7-cd06fe2c8e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666404894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
666404894
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1559747253
Short name T272
Test name
Test status
Simulation time 76701208307 ps
CPU time 91.48 seconds
Started Jul 05 05:32:03 PM PDT 24
Finished Jul 05 05:33:35 PM PDT 24
Peak memory 201948 kb
Host smart-54b542ae-9e45-48a3-b749-52d5bcfd0af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559747253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.1559747253
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2694671973
Short name T531
Test name
Test status
Simulation time 3948730511 ps
CPU time 9.93 seconds
Started Jul 05 05:32:01 PM PDT 24
Finished Jul 05 05:32:13 PM PDT 24
Peak memory 201528 kb
Host smart-2b035c8a-808e-4b8d-a02a-4206de02ee31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694671973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2694671973
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.677624903
Short name T260
Test name
Test status
Simulation time 4914046849 ps
CPU time 9.31 seconds
Started Jul 05 05:32:04 PM PDT 24
Finished Jul 05 05:32:14 PM PDT 24
Peak memory 201656 kb
Host smart-8b0e2c8b-2c46-407d-a19d-aa57ca66751a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677624903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctr
l_edge_detect.677624903
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3125313662
Short name T487
Test name
Test status
Simulation time 2608882297 ps
CPU time 7.34 seconds
Started Jul 05 05:32:05 PM PDT 24
Finished Jul 05 05:32:12 PM PDT 24
Peak memory 201664 kb
Host smart-b8806f3f-2a98-4dc7-b029-5610c38399cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125313662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3125313662
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2672615099
Short name T251
Test name
Test status
Simulation time 2451008285 ps
CPU time 7.32 seconds
Started Jul 05 05:32:04 PM PDT 24
Finished Jul 05 05:32:12 PM PDT 24
Peak memory 201656 kb
Host smart-f5ecd7ca-9969-4f03-a98c-933531bf44eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672615099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2672615099
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.284218693
Short name T584
Test name
Test status
Simulation time 2158680620 ps
CPU time 6.17 seconds
Started Jul 05 05:32:06 PM PDT 24
Finished Jul 05 05:32:13 PM PDT 24
Peak memory 201572 kb
Host smart-a6df4a22-1f3c-45b8-b98d-ab03bed1e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284218693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.284218693
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.1836883476
Short name T756
Test name
Test status
Simulation time 2512362329 ps
CPU time 6.82 seconds
Started Jul 05 05:31:57 PM PDT 24
Finished Jul 05 05:32:06 PM PDT 24
Peak memory 201528 kb
Host smart-a1e34c5b-4b76-481f-9582-dff6c5f0d085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836883476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.1836883476
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.238142831
Short name T735
Test name
Test status
Simulation time 2113343098 ps
CPU time 6.22 seconds
Started Jul 05 05:31:59 PM PDT 24
Finished Jul 05 05:32:07 PM PDT 24
Peak memory 201496 kb
Host smart-73e0755e-76d1-4521-9b7c-97be0cdfd314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238142831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.238142831
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.874686027
Short name T642
Test name
Test status
Simulation time 8450585576 ps
CPU time 5.97 seconds
Started Jul 05 05:32:01 PM PDT 24
Finished Jul 05 05:32:09 PM PDT 24
Peak memory 201664 kb
Host smart-a4e6e9d5-30b3-4325-b93a-a7ac09017248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874686027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_st
ress_all.874686027
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2164181305
Short name T153
Test name
Test status
Simulation time 10708817469 ps
CPU time 1.43 seconds
Started Jul 05 05:32:00 PM PDT 24
Finished Jul 05 05:32:03 PM PDT 24
Peak memory 201552 kb
Host smart-290e9257-b261-4d93-90d7-7237d603dba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164181305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2164181305
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.2013126257
Short name T137
Test name
Test status
Simulation time 2015495440 ps
CPU time 4.64 seconds
Started Jul 05 05:32:09 PM PDT 24
Finished Jul 05 05:32:15 PM PDT 24
Peak memory 201656 kb
Host smart-d1d53e7f-4909-41cf-a971-5bb324d49c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013126257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.2013126257
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2101912220
Short name T416
Test name
Test status
Simulation time 3513344866 ps
CPU time 3.03 seconds
Started Jul 05 05:33:51 PM PDT 24
Finished Jul 05 05:33:55 PM PDT 24
Peak memory 201764 kb
Host smart-7b20e173-bd23-4118-9d93-6d081446bc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101912220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2
101912220
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1353492158
Short name T356
Test name
Test status
Simulation time 121420086928 ps
CPU time 290.34 seconds
Started Jul 05 05:32:01 PM PDT 24
Finished Jul 05 05:36:53 PM PDT 24
Peak memory 201868 kb
Host smart-904d5418-ad20-4e56-a790-cefcd24cbc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353492158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.1353492158
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.890944544
Short name T729
Test name
Test status
Simulation time 3218058309 ps
CPU time 8.03 seconds
Started Jul 05 05:31:58 PM PDT 24
Finished Jul 05 05:32:08 PM PDT 24
Peak memory 201620 kb
Host smart-c08917cd-de5e-43ff-90eb-e851dc4bac38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890944544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.890944544
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3808042147
Short name T161
Test name
Test status
Simulation time 3401834967 ps
CPU time 2.58 seconds
Started Jul 05 05:32:03 PM PDT 24
Finished Jul 05 05:32:07 PM PDT 24
Peak memory 201656 kb
Host smart-a500f012-eb58-4022-81a4-8e1720f82e00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808042147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.3808042147
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2700886712
Short name T171
Test name
Test status
Simulation time 2609628365 ps
CPU time 7.77 seconds
Started Jul 05 05:32:06 PM PDT 24
Finished Jul 05 05:32:14 PM PDT 24
Peak memory 201656 kb
Host smart-97ba186c-6b99-4a6c-8049-1275439aa914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700886712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2700886712
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1080893849
Short name T422
Test name
Test status
Simulation time 2495836516 ps
CPU time 2.38 seconds
Started Jul 05 05:32:04 PM PDT 24
Finished Jul 05 05:32:07 PM PDT 24
Peak memory 201664 kb
Host smart-283f2a8d-207b-4eee-a7e4-b22d06fb9804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080893849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1080893849
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1930472151
Short name T244
Test name
Test status
Simulation time 2155386550 ps
CPU time 5.93 seconds
Started Jul 05 05:31:59 PM PDT 24
Finished Jul 05 05:32:07 PM PDT 24
Peak memory 201564 kb
Host smart-72c8c41e-826a-4204-8c0a-201d3393547a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930472151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.1930472151
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3365285631
Short name T785
Test name
Test status
Simulation time 2536673922 ps
CPU time 2.31 seconds
Started Jul 05 05:32:00 PM PDT 24
Finished Jul 05 05:32:04 PM PDT 24
Peak memory 201628 kb
Host smart-feece1b0-42df-408e-9ed2-0cd2a845eb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365285631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.3365285631
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.817806916
Short name T488
Test name
Test status
Simulation time 2111130431 ps
CPU time 5.6 seconds
Started Jul 05 05:31:59 PM PDT 24
Finished Jul 05 05:32:06 PM PDT 24
Peak memory 201576 kb
Host smart-bea39d31-3261-4f76-9c53-3f39d62d3013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817806916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.817806916
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.559059261
Short name T240
Test name
Test status
Simulation time 4895796227 ps
CPU time 2.39 seconds
Started Jul 05 05:32:00 PM PDT 24
Finished Jul 05 05:32:04 PM PDT 24
Peak memory 201620 kb
Host smart-159deeca-d4bc-4586-a222-22bcf1f26f31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559059261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ultra_low_pwr.559059261
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3751011426
Short name T509
Test name
Test status
Simulation time 2011031530 ps
CPU time 5.88 seconds
Started Jul 05 05:32:10 PM PDT 24
Finished Jul 05 05:32:17 PM PDT 24
Peak memory 201640 kb
Host smart-fd3b4125-6f50-4bf6-9b00-3fdd99a62d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751011426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3751011426
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.130736690
Short name T557
Test name
Test status
Simulation time 3347767246 ps
CPU time 8.95 seconds
Started Jul 05 05:32:08 PM PDT 24
Finished Jul 05 05:32:18 PM PDT 24
Peak memory 201728 kb
Host smart-50358934-5d1c-467f-b12d-934401e79a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130736690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.130736690
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3559115801
Short name T247
Test name
Test status
Simulation time 179177572421 ps
CPU time 427.9 seconds
Started Jul 05 05:32:09 PM PDT 24
Finished Jul 05 05:39:18 PM PDT 24
Peak memory 201852 kb
Host smart-4f746e62-ab47-4115-bb83-64d64665ef0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559115801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.3559115801
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2039079694
Short name T543
Test name
Test status
Simulation time 3330594166 ps
CPU time 9.24 seconds
Started Jul 05 05:32:12 PM PDT 24
Finished Jul 05 05:32:22 PM PDT 24
Peak memory 201624 kb
Host smart-7baab064-fd24-4a2c-b5c2-6dab09098e8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039079694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.2039079694
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.447936119
Short name T2
Test name
Test status
Simulation time 2756862082 ps
CPU time 1.55 seconds
Started Jul 05 05:32:08 PM PDT 24
Finished Jul 05 05:32:10 PM PDT 24
Peak memory 201656 kb
Host smart-67ebce65-aa38-43b3-b7e0-2318d3e5673d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447936119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.447936119
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3773244207
Short name T470
Test name
Test status
Simulation time 2676333031 ps
CPU time 1.4 seconds
Started Jul 05 05:32:09 PM PDT 24
Finished Jul 05 05:32:11 PM PDT 24
Peak memory 201664 kb
Host smart-8bc1acc7-64ac-4f40-ad25-479795141463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773244207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3773244207
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3558714350
Short name T421
Test name
Test status
Simulation time 2456927428 ps
CPU time 7.2 seconds
Started Jul 05 05:32:05 PM PDT 24
Finished Jul 05 05:32:12 PM PDT 24
Peak memory 201668 kb
Host smart-68a2201c-725a-4af2-892c-cace3470fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558714350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3558714350
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3954955480
Short name T60
Test name
Test status
Simulation time 2126219936 ps
CPU time 3.17 seconds
Started Jul 05 05:32:08 PM PDT 24
Finished Jul 05 05:32:12 PM PDT 24
Peak memory 201452 kb
Host smart-705e8780-4931-4039-9584-deae4b6c371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954955480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.3954955480
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.4220316887
Short name T655
Test name
Test status
Simulation time 2510046185 ps
CPU time 7.62 seconds
Started Jul 05 05:32:11 PM PDT 24
Finished Jul 05 05:32:19 PM PDT 24
Peak memory 201644 kb
Host smart-d7800eb7-5ed4-4bc0-b4e3-2da907f0fee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220316887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.4220316887
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.1954543651
Short name T200
Test name
Test status
Simulation time 2109698872 ps
CPU time 5.64 seconds
Started Jul 05 05:32:07 PM PDT 24
Finished Jul 05 05:32:13 PM PDT 24
Peak memory 201488 kb
Host smart-68f3c295-2a97-4bb6-8686-bbf9bc3fd607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954543651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.1954543651
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.3927803592
Short name T362
Test name
Test status
Simulation time 103956060670 ps
CPU time 276.17 seconds
Started Jul 05 05:32:08 PM PDT 24
Finished Jul 05 05:36:45 PM PDT 24
Peak memory 201892 kb
Host smart-ada50a9e-61fa-46d6-b8cc-6ba94fe98c1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927803592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.3927803592
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1531105479
Short name T168
Test name
Test status
Simulation time 95972370170 ps
CPU time 110.25 seconds
Started Jul 05 05:32:07 PM PDT 24
Finished Jul 05 05:33:59 PM PDT 24
Peak memory 218224 kb
Host smart-d6f0c2fc-eb13-4adb-994e-26d744dd6da5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531105479 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.1531105479
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3865662317
Short name T622
Test name
Test status
Simulation time 5926229084 ps
CPU time 1.21 seconds
Started Jul 05 05:32:08 PM PDT 24
Finished Jul 05 05:32:11 PM PDT 24
Peak memory 201640 kb
Host smart-a67cbca8-c03e-42c9-ae1a-20da8e9c933e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865662317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.3865662317
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.370874147
Short name T575
Test name
Test status
Simulation time 2062529983 ps
CPU time 1.22 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 201664 kb
Host smart-3932c9d6-9a46-4e75-8c3e-1ff512095f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370874147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test
.370874147
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.39960784
Short name T15
Test name
Test status
Simulation time 3325488203 ps
CPU time 4.59 seconds
Started Jul 05 05:30:34 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201632 kb
Host smart-bf518ce8-6054-42d6-ad0e-6740ca7fb5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39960784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.39960784
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.763515477
Short name T723
Test name
Test status
Simulation time 96241334414 ps
CPU time 63.07 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:31:40 PM PDT 24
Peak memory 201876 kb
Host smart-98098f76-358e-420f-b7ef-e6838185337d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763515477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_combo_detect.763515477
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1856970440
Short name T778
Test name
Test status
Simulation time 2151832558 ps
CPU time 5.95 seconds
Started Jul 05 05:30:26 PM PDT 24
Finished Jul 05 05:30:33 PM PDT 24
Peak memory 201660 kb
Host smart-9cc5ee50-2187-4cd1-a7f4-639c22be13ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856970440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.1856970440
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2348246593
Short name T765
Test name
Test status
Simulation time 2317366139 ps
CPU time 2.19 seconds
Started Jul 05 05:30:27 PM PDT 24
Finished Jul 05 05:30:30 PM PDT 24
Peak memory 201616 kb
Host smart-a618795c-3b97-41a0-9502-501312116e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348246593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2348246593
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.285959959
Short name T775
Test name
Test status
Simulation time 83053693064 ps
CPU time 55 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:31:31 PM PDT 24
Peak memory 201856 kb
Host smart-3d9a5bad-d8aa-41d6-a156-56c98d478e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285959959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wit
h_pre_cond.285959959
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1608622783
Short name T555
Test name
Test status
Simulation time 3133403825 ps
CPU time 2.59 seconds
Started Jul 05 05:30:37 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201612 kb
Host smart-e60cc49b-2e77-439f-ada9-d33c361a5547
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608622783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1608622783
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.424737314
Short name T189
Test name
Test status
Simulation time 4309528792 ps
CPU time 8.24 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:46 PM PDT 24
Peak memory 201688 kb
Host smart-761e6542-fe99-4715-9824-dbe7e5ed6538
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424737314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_edge_detect.424737314
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.685953684
Short name T679
Test name
Test status
Simulation time 2610599220 ps
CPU time 6.92 seconds
Started Jul 05 05:30:34 PM PDT 24
Finished Jul 05 05:30:42 PM PDT 24
Peak memory 201644 kb
Host smart-3f7f125f-f791-47be-8d45-7055272891c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685953684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.685953684
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2642027006
Short name T614
Test name
Test status
Simulation time 2483437818 ps
CPU time 1.81 seconds
Started Jul 05 05:30:30 PM PDT 24
Finished Jul 05 05:30:32 PM PDT 24
Peak memory 201640 kb
Host smart-4d0d2557-2748-48ae-8784-dd4ae34e7213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642027006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.2642027006
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2432944703
Short name T513
Test name
Test status
Simulation time 2074493723 ps
CPU time 1.98 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201488 kb
Host smart-6ba9c6c8-15d4-4bef-97fe-96af6ad6cf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432944703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.2432944703
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1150860961
Short name T616
Test name
Test status
Simulation time 2575969051 ps
CPU time 1.47 seconds
Started Jul 05 05:30:34 PM PDT 24
Finished Jul 05 05:30:36 PM PDT 24
Peak memory 201644 kb
Host smart-7b759760-a381-4d53-adf3-b41d264f5fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150860961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1150860961
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.129788757
Short name T16
Test name
Test status
Simulation time 22008585723 ps
CPU time 57.75 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:31:34 PM PDT 24
Peak memory 221224 kb
Host smart-af1578bd-4aba-4dda-ace6-669f1d855379
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129788757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.129788757
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.1151871185
Short name T132
Test name
Test status
Simulation time 2111668805 ps
CPU time 6.16 seconds
Started Jul 05 05:30:32 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 201348 kb
Host smart-5f26cf55-5f06-4b05-9814-8edbc31e3396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151871185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1151871185
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2467850460
Short name T84
Test name
Test status
Simulation time 68262888780 ps
CPU time 43.28 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:31:19 PM PDT 24
Peak memory 210264 kb
Host smart-54b95d96-ace0-4b8a-99ee-f17aebdd27b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467850460 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2467850460
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2532747732
Short name T583
Test name
Test status
Simulation time 7689578402 ps
CPU time 6.46 seconds
Started Jul 05 05:30:41 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201680 kb
Host smart-d7667d51-4a48-4830-b849-1124f1e5ac7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532747732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.2532747732
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.113565821
Short name T498
Test name
Test status
Simulation time 2101650902 ps
CPU time 1.18 seconds
Started Jul 05 05:32:21 PM PDT 24
Finished Jul 05 05:32:23 PM PDT 24
Peak memory 201692 kb
Host smart-e398eb00-ab9d-4095-ae99-f02644112d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113565821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.113565821
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.508090101
Short name T264
Test name
Test status
Simulation time 3622585519 ps
CPU time 9.74 seconds
Started Jul 05 05:32:09 PM PDT 24
Finished Jul 05 05:32:20 PM PDT 24
Peak memory 201692 kb
Host smart-ec06f440-2608-48b3-95c1-29ed0f603930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508090101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.508090101
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.2365622597
Short name T363
Test name
Test status
Simulation time 145568498536 ps
CPU time 171.02 seconds
Started Jul 05 05:32:11 PM PDT 24
Finished Jul 05 05:35:03 PM PDT 24
Peak memory 201864 kb
Host smart-464ea04f-5858-4ef9-8b79-5fe4f0a94572
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365622597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.2365622597
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.122631837
Short name T527
Test name
Test status
Simulation time 4579486424 ps
CPU time 6.61 seconds
Started Jul 05 05:32:07 PM PDT 24
Finished Jul 05 05:32:15 PM PDT 24
Peak memory 201636 kb
Host smart-1c355d94-8f5d-4b6a-8f75-224d21b495f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122631837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ec_pwr_on_rst.122631837
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.606217975
Short name T694
Test name
Test status
Simulation time 3763871709 ps
CPU time 3.16 seconds
Started Jul 05 05:32:11 PM PDT 24
Finished Jul 05 05:32:15 PM PDT 24
Peak memory 201580 kb
Host smart-2fded41d-c564-42f5-a66b-41ccb4ac5f43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606217975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctr
l_edge_detect.606217975
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1646769092
Short name T432
Test name
Test status
Simulation time 2631484165 ps
CPU time 2.34 seconds
Started Jul 05 05:32:11 PM PDT 24
Finished Jul 05 05:32:14 PM PDT 24
Peak memory 201652 kb
Host smart-4d8156d2-c834-4c14-90f0-d4db60748c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646769092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1646769092
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.4205902778
Short name T481
Test name
Test status
Simulation time 2489247311 ps
CPU time 2.26 seconds
Started Jul 05 05:32:11 PM PDT 24
Finished Jul 05 05:32:14 PM PDT 24
Peak memory 201584 kb
Host smart-442d7859-994f-42cb-9584-842d683aaafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205902778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.4205902778
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.376633010
Short name T777
Test name
Test status
Simulation time 2102322079 ps
CPU time 1.54 seconds
Started Jul 05 05:32:08 PM PDT 24
Finished Jul 05 05:32:11 PM PDT 24
Peak memory 201512 kb
Host smart-2a3fb391-7abb-46c4-a6e1-550aaeccbfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376633010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.376633010
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3345996157
Short name T297
Test name
Test status
Simulation time 2529780930 ps
CPU time 2.26 seconds
Started Jul 05 05:32:09 PM PDT 24
Finished Jul 05 05:32:12 PM PDT 24
Peak memory 201656 kb
Host smart-8b6ae90c-d29f-469b-8368-ddfe1e4f6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345996157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3345996157
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.1174452966
Short name T598
Test name
Test status
Simulation time 2127863648 ps
CPU time 1.87 seconds
Started Jul 05 05:32:08 PM PDT 24
Finished Jul 05 05:32:10 PM PDT 24
Peak memory 201552 kb
Host smart-9146ec17-3a7a-4352-bcca-2862534af223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174452966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.1174452966
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.296081291
Short name T482
Test name
Test status
Simulation time 11854897460 ps
CPU time 32.48 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:32:51 PM PDT 24
Peak memory 201648 kb
Host smart-17e68f32-b402-4745-8704-1ed02fb03358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296081291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_st
ress_all.296081291
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1495255204
Short name T64
Test name
Test status
Simulation time 2478499499 ps
CPU time 5.67 seconds
Started Jul 05 05:32:06 PM PDT 24
Finished Jul 05 05:32:12 PM PDT 24
Peak memory 201668 kb
Host smart-13fa3318-8958-4c94-91e7-921867de589a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495255204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.1495255204
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.912413777
Short name T724
Test name
Test status
Simulation time 2014852957 ps
CPU time 5.78 seconds
Started Jul 05 05:32:20 PM PDT 24
Finished Jul 05 05:32:27 PM PDT 24
Peak memory 201660 kb
Host smart-7de7f75c-d23a-49f3-82c3-61180a260981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912413777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_tes
t.912413777
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3277953590
Short name T54
Test name
Test status
Simulation time 3366976772 ps
CPU time 4.95 seconds
Started Jul 05 05:32:19 PM PDT 24
Finished Jul 05 05:32:26 PM PDT 24
Peak memory 201724 kb
Host smart-7c878a42-3a40-4f5a-962f-7cd982ea03f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277953590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3
277953590
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.3471255383
Short name T12
Test name
Test status
Simulation time 115199989271 ps
CPU time 23.66 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201948 kb
Host smart-7971a8a3-a688-4076-b0e4-3ee850f64bed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471255383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.3471255383
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.4268465136
Short name T276
Test name
Test status
Simulation time 75797477824 ps
CPU time 99.98 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:34:00 PM PDT 24
Peak memory 201852 kb
Host smart-f8bc56fa-2346-4bf8-bc22-8a8d8218e9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268465136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.4268465136
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4217564662
Short name T542
Test name
Test status
Simulation time 3081767207 ps
CPU time 4.48 seconds
Started Jul 05 05:32:17 PM PDT 24
Finished Jul 05 05:32:22 PM PDT 24
Peak memory 201640 kb
Host smart-04a2905b-5ce5-4267-99d5-2aecb82520af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217564662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.4217564662
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3421264364
Short name T227
Test name
Test status
Simulation time 3790691528 ps
CPU time 5.05 seconds
Started Jul 05 05:32:20 PM PDT 24
Finished Jul 05 05:32:26 PM PDT 24
Peak memory 201700 kb
Host smart-da775b0c-6675-4a81-8ddd-29813c9fb394
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421264364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.3421264364
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1827232257
Short name T545
Test name
Test status
Simulation time 2608304593 ps
CPU time 7.06 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:32:27 PM PDT 24
Peak memory 201660 kb
Host smart-bbaaf86a-9d57-4752-8a78-d2197d60bf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827232257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1827232257
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.279331606
Short name T295
Test name
Test status
Simulation time 2474666722 ps
CPU time 2.17 seconds
Started Jul 05 05:32:20 PM PDT 24
Finished Jul 05 05:32:23 PM PDT 24
Peak memory 201640 kb
Host smart-3fb37484-6096-4eb6-861b-8db6861767b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279331606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.279331606
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1775036656
Short name T787
Test name
Test status
Simulation time 2221776148 ps
CPU time 5.17 seconds
Started Jul 05 05:32:21 PM PDT 24
Finished Jul 05 05:32:27 PM PDT 24
Peak memory 201652 kb
Host smart-d78a56a2-3bbf-4a42-b695-f4e403a04c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775036656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1775036656
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1038764538
Short name T539
Test name
Test status
Simulation time 2530918806 ps
CPU time 2.27 seconds
Started Jul 05 05:32:20 PM PDT 24
Finished Jul 05 05:32:23 PM PDT 24
Peak memory 201644 kb
Host smart-4121312e-1061-4b4d-ba58-6ddeb4fb458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038764538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.1038764538
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.2991732944
Short name T674
Test name
Test status
Simulation time 2223811102 ps
CPU time 0.88 seconds
Started Jul 05 05:32:22 PM PDT 24
Finished Jul 05 05:32:24 PM PDT 24
Peak memory 201608 kb
Host smart-2ff584b3-e50a-4dee-841c-a1cb581a7139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991732944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.2991732944
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.2644181550
Short name T701
Test name
Test status
Simulation time 195498197817 ps
CPU time 520.39 seconds
Started Jul 05 05:32:20 PM PDT 24
Finished Jul 05 05:41:01 PM PDT 24
Peak memory 201820 kb
Host smart-f0e87063-6b07-4b32-a0e8-22c7785a3c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644181550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.2644181550
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.577786780
Short name T570
Test name
Test status
Simulation time 11041157918 ps
CPU time 2.38 seconds
Started Jul 05 05:32:19 PM PDT 24
Finished Jul 05 05:32:23 PM PDT 24
Peak memory 201648 kb
Host smart-6af7510a-ce9f-4259-81bf-5fe09b7316f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577786780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ultra_low_pwr.577786780
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.2707379020
Short name T406
Test name
Test status
Simulation time 2016857882 ps
CPU time 3.15 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:32:22 PM PDT 24
Peak memory 201660 kb
Host smart-82fa22cd-7826-4784-b5e7-fb55ec34ad21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707379020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.2707379020
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.4068480675
Short name T242
Test name
Test status
Simulation time 3758511880 ps
CPU time 10.18 seconds
Started Jul 05 05:32:19 PM PDT 24
Finished Jul 05 05:32:31 PM PDT 24
Peak memory 201700 kb
Host smart-d28e02b3-66fd-4b1a-b1cb-b14b6864ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068480675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.4
068480675
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.2540414308
Short name T433
Test name
Test status
Simulation time 84794581332 ps
CPU time 217.86 seconds
Started Jul 05 05:32:20 PM PDT 24
Finished Jul 05 05:35:59 PM PDT 24
Peak memory 201856 kb
Host smart-accfd080-78e4-433a-8d3a-8ca810954c20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540414308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.2540414308
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.652869226
Short name T285
Test name
Test status
Simulation time 37386046662 ps
CPU time 93.69 seconds
Started Jul 05 05:32:19 PM PDT 24
Finished Jul 05 05:33:54 PM PDT 24
Peak memory 201868 kb
Host smart-c54c3af0-b1fa-406f-b709-4f50e2747047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652869226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_wi
th_pre_cond.652869226
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3699678903
Short name T446
Test name
Test status
Simulation time 5039441481 ps
CPU time 7.51 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:32:27 PM PDT 24
Peak memory 201640 kb
Host smart-9170eb61-eee1-4318-a45b-b6c48ed35daa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699678903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.3699678903
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3552589331
Short name T195
Test name
Test status
Simulation time 395568232583 ps
CPU time 1038.56 seconds
Started Jul 05 05:32:17 PM PDT 24
Finished Jul 05 05:49:36 PM PDT 24
Peak memory 201648 kb
Host smart-838eeb31-646d-4236-a52b-70057beaf300
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552589331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.3552589331
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.922061029
Short name T444
Test name
Test status
Simulation time 2633650497 ps
CPU time 2.45 seconds
Started Jul 05 05:32:21 PM PDT 24
Finished Jul 05 05:32:24 PM PDT 24
Peak memory 201600 kb
Host smart-f0d1726b-0319-49de-bbe4-a395f4c1d52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922061029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.922061029
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1921022660
Short name T468
Test name
Test status
Simulation time 2443955535 ps
CPU time 3.9 seconds
Started Jul 05 05:32:19 PM PDT 24
Finished Jul 05 05:32:24 PM PDT 24
Peak memory 201656 kb
Host smart-9f8deaf0-5744-402c-80cb-1c7580addef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921022660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.1921022660
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.473692763
Short name T624
Test name
Test status
Simulation time 2080360816 ps
CPU time 1.92 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:32:21 PM PDT 24
Peak memory 201508 kb
Host smart-51c64e52-ddb8-4b05-9863-a08dc03ddf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473692763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.473692763
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.4093029069
Short name T508
Test name
Test status
Simulation time 2536679669 ps
CPU time 2.35 seconds
Started Jul 05 05:32:17 PM PDT 24
Finished Jul 05 05:32:20 PM PDT 24
Peak memory 201524 kb
Host smart-fafcd84f-8f19-4819-964d-9b982268c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093029069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.4093029069
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.2869487876
Short name T741
Test name
Test status
Simulation time 2112005734 ps
CPU time 6.18 seconds
Started Jul 05 05:32:17 PM PDT 24
Finished Jul 05 05:32:24 PM PDT 24
Peak memory 201408 kb
Host smart-76a8ecc8-4b6c-4fbf-beb8-9f6bd1d83351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869487876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2869487876
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.4205540024
Short name T211
Test name
Test status
Simulation time 3138488770 ps
CPU time 2.37 seconds
Started Jul 05 05:32:21 PM PDT 24
Finished Jul 05 05:32:24 PM PDT 24
Peak memory 201696 kb
Host smart-9d101e52-c262-4a35-be18-48a3cbe47cd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205540024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.4205540024
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.1835557898
Short name T393
Test name
Test status
Simulation time 2012851334 ps
CPU time 6.22 seconds
Started Jul 05 05:32:30 PM PDT 24
Finished Jul 05 05:32:37 PM PDT 24
Peak memory 201664 kb
Host smart-6267ae9a-7860-47a9-9b20-ed0963d8b794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835557898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.1835557898
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.950225400
Short name T415
Test name
Test status
Simulation time 3189206803 ps
CPU time 2.67 seconds
Started Jul 05 05:32:21 PM PDT 24
Finished Jul 05 05:32:24 PM PDT 24
Peak memory 201636 kb
Host smart-3cbe3407-2643-44f3-9ea3-8ac8f3dde960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950225400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.950225400
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.2741498459
Short name T745
Test name
Test status
Simulation time 198253957825 ps
CPU time 528.27 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:41:08 PM PDT 24
Peak memory 201820 kb
Host smart-99cd91d2-6964-4c14-a6a3-98ce284f14ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741498459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.2741498459
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.310539378
Short name T448
Test name
Test status
Simulation time 2765749285 ps
CPU time 7.6 seconds
Started Jul 05 05:32:17 PM PDT 24
Finished Jul 05 05:32:26 PM PDT 24
Peak memory 201640 kb
Host smart-109b2da5-3b21-4990-bb44-bbadf6517860
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310539378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_ec_pwr_on_rst.310539378
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.2068760483
Short name T190
Test name
Test status
Simulation time 3780874543 ps
CPU time 8.23 seconds
Started Jul 05 05:32:19 PM PDT 24
Finished Jul 05 05:32:29 PM PDT 24
Peak memory 201664 kb
Host smart-6533ad4a-d2d0-4ba6-b624-09bac9e4229b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068760483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.2068760483
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3309632921
Short name T213
Test name
Test status
Simulation time 2633550868 ps
CPU time 2.33 seconds
Started Jul 05 05:32:21 PM PDT 24
Finished Jul 05 05:32:25 PM PDT 24
Peak memory 201664 kb
Host smart-600805c4-b14c-4852-bccf-75145102c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309632921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.3309632921
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3386434406
Short name T293
Test name
Test status
Simulation time 2459805612 ps
CPU time 3.69 seconds
Started Jul 05 05:32:17 PM PDT 24
Finished Jul 05 05:32:22 PM PDT 24
Peak memory 201668 kb
Host smart-e1c4cba5-2abe-49a0-8593-75ef18224e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386434406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3386434406
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3877963289
Short name T503
Test name
Test status
Simulation time 2092573988 ps
CPU time 3.24 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:31 PM PDT 24
Peak memory 201572 kb
Host smart-ed3b623e-9fbf-4e63-8dec-30748b2c3727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877963289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.3877963289
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1021618494
Short name T439
Test name
Test status
Simulation time 2530616945 ps
CPU time 2.29 seconds
Started Jul 05 05:32:18 PM PDT 24
Finished Jul 05 05:32:21 PM PDT 24
Peak memory 201616 kb
Host smart-868721d4-8547-4f3c-b3dd-e355193be0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021618494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1021618494
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.1553173140
Short name T788
Test name
Test status
Simulation time 2123955745 ps
CPU time 2.04 seconds
Started Jul 05 05:32:21 PM PDT 24
Finished Jul 05 05:32:24 PM PDT 24
Peak memory 201532 kb
Host smart-37679826-3f42-43de-ab45-de51f352d7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553173140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.1553173140
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.2202237562
Short name T442
Test name
Test status
Simulation time 107782537511 ps
CPU time 135.54 seconds
Started Jul 05 05:32:27 PM PDT 24
Finished Jul 05 05:34:44 PM PDT 24
Peak memory 201924 kb
Host smart-3c5467c3-e029-45be-ae2b-7ac0bd88b7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202237562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.2202237562
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3649068990
Short name T42
Test name
Test status
Simulation time 80632743138 ps
CPU time 53.38 seconds
Started Jul 05 05:32:29 PM PDT 24
Finished Jul 05 05:33:23 PM PDT 24
Peak memory 210308 kb
Host smart-2bd5563a-5f4f-4fae-a1a7-8155b083d2c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649068990 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.3649068990
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1452596771
Short name T111
Test name
Test status
Simulation time 7144160221 ps
CPU time 2.77 seconds
Started Jul 05 05:32:19 PM PDT 24
Finished Jul 05 05:32:23 PM PDT 24
Peak memory 201648 kb
Host smart-0c862987-4a78-4904-b86c-4c2248fa1463
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452596771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.1452596771
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.3434496513
Short name T452
Test name
Test status
Simulation time 2017843185 ps
CPU time 3.42 seconds
Started Jul 05 05:32:27 PM PDT 24
Finished Jul 05 05:32:32 PM PDT 24
Peak memory 201556 kb
Host smart-55160af2-7826-44a7-ba56-1bfea830d019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434496513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.3434496513
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.565914923
Short name T755
Test name
Test status
Simulation time 3113775262 ps
CPU time 8.82 seconds
Started Jul 05 05:32:33 PM PDT 24
Finished Jul 05 05:32:43 PM PDT 24
Peak memory 201732 kb
Host smart-1da03f4d-89d3-4371-9691-1049e1bb15d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565914923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.565914923
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1878762258
Short name T768
Test name
Test status
Simulation time 33796696253 ps
CPU time 90.59 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:33:57 PM PDT 24
Peak memory 201920 kb
Host smart-29ff8119-19ad-46ca-b9ef-60692a40b504
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878762258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1878762258
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.975094554
Short name T453
Test name
Test status
Simulation time 4060369152 ps
CPU time 1.88 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:29 PM PDT 24
Peak memory 201640 kb
Host smart-3ede5a57-be7a-4c8c-9198-3a802590ae52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975094554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_ec_pwr_on_rst.975094554
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3400285563
Short name T170
Test name
Test status
Simulation time 4361261411 ps
CPU time 8.59 seconds
Started Jul 05 05:32:25 PM PDT 24
Finished Jul 05 05:32:34 PM PDT 24
Peak memory 201700 kb
Host smart-230fefff-c3f5-40b1-b342-c0980a2580ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400285563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3400285563
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4148856557
Short name T491
Test name
Test status
Simulation time 2636648913 ps
CPU time 1.5 seconds
Started Jul 05 05:32:29 PM PDT 24
Finished Jul 05 05:32:31 PM PDT 24
Peak memory 201636 kb
Host smart-221ff196-8b56-4fad-a08c-e69225291367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148856557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.4148856557
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2014756265
Short name T591
Test name
Test status
Simulation time 2538546020 ps
CPU time 1.17 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:28 PM PDT 24
Peak memory 201656 kb
Host smart-efbd8963-06c5-4a0f-9b9d-7c63aacbab01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014756265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2014756265
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.596290874
Short name T695
Test name
Test status
Simulation time 2128525269 ps
CPU time 0.93 seconds
Started Jul 05 05:32:25 PM PDT 24
Finished Jul 05 05:32:27 PM PDT 24
Peak memory 201580 kb
Host smart-d2e47c0d-8edd-4597-a95a-4817ccdb315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596290874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.596290874
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2447200771
Short name T630
Test name
Test status
Simulation time 2512486330 ps
CPU time 6.9 seconds
Started Jul 05 05:32:25 PM PDT 24
Finished Jul 05 05:32:33 PM PDT 24
Peak memory 201592 kb
Host smart-a8c8fe20-562b-4840-9537-b929ad674dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447200771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2447200771
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.2518967532
Short name T532
Test name
Test status
Simulation time 2114743923 ps
CPU time 5.25 seconds
Started Jul 05 05:32:27 PM PDT 24
Finished Jul 05 05:32:33 PM PDT 24
Peak memory 201536 kb
Host smart-716abb12-92f4-481a-ab96-f5175fe3e257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518967532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2518967532
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.996067913
Short name T139
Test name
Test status
Simulation time 3459698221 ps
CPU time 2.14 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:29 PM PDT 24
Peak memory 201640 kb
Host smart-2f12b076-a6fb-47d4-9fe4-d5958ba0d5ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996067913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_ultra_low_pwr.996067913
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.2812220289
Short name T246
Test name
Test status
Simulation time 2012885361 ps
CPU time 5.81 seconds
Started Jul 05 05:32:27 PM PDT 24
Finished Jul 05 05:32:34 PM PDT 24
Peak memory 201664 kb
Host smart-b3864a2e-3d1e-47a7-ab99-15539e0a9c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812220289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.2812220289
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1453124297
Short name T447
Test name
Test status
Simulation time 96520415209 ps
CPU time 22.35 seconds
Started Jul 05 05:32:34 PM PDT 24
Finished Jul 05 05:32:59 PM PDT 24
Peak memory 201748 kb
Host smart-bdd150c3-212e-4518-9d16-e4c89fb74d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453124297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
453124297
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.4267113773
Short name T331
Test name
Test status
Simulation time 38947809129 ps
CPU time 44.83 seconds
Started Jul 05 05:32:33 PM PDT 24
Finished Jul 05 05:33:19 PM PDT 24
Peak memory 201864 kb
Host smart-dcfe5114-d68c-42d8-a676-f082c5c5d57e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267113773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.4267113773
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3701137486
Short name T397
Test name
Test status
Simulation time 5393059598 ps
CPU time 4.11 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:31 PM PDT 24
Peak memory 201640 kb
Host smart-8443ddd3-6b37-4413-b056-c8ab3da62e4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701137486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.3701137486
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.2305086721
Short name T599
Test name
Test status
Simulation time 4448835306 ps
CPU time 3.23 seconds
Started Jul 05 05:32:27 PM PDT 24
Finished Jul 05 05:32:31 PM PDT 24
Peak memory 201628 kb
Host smart-a9bfc0f8-cdb6-431d-996a-05133841defe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305086721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.2305086721
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1826861996
Short name T561
Test name
Test status
Simulation time 2639430462 ps
CPU time 2.31 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:32:39 PM PDT 24
Peak memory 201664 kb
Host smart-f89ad991-4be1-4c76-97c6-c373cc4736a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826861996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.1826861996
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2123827249
Short name T641
Test name
Test status
Simulation time 2475868877 ps
CPU time 2.41 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:30 PM PDT 24
Peak memory 201664 kb
Host smart-14a3921a-8f17-408b-b503-d32616f85197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123827249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.2123827249
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2467126236
Short name T601
Test name
Test status
Simulation time 2127834911 ps
CPU time 1.77 seconds
Started Jul 05 05:32:29 PM PDT 24
Finished Jul 05 05:32:31 PM PDT 24
Peak memory 201508 kb
Host smart-64672a2c-9df0-446a-b349-1a2ad0cdee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467126236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2467126236
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.240600436
Short name T191
Test name
Test status
Simulation time 2530673845 ps
CPU time 2.48 seconds
Started Jul 05 05:32:29 PM PDT 24
Finished Jul 05 05:32:33 PM PDT 24
Peak memory 201580 kb
Host smart-65e40322-d516-4a13-9c5b-168810e45a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240600436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.240600436
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.678145699
Short name T620
Test name
Test status
Simulation time 2135229104 ps
CPU time 1.95 seconds
Started Jul 05 05:32:30 PM PDT 24
Finished Jul 05 05:32:32 PM PDT 24
Peak memory 201572 kb
Host smart-8473c0a0-e737-4cdb-ba82-5ab91924b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678145699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.678145699
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.488937738
Short name T665
Test name
Test status
Simulation time 11133425651 ps
CPU time 23.57 seconds
Started Jul 05 05:32:29 PM PDT 24
Finished Jul 05 05:32:54 PM PDT 24
Peak memory 201640 kb
Host smart-04ce45d1-c60e-4060-8dc6-68a41db33de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488937738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_st
ress_all.488937738
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.112042846
Short name T325
Test name
Test status
Simulation time 111346450290 ps
CPU time 146.64 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:35:06 PM PDT 24
Peak memory 210304 kb
Host smart-4f23e3d2-a917-4473-945c-738c245778e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112042846 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.112042846
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.426543953
Short name T648
Test name
Test status
Simulation time 2911692106 ps
CPU time 2.03 seconds
Started Jul 05 05:32:34 PM PDT 24
Finished Jul 05 05:32:37 PM PDT 24
Peak memory 201644 kb
Host smart-266e8504-0e6b-4a26-b3f2-20046ea3e01b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426543953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ultra_low_pwr.426543953
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.2868815902
Short name T525
Test name
Test status
Simulation time 2036795572 ps
CPU time 2.04 seconds
Started Jul 05 05:32:32 PM PDT 24
Finished Jul 05 05:32:35 PM PDT 24
Peak memory 201664 kb
Host smart-62df9d50-3032-4b37-b438-6755e8474fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868815902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.2868815902
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2469918657
Short name T290
Test name
Test status
Simulation time 3776596006 ps
CPU time 10.68 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:38 PM PDT 24
Peak memory 201704 kb
Host smart-efe061ca-4a25-46ea-a772-773b97d1638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469918657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.2
469918657
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1630935950
Short name T129
Test name
Test status
Simulation time 51709071166 ps
CPU time 16.61 seconds
Started Jul 05 05:32:25 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 202112 kb
Host smart-e73e8f83-9f07-497a-9904-a14ae61dcd18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630935950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.1630935950
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1498899486
Short name T241
Test name
Test status
Simulation time 75143631123 ps
CPU time 181.59 seconds
Started Jul 05 05:32:32 PM PDT 24
Finished Jul 05 05:35:34 PM PDT 24
Peak memory 201872 kb
Host smart-aabc8817-42eb-43c9-96a4-0b0d706638ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498899486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.1498899486
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.874640648
Short name T385
Test name
Test status
Simulation time 2694294849 ps
CPU time 7.35 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:32:44 PM PDT 24
Peak memory 201636 kb
Host smart-5db734bb-8c83-4617-818d-a3453ac4a6d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874640648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ec_pwr_on_rst.874640648
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.4000131145
Short name T7
Test name
Test status
Simulation time 3838893201 ps
CPU time 2.65 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:29 PM PDT 24
Peak memory 201612 kb
Host smart-8220f0e3-173d-4366-ab12-9995bf3bb925
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000131145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.4000131145
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.634487357
Short name T604
Test name
Test status
Simulation time 2629158888 ps
CPU time 2.08 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:29 PM PDT 24
Peak memory 201660 kb
Host smart-8605c7ed-32d2-4bca-bc67-251281c0f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634487357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.634487357
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1138931347
Short name T69
Test name
Test status
Simulation time 2463403159 ps
CPU time 3.97 seconds
Started Jul 05 05:32:28 PM PDT 24
Finished Jul 05 05:32:32 PM PDT 24
Peak memory 201660 kb
Host smart-7392e49c-637d-43b7-ab47-d6b17a550592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138931347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1138931347
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2484618439
Short name T210
Test name
Test status
Simulation time 2062766932 ps
CPU time 1.7 seconds
Started Jul 05 05:32:27 PM PDT 24
Finished Jul 05 05:32:30 PM PDT 24
Peak memory 201496 kb
Host smart-c9eeda79-a015-43e2-9037-de3eb7a8cbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484618439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2484618439
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.495610565
Short name T535
Test name
Test status
Simulation time 2523540733 ps
CPU time 2.44 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201640 kb
Host smart-f213b975-5789-4bf9-93a5-20df66143aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495610565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.495610565
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.2894401400
Short name T657
Test name
Test status
Simulation time 2127956241 ps
CPU time 1.95 seconds
Started Jul 05 05:32:33 PM PDT 24
Finished Jul 05 05:32:36 PM PDT 24
Peak memory 201528 kb
Host smart-7a08bdbf-fae6-4ea3-bcbb-a0dc3a83c7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894401400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2894401400
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.438001657
Short name T582
Test name
Test status
Simulation time 10408109625 ps
CPU time 7.86 seconds
Started Jul 05 05:32:32 PM PDT 24
Finished Jul 05 05:32:41 PM PDT 24
Peak memory 201664 kb
Host smart-9c514127-db3e-4ea5-b0b4-c21a6ffb87f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438001657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_st
ress_all.438001657
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.345411657
Short name T300
Test name
Test status
Simulation time 41216033130 ps
CPU time 110.68 seconds
Started Jul 05 05:32:32 PM PDT 24
Finished Jul 05 05:34:24 PM PDT 24
Peak memory 211760 kb
Host smart-d1961d99-755a-4203-8e8c-21ae3001ad61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345411657 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.345411657
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1653712294
Short name T774
Test name
Test status
Simulation time 3522031229 ps
CPU time 5.86 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:32:46 PM PDT 24
Peak memory 201652 kb
Host smart-db431e31-0afe-4f3e-bc5b-3cdc72cff7d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653712294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.1653712294
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.2567896211
Short name T158
Test name
Test status
Simulation time 2015508061 ps
CPU time 3.29 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201664 kb
Host smart-ce7bf701-5538-46d1-a1d0-5468a3181195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567896211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.2567896211
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3439473393
Short name T683
Test name
Test status
Simulation time 2912242682 ps
CPU time 2.51 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201652 kb
Host smart-d41aea98-7d6e-4429-ab1e-fdde885089fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439473393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3
439473393
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3337863033
Short name T706
Test name
Test status
Simulation time 113706086013 ps
CPU time 269.05 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:37:08 PM PDT 24
Peak memory 201864 kb
Host smart-54736d9d-3a0c-4872-8694-6a504bbeb472
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337863033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.3337863033
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.797800513
Short name T703
Test name
Test status
Simulation time 46048858812 ps
CPU time 126.27 seconds
Started Jul 05 05:32:38 PM PDT 24
Finished Jul 05 05:34:47 PM PDT 24
Peak memory 201868 kb
Host smart-8bdfb0b2-c76c-47e8-b638-957f72fa148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797800513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_wi
th_pre_cond.797800513
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3734850177
Short name T402
Test name
Test status
Simulation time 3925765788 ps
CPU time 2.91 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201648 kb
Host smart-b9c03204-d3a5-4ff9-a462-c750d43c5ddf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734850177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3734850177
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.53058131
Short name T34
Test name
Test status
Simulation time 886325676160 ps
CPU time 209.14 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:36:08 PM PDT 24
Peak memory 201656 kb
Host smart-23f694d9-2f7b-416b-9be0-90448b930aa4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53058131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl
_edge_detect.53058131
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2687934774
Short name T629
Test name
Test status
Simulation time 2609396149 ps
CPU time 7.18 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:32:45 PM PDT 24
Peak memory 201660 kb
Host smart-7e79a2ce-03bf-4978-80d6-b157b819cbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687934774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.2687934774
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.858580064
Short name T24
Test name
Test status
Simulation time 2464014154 ps
CPU time 3.17 seconds
Started Jul 05 05:32:32 PM PDT 24
Finished Jul 05 05:32:36 PM PDT 24
Peak memory 201608 kb
Host smart-831eee59-a8ba-410a-850f-5844c608c866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858580064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.858580064
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4250547878
Short name T637
Test name
Test status
Simulation time 2062400469 ps
CPU time 1.73 seconds
Started Jul 05 05:32:26 PM PDT 24
Finished Jul 05 05:32:29 PM PDT 24
Peak memory 201476 kb
Host smart-3d8d2cc5-44b7-49f6-8291-dbf203e87892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250547878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.4250547878
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4133844015
Short name T747
Test name
Test status
Simulation time 2510183137 ps
CPU time 7.32 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:32:45 PM PDT 24
Peak memory 201660 kb
Host smart-246eda1a-6de1-49d1-9a20-e5efabfb32bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133844015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.4133844015
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.2659950951
Short name T563
Test name
Test status
Simulation time 2125606028 ps
CPU time 2.02 seconds
Started Jul 05 05:32:27 PM PDT 24
Finished Jul 05 05:32:30 PM PDT 24
Peak memory 201488 kb
Host smart-79583640-f598-4c53-90f5-aca0587e427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659950951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2659950951
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.585973433
Short name T410
Test name
Test status
Simulation time 6598454642 ps
CPU time 3.8 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201576 kb
Host smart-d4d2972a-9995-4a76-b7ab-1a5db36dd558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585973433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_st
ress_all.585973433
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.777308035
Short name T155
Test name
Test status
Simulation time 58228098096 ps
CPU time 33.01 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:33:11 PM PDT 24
Peak memory 210300 kb
Host smart-e703f49c-0740-4fd6-ac35-0e2773909e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777308035 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.777308035
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3640753770
Short name T441
Test name
Test status
Simulation time 2647486150 ps
CPU time 6.23 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:46 PM PDT 24
Peak memory 201632 kb
Host smart-ef179a6b-1179-4887-9e14-fb728d0317b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640753770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.3640753770
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3056498845
Short name T465
Test name
Test status
Simulation time 2011349404 ps
CPU time 5.75 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:45 PM PDT 24
Peak memory 201644 kb
Host smart-9499a561-fdbf-4b26-bc2d-a2c70e6a4114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056498845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3056498845
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.641281980
Short name T430
Test name
Test status
Simulation time 3611907451 ps
CPU time 8.35 seconds
Started Jul 05 05:32:38 PM PDT 24
Finished Jul 05 05:32:49 PM PDT 24
Peak memory 201728 kb
Host smart-eda0ac62-3cf7-4ea0-86da-3a2b1c5e36df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641281980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.641281980
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.1372009581
Short name T338
Test name
Test status
Simulation time 62617226315 ps
CPU time 23.7 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:33:03 PM PDT 24
Peak memory 201920 kb
Host smart-783ebcb6-15b2-46f8-a9fa-95fcc935c1a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372009581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.1372009581
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1535774680
Short name T122
Test name
Test status
Simulation time 28098572888 ps
CPU time 28.67 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:33:09 PM PDT 24
Peak memory 201840 kb
Host smart-5b873e7c-2116-44b7-b739-79c3f975f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535774680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.1535774680
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.119829944
Short name T490
Test name
Test status
Simulation time 2870797023 ps
CPU time 7.9 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:32:47 PM PDT 24
Peak memory 201652 kb
Host smart-f3ff0690-8fbe-4163-b8ea-70914485d390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119829944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_ec_pwr_on_rst.119829944
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.157224957
Short name T651
Test name
Test status
Simulation time 2760787477 ps
CPU time 3.6 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201652 kb
Host smart-49f494a4-8108-49a1-836e-37b2a0dd516f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157224957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctr
l_edge_detect.157224957
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1705777365
Short name T380
Test name
Test status
Simulation time 2616821163 ps
CPU time 4.18 seconds
Started Jul 05 05:32:34 PM PDT 24
Finished Jul 05 05:32:40 PM PDT 24
Peak memory 201668 kb
Host smart-d0215655-741c-47c6-b56e-9f0a27e40547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705777365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1705777365
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3010054431
Short name T483
Test name
Test status
Simulation time 2493312275 ps
CPU time 2.3 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:41 PM PDT 24
Peak memory 201588 kb
Host smart-e2d42c8e-1097-42cd-9a74-e845390521e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010054431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3010054431
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3413531583
Short name T712
Test name
Test status
Simulation time 2014795687 ps
CPU time 5.95 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:32:46 PM PDT 24
Peak memory 201524 kb
Host smart-5bf48df9-b513-493b-aec6-2f13e23c4fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413531583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.3413531583
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2571949747
Short name T594
Test name
Test status
Simulation time 2507843884 ps
CPU time 6.96 seconds
Started Jul 05 05:32:34 PM PDT 24
Finished Jul 05 05:32:43 PM PDT 24
Peak memory 201644 kb
Host smart-84ce81cc-d5a8-4259-9f75-436112e26061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571949747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.2571949747
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.518763354
Short name T477
Test name
Test status
Simulation time 2113557071 ps
CPU time 3.34 seconds
Started Jul 05 05:32:34 PM PDT 24
Finished Jul 05 05:32:39 PM PDT 24
Peak memory 201576 kb
Host smart-8595cc56-eb79-45cb-bb96-f621ea162347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518763354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.518763354
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.3122676878
Short name T154
Test name
Test status
Simulation time 983297111013 ps
CPU time 49.39 seconds
Started Jul 05 05:32:35 PM PDT 24
Finished Jul 05 05:33:28 PM PDT 24
Peak memory 201576 kb
Host smart-3bf019ba-394d-456a-b8bd-2883af1987c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122676878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.3122676878
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1853080766
Short name T9
Test name
Test status
Simulation time 4768496270 ps
CPU time 2.04 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201644 kb
Host smart-c0a42591-5b58-4bff-96f7-20a6788e959a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853080766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1853080766
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.844174082
Short name T716
Test name
Test status
Simulation time 2013420407 ps
CPU time 6.02 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:32:50 PM PDT 24
Peak memory 201660 kb
Host smart-efb38cbf-abae-4432-a3d0-a2f500be3ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844174082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_tes
t.844174082
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.191963779
Short name T112
Test name
Test status
Simulation time 3853236870 ps
CPU time 10.11 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:32:50 PM PDT 24
Peak memory 201728 kb
Host smart-225ff306-ac76-40cc-8b11-3996ae9e0ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191963779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.191963779
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.4284512271
Short name T128
Test name
Test status
Simulation time 149343517280 ps
CPU time 92.24 seconds
Started Jul 05 05:32:34 PM PDT 24
Finished Jul 05 05:34:09 PM PDT 24
Peak memory 201892 kb
Host smart-11cb7180-bcfa-4693-872d-0ca9564b37d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284512271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.4284512271
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2252199081
Short name T5
Test name
Test status
Simulation time 3407204470 ps
CPU time 9.51 seconds
Started Jul 05 05:32:34 PM PDT 24
Finished Jul 05 05:32:46 PM PDT 24
Peak memory 201564 kb
Host smart-880356b1-09b7-42fb-958a-cee7fc55a5a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252199081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.2252199081
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.334177652
Short name T166
Test name
Test status
Simulation time 3466514664 ps
CPU time 1.29 seconds
Started Jul 05 05:32:39 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201616 kb
Host smart-da987244-d402-43f2-8b8b-3909f3cd8b48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334177652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctr
l_edge_detect.334177652
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3164337209
Short name T484
Test name
Test status
Simulation time 2614769954 ps
CPU time 3.93 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:32:44 PM PDT 24
Peak memory 201660 kb
Host smart-391e3379-1de4-4761-84c1-5a44379dafb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164337209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.3164337209
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.184353026
Short name T72
Test name
Test status
Simulation time 2474193602 ps
CPU time 1.95 seconds
Started Jul 05 05:32:37 PM PDT 24
Finished Jul 05 05:32:42 PM PDT 24
Peak memory 201640 kb
Host smart-8ff400df-47e9-4b54-8f61-8d14c3d8f28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184353026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.184353026
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1982126076
Short name T245
Test name
Test status
Simulation time 2079083846 ps
CPU time 6.07 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:45 PM PDT 24
Peak memory 201580 kb
Host smart-deae3fd3-9be6-4056-a0cc-b5cee3ea038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982126076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1982126076
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1050369918
Short name T378
Test name
Test status
Simulation time 2507985257 ps
CPU time 7.12 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:46 PM PDT 24
Peak memory 201640 kb
Host smart-7eed982c-794f-48b6-975a-ceb004d83a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050369918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1050369918
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.3842118439
Short name T611
Test name
Test status
Simulation time 2135937439 ps
CPU time 1.99 seconds
Started Jul 05 05:32:36 PM PDT 24
Finished Jul 05 05:32:41 PM PDT 24
Peak memory 201588 kb
Host smart-7805ada2-55b4-4191-9997-0653ba47a496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842118439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3842118439
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.4225677107
Short name T560
Test name
Test status
Simulation time 6470583138 ps
CPU time 2.22 seconds
Started Jul 05 05:32:44 PM PDT 24
Finished Jul 05 05:32:48 PM PDT 24
Peak memory 201568 kb
Host smart-61f23d28-103b-409a-8b7f-74014ae88345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225677107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.4225677107
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1339906454
Short name T62
Test name
Test status
Simulation time 14382153932 ps
CPU time 3.23 seconds
Started Jul 05 05:32:38 PM PDT 24
Finished Jul 05 05:32:44 PM PDT 24
Peak memory 201696 kb
Host smart-0aa2b1ed-b9fd-42e2-b32a-0177031081dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339906454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.1339906454
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1301510866
Short name T411
Test name
Test status
Simulation time 2042332493 ps
CPU time 1.46 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 201592 kb
Host smart-9e9c08ef-257a-451c-9160-5f18de6860a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301510866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1301510866
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2182093163
Short name T625
Test name
Test status
Simulation time 3661429534 ps
CPU time 1.43 seconds
Started Jul 05 05:30:38 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201752 kb
Host smart-4c941929-3a82-4300-8149-9a0c5d0ffbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182093163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2182093163
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.22590699
Short name T281
Test name
Test status
Simulation time 50629319488 ps
CPU time 135.55 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:32:53 PM PDT 24
Peak memory 201940 kb
Host smart-cf6a8de3-0e21-4a38-a07f-a234fbb3ad81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22590699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl
_combo_detect.22590699
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3600827435
Short name T370
Test name
Test status
Simulation time 67277925256 ps
CPU time 44.01 seconds
Started Jul 05 05:30:34 PM PDT 24
Finished Jul 05 05:31:19 PM PDT 24
Peak memory 201892 kb
Host smart-2e01249e-6fa6-4d26-940f-dc5a7f8c0a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600827435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.3600827435
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2154698891
Short name T597
Test name
Test status
Simulation time 4892669183 ps
CPU time 7.47 seconds
Started Jul 05 05:30:38 PM PDT 24
Finished Jul 05 05:30:47 PM PDT 24
Peak memory 201644 kb
Host smart-ee3c3752-5ac6-4561-9708-1b10da1f8cb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154698891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.2154698891
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3453752231
Short name T1
Test name
Test status
Simulation time 946895093923 ps
CPU time 169.62 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:33:25 PM PDT 24
Peak memory 201656 kb
Host smart-d54b344c-c55f-48b7-91a2-a6a658ac58cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453752231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3453752231
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.523117451
Short name T379
Test name
Test status
Simulation time 2627233254 ps
CPU time 2.28 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 201600 kb
Host smart-1a0c90b5-f046-4ff6-a1e7-ae66b229ba39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523117451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.523117451
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1281388418
Short name T662
Test name
Test status
Simulation time 2471581355 ps
CPU time 4.54 seconds
Started Jul 05 05:30:39 PM PDT 24
Finished Jul 05 05:30:44 PM PDT 24
Peak memory 201596 kb
Host smart-19148f29-2402-43e7-99bf-a2e9b4d28aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281388418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1281388418
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2469880444
Short name T435
Test name
Test status
Simulation time 2290037770 ps
CPU time 1.2 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 201612 kb
Host smart-e418f9e4-3e7e-4aa2-b797-4edc411d0562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469880444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2469880444
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.4066504132
Short name T377
Test name
Test status
Simulation time 2507727975 ps
CPU time 7.1 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:30:43 PM PDT 24
Peak memory 201624 kb
Host smart-96b2fea8-d2a6-4aaf-90f3-7b76f4c64eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066504132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.4066504132
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.2706529786
Short name T469
Test name
Test status
Simulation time 2107912073 ps
CPU time 5.82 seconds
Started Jul 05 05:30:34 PM PDT 24
Finished Jul 05 05:30:41 PM PDT 24
Peak memory 201588 kb
Host smart-c0eb1335-8547-404a-a594-6da1116eaa67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706529786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.2706529786
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.1699310390
Short name T50
Test name
Test status
Simulation time 13230505805 ps
CPU time 8.61 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:53 PM PDT 24
Peak memory 201728 kb
Host smart-7cbc2068-b57a-4125-822c-e3d66608f680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699310390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.1699310390
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1889364588
Short name T299
Test name
Test status
Simulation time 48710002282 ps
CPU time 116.98 seconds
Started Jul 05 05:30:40 PM PDT 24
Finished Jul 05 05:32:38 PM PDT 24
Peak memory 210292 kb
Host smart-06945892-4679-4a81-a8cb-e849d5f34c54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889364588 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.1889364588
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2952733144
Short name T472
Test name
Test status
Simulation time 5478917961 ps
CPU time 5.88 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:43 PM PDT 24
Peak memory 201640 kb
Host smart-b039536d-172f-4857-a2ae-e89636c83b10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952733144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.2952733144
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1301427574
Short name T148
Test name
Test status
Simulation time 81141375728 ps
CPU time 14.28 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:32:59 PM PDT 24
Peak memory 201884 kb
Host smart-0f72e4f5-82c1-4b9c-a703-500c90fc1f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301427574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1301427574
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3594889558
Short name T271
Test name
Test status
Simulation time 23082152805 ps
CPU time 55.87 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:33:40 PM PDT 24
Peak memory 201832 kb
Host smart-c37e9e05-4ccb-4764-89b5-4132590086ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594889558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.3594889558
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3533213512
Short name T644
Test name
Test status
Simulation time 81746568444 ps
CPU time 206.93 seconds
Started Jul 05 05:32:41 PM PDT 24
Finished Jul 05 05:36:09 PM PDT 24
Peak memory 201760 kb
Host smart-b3e1e208-6efe-441d-87d6-21d39aa04f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533213512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.3533213512
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.239258007
Short name T722
Test name
Test status
Simulation time 26354835611 ps
CPU time 19.02 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:33:06 PM PDT 24
Peak memory 201908 kb
Host smart-270c3bfb-c038-4d5b-a722-54e7763e02e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239258007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_wi
th_pre_cond.239258007
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3450427084
Short name T708
Test name
Test status
Simulation time 26852371207 ps
CPU time 21.77 seconds
Started Jul 05 05:32:47 PM PDT 24
Finished Jul 05 05:33:10 PM PDT 24
Peak memory 201916 kb
Host smart-009acdbb-371c-449d-985e-985d458f9d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450427084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.3450427084
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4255554608
Short name T707
Test name
Test status
Simulation time 214658341460 ps
CPU time 549.66 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:41:54 PM PDT 24
Peak memory 201916 kb
Host smart-4f001ec0-dc7f-418f-b76d-385c5653a735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255554608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.4255554608
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2896968947
Short name T780
Test name
Test status
Simulation time 63102070576 ps
CPU time 36.04 seconds
Started Jul 05 05:32:46 PM PDT 24
Finished Jul 05 05:33:24 PM PDT 24
Peak memory 201936 kb
Host smart-219e3774-c176-4e91-b5f3-677687c8e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896968947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.2896968947
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.1075307987
Short name T718
Test name
Test status
Simulation time 2037013592 ps
CPU time 1.82 seconds
Started Jul 05 05:30:38 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201684 kb
Host smart-e3d3ac89-16a8-495b-8faf-68db4444b3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075307987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.1075307987
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2491830604
Short name T425
Test name
Test status
Simulation time 3015193946 ps
CPU time 2.4 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:47 PM PDT 24
Peak memory 201760 kb
Host smart-7b460ea1-5521-436f-a8e9-6833dc4aa3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491830604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.2491830604
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1614795785
Short name T783
Test name
Test status
Simulation time 106031446646 ps
CPU time 71.06 seconds
Started Jul 05 05:30:39 PM PDT 24
Finished Jul 05 05:31:51 PM PDT 24
Peak memory 201852 kb
Host smart-fd09266d-18c4-44ad-ac75-bce41e648c12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614795785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.1614795785
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.430382573
Short name T103
Test name
Test status
Simulation time 115840889241 ps
CPU time 28.11 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:31:13 PM PDT 24
Peak memory 201932 kb
Host smart-6f5230c2-b0c9-4af7-93c2-2d6cc38ae439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430382573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wit
h_pre_cond.430382573
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2472732356
Short name T685
Test name
Test status
Simulation time 3803226738 ps
CPU time 1.7 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 201636 kb
Host smart-829bc4a7-d325-45a6-bb56-dbaaf93868e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472732356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2472732356
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1232326975
Short name T182
Test name
Test status
Simulation time 3698450410 ps
CPU time 1.18 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:30:37 PM PDT 24
Peak memory 201688 kb
Host smart-d012cc3c-49ad-4ced-a68a-e9da8a8bd4bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232326975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1232326975
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1084867774
Short name T731
Test name
Test status
Simulation time 2618556526 ps
CPU time 4.27 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:41 PM PDT 24
Peak memory 201596 kb
Host smart-d63cfd98-46a6-4a2d-b067-5112e3969953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084867774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1084867774
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.4240998167
Short name T478
Test name
Test status
Simulation time 2489291862 ps
CPU time 1.6 seconds
Started Jul 05 05:30:38 PM PDT 24
Finished Jul 05 05:30:41 PM PDT 24
Peak memory 201664 kb
Host smart-2ded1666-c8d8-4eea-a57b-f63f57e26cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240998167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.4240998167
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.395546094
Short name T431
Test name
Test status
Simulation time 2070728200 ps
CPU time 6.16 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:44 PM PDT 24
Peak memory 201512 kb
Host smart-b0e4a3f2-d602-4f8b-960d-8b0d9812933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395546094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.395546094
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.845866696
Short name T528
Test name
Test status
Simulation time 2515058743 ps
CPU time 4.04 seconds
Started Jul 05 05:30:35 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201640 kb
Host smart-b2244aff-036f-4ddd-a1c5-007ec8c499ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845866696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.845866696
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.2122327017
Short name T580
Test name
Test status
Simulation time 2133802078 ps
CPU time 1.95 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:47 PM PDT 24
Peak memory 201500 kb
Host smart-be4cf9c2-ad70-4a4a-88fa-5953395d5bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122327017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.2122327017
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.4273624064
Short name T6
Test name
Test status
Simulation time 16907183860 ps
CPU time 26.68 seconds
Started Jul 05 05:30:40 PM PDT 24
Finished Jul 05 05:31:07 PM PDT 24
Peak memory 201664 kb
Host smart-b22f3d33-422f-4276-91db-06a2c9966a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273624064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.4273624064
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2990235143
Short name T743
Test name
Test status
Simulation time 64805093619 ps
CPU time 170.98 seconds
Started Jul 05 05:32:47 PM PDT 24
Finished Jul 05 05:35:39 PM PDT 24
Peak memory 201840 kb
Host smart-97d3f826-8c31-492e-8d94-d186d0e063fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990235143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.2990235143
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1802186696
Short name T626
Test name
Test status
Simulation time 32995079554 ps
CPU time 43.81 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:33:35 PM PDT 24
Peak memory 201944 kb
Host smart-c03fbf8d-3bd8-4cf7-ae89-f0f0e99ef25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802186696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1802186696
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3065382936
Short name T352
Test name
Test status
Simulation time 173789055283 ps
CPU time 442.44 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:40:09 PM PDT 24
Peak memory 201844 kb
Host smart-a6022298-0c06-407d-9efc-44fbe1d570c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065382936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.3065382936
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1210851700
Short name T758
Test name
Test status
Simulation time 141061673124 ps
CPU time 88.1 seconds
Started Jul 05 05:32:46 PM PDT 24
Finished Jul 05 05:34:16 PM PDT 24
Peak memory 201868 kb
Host smart-ce8d1f87-aa6d-4820-be5b-6ebec2a963fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210851700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.1210851700
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2137048151
Short name T359
Test name
Test status
Simulation time 51354246412 ps
CPU time 68.96 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:33:56 PM PDT 24
Peak memory 201852 kb
Host smart-c6edad5c-16c1-4318-84ff-dcba9fdaf3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137048151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.2137048151
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.317532420
Short name T540
Test name
Test status
Simulation time 28342918424 ps
CPU time 23.24 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:33:10 PM PDT 24
Peak memory 201916 kb
Host smart-e8f23b59-4c58-4423-b81d-f8d2c655fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317532420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_wi
th_pre_cond.317532420
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3386749170
Short name T239
Test name
Test status
Simulation time 76093458830 ps
CPU time 54.49 seconds
Started Jul 05 05:32:49 PM PDT 24
Finished Jul 05 05:33:44 PM PDT 24
Peak memory 201932 kb
Host smart-d0ef458c-09a8-4b98-8888-56628187d1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386749170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.3386749170
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2415849665
Short name T348
Test name
Test status
Simulation time 184129223108 ps
CPU time 122.21 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:34:49 PM PDT 24
Peak memory 201932 kb
Host smart-ca391511-40b1-400e-80e4-ed3c93c90cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415849665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.2415849665
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3397297885
Short name T186
Test name
Test status
Simulation time 113010021512 ps
CPU time 80.22 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:34:04 PM PDT 24
Peak memory 201824 kb
Host smart-e3323a77-eda0-45f7-b957-3347ddb0a073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397297885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.3397297885
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.3798371600
Short name T727
Test name
Test status
Simulation time 2027677704 ps
CPU time 2.84 seconds
Started Jul 05 05:30:42 PM PDT 24
Finished Jul 05 05:30:45 PM PDT 24
Peak memory 201632 kb
Host smart-6f35bbe8-bbd5-4b85-9101-15afa1b1121d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798371600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.3798371600
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4121737902
Short name T499
Test name
Test status
Simulation time 299440760950 ps
CPU time 406.47 seconds
Started Jul 05 05:30:49 PM PDT 24
Finished Jul 05 05:37:36 PM PDT 24
Peak memory 201580 kb
Host smart-b11cbe06-751f-40d9-8b62-9bba898aec11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121737902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.4121737902
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.2932761085
Short name T49
Test name
Test status
Simulation time 136492949601 ps
CPU time 96.58 seconds
Started Jul 05 05:30:41 PM PDT 24
Finished Jul 05 05:32:18 PM PDT 24
Peak memory 201864 kb
Host smart-99b87e2c-7904-4279-8732-b86149e73c14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932761085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.2932761085
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2869931199
Short name T349
Test name
Test status
Simulation time 106726873080 ps
CPU time 24.2 seconds
Started Jul 05 05:38:45 PM PDT 24
Finished Jul 05 05:39:10 PM PDT 24
Peak memory 201864 kb
Host smart-8a776c68-405d-4aaa-bf48-cb72ab99228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869931199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.2869931199
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1454952623
Short name T197
Test name
Test status
Simulation time 2527204200 ps
CPU time 2.2 seconds
Started Jul 05 05:30:42 PM PDT 24
Finished Jul 05 05:30:45 PM PDT 24
Peak memory 201524 kb
Host smart-b8e22bbd-f403-4971-81b3-b111d4bc4c3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454952623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.1454952623
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1072394410
Short name T383
Test name
Test status
Simulation time 2637374610 ps
CPU time 2.4 seconds
Started Jul 05 05:30:37 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201636 kb
Host smart-9a348568-dd6c-4d7c-aa28-15fe2227c953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072394410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.1072394410
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2209737466
Short name T236
Test name
Test status
Simulation time 2481679987 ps
CPU time 3.74 seconds
Started Jul 05 05:30:41 PM PDT 24
Finished Jul 05 05:30:45 PM PDT 24
Peak memory 201644 kb
Host smart-cfdfe1ab-c280-4994-80c7-7812c8c2609c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209737466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.2209737466
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.623874232
Short name T771
Test name
Test status
Simulation time 2170474214 ps
CPU time 5.61 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:43 PM PDT 24
Peak memory 201584 kb
Host smart-61e4aed6-a28e-44bd-9cac-db3ff625740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623874232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.623874232
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.590506991
Short name T759
Test name
Test status
Simulation time 2522365006 ps
CPU time 4.05 seconds
Started Jul 05 05:30:34 PM PDT 24
Finished Jul 05 05:30:39 PM PDT 24
Peak memory 201648 kb
Host smart-f93e8211-074f-4636-a099-bc2519814b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590506991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.590506991
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.3570167968
Short name T417
Test name
Test status
Simulation time 2126266442 ps
CPU time 2.14 seconds
Started Jul 05 05:30:36 PM PDT 24
Finished Jul 05 05:30:40 PM PDT 24
Peak memory 201564 kb
Host smart-498c81ba-4075-4157-a1fd-a5fba1b600d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570167968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.3570167968
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.1031122242
Short name T113
Test name
Test status
Simulation time 249111563396 ps
CPU time 626.88 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:41:11 PM PDT 24
Peak memory 202024 kb
Host smart-e71ef74c-f0ef-468d-a608-d1a4e299bbb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031122242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.1031122242
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2831626141
Short name T38
Test name
Test status
Simulation time 32002034230 ps
CPU time 49.58 seconds
Started Jul 05 05:30:42 PM PDT 24
Finished Jul 05 05:31:33 PM PDT 24
Peak memory 210200 kb
Host smart-8a172476-97f1-496a-9343-3dc143addadd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831626141 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.2831626141
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3343174442
Short name T740
Test name
Test status
Simulation time 3802705314 ps
CPU time 3.59 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201644 kb
Host smart-4f6dc361-f556-443c-9771-e39134a1b16a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343174442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.3343174442
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2321879433
Short name T250
Test name
Test status
Simulation time 38291927092 ps
CPU time 89.92 seconds
Started Jul 05 05:32:44 PM PDT 24
Finished Jul 05 05:34:16 PM PDT 24
Peak memory 201836 kb
Host smart-7097943d-681d-4e9e-88a0-5d812dc5ba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321879433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2321879433
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1378039747
Short name T618
Test name
Test status
Simulation time 25835593830 ps
CPU time 70.73 seconds
Started Jul 05 05:32:47 PM PDT 24
Finished Jul 05 05:33:59 PM PDT 24
Peak memory 201916 kb
Host smart-d49c9b78-8201-4e13-a23d-a1bfa02b5c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378039747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1378039747
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2294101715
Short name T571
Test name
Test status
Simulation time 25336450188 ps
CPU time 42.39 seconds
Started Jul 05 05:32:48 PM PDT 24
Finished Jul 05 05:33:31 PM PDT 24
Peak memory 201916 kb
Host smart-3ba32b19-4208-4786-948f-53f6646ed847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294101715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2294101715
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1140971141
Short name T589
Test name
Test status
Simulation time 33218798777 ps
CPU time 41.54 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:33:28 PM PDT 24
Peak memory 201944 kb
Host smart-ca2b6557-339f-4c46-9676-0ab44ef4cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140971141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.1140971141
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3842630864
Short name T529
Test name
Test status
Simulation time 25583270676 ps
CPU time 63.66 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:33:48 PM PDT 24
Peak memory 201908 kb
Host smart-2f334fb5-3014-42ee-8a99-12f871768a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842630864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.3842630864
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.53866101
Short name T80
Test name
Test status
Simulation time 24599348274 ps
CPU time 16.74 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:33:03 PM PDT 24
Peak memory 201912 kb
Host smart-8638b019-59c0-42dc-b347-1b905136d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53866101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_wit
h_pre_cond.53866101
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.273076696
Short name T636
Test name
Test status
Simulation time 57614017555 ps
CPU time 38.38 seconds
Started Jul 05 05:32:42 PM PDT 24
Finished Jul 05 05:33:21 PM PDT 24
Peak memory 201908 kb
Host smart-9ee9d74e-04ab-438c-9549-6458ab7f0fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273076696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_wi
th_pre_cond.273076696
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3323241629
Short name T275
Test name
Test status
Simulation time 74578036388 ps
CPU time 182.63 seconds
Started Jul 05 05:32:47 PM PDT 24
Finished Jul 05 05:35:51 PM PDT 24
Peak memory 201780 kb
Host smart-c4f9be25-0604-40ab-864e-03cb460348ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323241629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.3323241629
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4072618507
Short name T48
Test name
Test status
Simulation time 54035139367 ps
CPU time 141.44 seconds
Started Jul 05 05:32:44 PM PDT 24
Finished Jul 05 05:35:07 PM PDT 24
Peak memory 201888 kb
Host smart-fca61d00-70bc-4368-b977-8c8d2e47ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072618507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.4072618507
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.1906616066
Short name T156
Test name
Test status
Simulation time 2030890784 ps
CPU time 1.77 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201668 kb
Host smart-4d467611-1b78-422e-8a6f-a17978fe9777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906616066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.1906616066
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3764045256
Short name T588
Test name
Test status
Simulation time 3427368642 ps
CPU time 5.31 seconds
Started Jul 05 05:30:42 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201688 kb
Host smart-5f98a41e-28ba-4fec-ae9f-cc173fe9a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764045256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.3764045256
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.2214108012
Short name T330
Test name
Test status
Simulation time 127285969597 ps
CPU time 75.92 seconds
Started Jul 05 05:30:46 PM PDT 24
Finished Jul 05 05:32:03 PM PDT 24
Peak memory 201396 kb
Host smart-6ea27bdc-a499-446b-8e69-096e3725664e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214108012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.2214108012
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1801780872
Short name T157
Test name
Test status
Simulation time 5403705796 ps
CPU time 7.68 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:51 PM PDT 24
Peak memory 201644 kb
Host smart-ab126475-7113-4906-ad43-7154f45cf626
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801780872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1801780872
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.35092956
Short name T770
Test name
Test status
Simulation time 3122624603 ps
CPU time 9.08 seconds
Started Jul 05 05:30:44 PM PDT 24
Finished Jul 05 05:30:55 PM PDT 24
Peak memory 201644 kb
Host smart-b1b26041-ca75-46bb-aa45-c8f00a35db0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35092956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_
edge_detect.35092956
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.4048866842
Short name T749
Test name
Test status
Simulation time 2644771212 ps
CPU time 2.14 seconds
Started Jul 05 05:30:44 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201664 kb
Host smart-b370db11-8b41-4426-a36d-f49413c68ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048866842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.4048866842
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1147236417
Short name T208
Test name
Test status
Simulation time 2462668495 ps
CPU time 7.33 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:52 PM PDT 24
Peak memory 201644 kb
Host smart-df475014-1db2-4a1a-81ff-7bdc814dd867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147236417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1147236417
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.965254896
Short name T649
Test name
Test status
Simulation time 2195470537 ps
CPU time 2.06 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:49 PM PDT 24
Peak memory 201480 kb
Host smart-119760ce-3693-4962-b2e2-84e1604b9f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965254896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.965254896
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3890964279
Short name T376
Test name
Test status
Simulation time 2526295002 ps
CPU time 2.71 seconds
Started Jul 05 05:30:46 PM PDT 24
Finished Jul 05 05:30:50 PM PDT 24
Peak memory 201076 kb
Host smart-bc1e22e2-4a14-4476-bb97-f2dee555f1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890964279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3890964279
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.1468250491
Short name T192
Test name
Test status
Simulation time 2133704449 ps
CPU time 1.98 seconds
Started Jul 05 05:30:44 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201512 kb
Host smart-e270022d-9576-4f0e-979e-c465cbac1aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468250491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.1468250491
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.1526358447
Short name T199
Test name
Test status
Simulation time 8039272455 ps
CPU time 6.01 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:53 PM PDT 24
Peak memory 201732 kb
Host smart-0de3819c-d15a-4e8b-8a83-b635a1cc707d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526358447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.1526358447
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.682855520
Short name T145
Test name
Test status
Simulation time 31612137368 ps
CPU time 68.68 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:31:54 PM PDT 24
Peak memory 210044 kb
Host smart-5b072f68-cf3b-431a-8cac-656319950aea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682855520 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.682855520
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1826852707
Short name T631
Test name
Test status
Simulation time 7602287391 ps
CPU time 1.23 seconds
Started Jul 05 05:30:44 PM PDT 24
Finished Jul 05 05:30:47 PM PDT 24
Peak memory 201656 kb
Host smart-e1d69f73-0681-4700-ada4-28034eedacfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826852707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.1826852707
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3556429817
Short name T784
Test name
Test status
Simulation time 80235322795 ps
CPU time 191.29 seconds
Started Jul 05 05:32:42 PM PDT 24
Finished Jul 05 05:35:54 PM PDT 24
Peak memory 201920 kb
Host smart-56ce85ae-2850-4473-a466-ad68ced987ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556429817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.3556429817
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1168272563
Short name T121
Test name
Test status
Simulation time 26602345624 ps
CPU time 17.55 seconds
Started Jul 05 05:32:44 PM PDT 24
Finished Jul 05 05:33:04 PM PDT 24
Peak memory 201896 kb
Host smart-bb5464af-436d-4415-8c8e-94fdcdac6818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168272563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1168272563
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.186610569
Short name T355
Test name
Test status
Simulation time 110933973616 ps
CPU time 68 seconds
Started Jul 05 05:32:44 PM PDT 24
Finished Jul 05 05:33:54 PM PDT 24
Peak memory 201808 kb
Host smart-33b90d6c-4cf0-4d32-94af-9eca6ded0e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186610569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wi
th_pre_cond.186610569
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.955977806
Short name T350
Test name
Test status
Simulation time 57137173276 ps
CPU time 44.92 seconds
Started Jul 05 05:32:45 PM PDT 24
Finished Jul 05 05:33:32 PM PDT 24
Peak memory 201928 kb
Host smart-053398dc-6826-4921-9815-e4b9a48d31a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955977806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_wi
th_pre_cond.955977806
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2133080343
Short name T27
Test name
Test status
Simulation time 61876723436 ps
CPU time 38.94 seconds
Started Jul 05 05:32:42 PM PDT 24
Finished Jul 05 05:33:22 PM PDT 24
Peak memory 201888 kb
Host smart-a7ae354a-2567-48ae-9f26-b406f4a36566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133080343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.2133080343
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2632404183
Short name T486
Test name
Test status
Simulation time 40919009805 ps
CPU time 27.8 seconds
Started Jul 05 05:32:44 PM PDT 24
Finished Jul 05 05:33:13 PM PDT 24
Peak memory 201892 kb
Host smart-0773e56d-8886-4045-8776-ca8f94c61f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632404183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.2632404183
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1636602374
Short name T335
Test name
Test status
Simulation time 30933653996 ps
CPU time 44.71 seconds
Started Jul 05 05:32:44 PM PDT 24
Finished Jul 05 05:33:31 PM PDT 24
Peak memory 201880 kb
Host smart-344e620d-89f0-4f50-8b0b-f23f060b9c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636602374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1636602374
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.742308764
Short name T238
Test name
Test status
Simulation time 2087168602 ps
CPU time 0.96 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 201648 kb
Host smart-b00a1ea0-e9e5-43d5-83c9-6d5330fadade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742308764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test
.742308764
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.965872246
Short name T742
Test name
Test status
Simulation time 3318184945 ps
CPU time 5.81 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:51 PM PDT 24
Peak memory 201644 kb
Host smart-d7b515d1-c338-40e2-a399-d70b7a23236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965872246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.965872246
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3197821170
Short name T719
Test name
Test status
Simulation time 83609995434 ps
CPU time 59.04 seconds
Started Jul 05 05:30:44 PM PDT 24
Finished Jul 05 05:31:44 PM PDT 24
Peak memory 201872 kb
Host smart-e2306fba-1073-46f8-ba4d-a7441cf66912
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197821170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3197821170
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.303184678
Short name T511
Test name
Test status
Simulation time 143355893944 ps
CPU time 191.59 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:33:58 PM PDT 24
Peak memory 201856 kb
Host smart-8d7a3d31-b64c-4346-a7cf-f976711182fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303184678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wit
h_pre_cond.303184678
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.718564111
Short name T14
Test name
Test status
Simulation time 3727491217 ps
CPU time 2.85 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:49 PM PDT 24
Peak memory 201632 kb
Host smart-9c1fee49-e1ad-4b8c-8e6c-c47975f9df5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718564111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ec_pwr_on_rst.718564111
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.344155326
Short name T187
Test name
Test status
Simulation time 3312833192 ps
CPU time 9.77 seconds
Started Jul 05 05:30:42 PM PDT 24
Finished Jul 05 05:30:52 PM PDT 24
Peak memory 201612 kb
Host smart-3b78ddd0-3e07-4735-a351-e56bc3e741c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344155326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl
_edge_detect.344155326
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3029563300
Short name T574
Test name
Test status
Simulation time 2611627365 ps
CPU time 3.96 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:50 PM PDT 24
Peak memory 201552 kb
Host smart-4be0716b-a0bf-4912-8cfc-63a88949ed02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029563300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.3029563300
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3738020834
Short name T450
Test name
Test status
Simulation time 2494428520 ps
CPU time 2.51 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:49 PM PDT 24
Peak memory 201632 kb
Host smart-f7d20812-f17e-4f2c-864e-aabc63632522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738020834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3738020834
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.659010153
Short name T133
Test name
Test status
Simulation time 2213273247 ps
CPU time 2.04 seconds
Started Jul 05 05:30:49 PM PDT 24
Finished Jul 05 05:30:51 PM PDT 24
Peak memory 201484 kb
Host smart-91f438e4-f399-4564-81c6-cd7e65b185e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659010153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.659010153
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2258650355
Short name T720
Test name
Test status
Simulation time 2522476339 ps
CPU time 2.29 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:49 PM PDT 24
Peak memory 201636 kb
Host smart-f5088eeb-d203-4cff-b3f6-c51ef8fc1492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258650355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2258650355
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.3759973945
Short name T401
Test name
Test status
Simulation time 2112011550 ps
CPU time 5.66 seconds
Started Jul 05 05:30:45 PM PDT 24
Finished Jul 05 05:30:52 PM PDT 24
Peak memory 201544 kb
Host smart-b75c49f8-31f0-4dab-816e-075c6479d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759973945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3759973945
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.3375051515
Short name T233
Test name
Test status
Simulation time 8159759745 ps
CPU time 2.73 seconds
Started Jul 05 05:30:43 PM PDT 24
Finished Jul 05 05:30:47 PM PDT 24
Peak memory 201660 kb
Host smart-fe11823f-8abb-4bc0-accc-cccf8bafb433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375051515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.3375051515
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1387830102
Short name T142
Test name
Test status
Simulation time 14253103495 ps
CPU time 2.65 seconds
Started Jul 05 05:30:42 PM PDT 24
Finished Jul 05 05:30:45 PM PDT 24
Peak memory 201572 kb
Host smart-8a92657e-6bab-42b5-8b71-173dde22a91e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387830102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.1387830102
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2142626264
Short name T769
Test name
Test status
Simulation time 27327800387 ps
CPU time 68.95 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:33:54 PM PDT 24
Peak memory 201900 kb
Host smart-2857e0b6-95f6-45f1-b3ec-409757508268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142626264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.2142626264
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3665290271
Short name T345
Test name
Test status
Simulation time 103371334569 ps
CPU time 140.57 seconds
Started Jul 05 05:32:44 PM PDT 24
Finished Jul 05 05:35:07 PM PDT 24
Peak memory 201848 kb
Host smart-c153d7fd-3c62-4725-8c62-18b460b9b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665290271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.3665290271
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3135020828
Short name T732
Test name
Test status
Simulation time 37058801431 ps
CPU time 25.83 seconds
Started Jul 05 05:32:43 PM PDT 24
Finished Jul 05 05:33:11 PM PDT 24
Peak memory 201948 kb
Host smart-a51d85f0-68da-44be-91d6-fb1ee48f90ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135020828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3135020828
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.732417579
Short name T267
Test name
Test status
Simulation time 62125861705 ps
CPU time 108.86 seconds
Started Jul 05 05:32:48 PM PDT 24
Finished Jul 05 05:34:38 PM PDT 24
Peak memory 201936 kb
Host smart-83dfc2b6-c1b0-417c-935d-25eee1272240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732417579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_wi
th_pre_cond.732417579
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2403690849
Short name T682
Test name
Test status
Simulation time 59868165860 ps
CPU time 159.65 seconds
Started Jul 05 05:32:51 PM PDT 24
Finished Jul 05 05:35:32 PM PDT 24
Peak memory 201940 kb
Host smart-fc1a366b-f062-434e-a39b-16c8b6d1d04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403690849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.2403690849
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.443057576
Short name T479
Test name
Test status
Simulation time 46720465864 ps
CPU time 32.01 seconds
Started Jul 05 05:32:50 PM PDT 24
Finished Jul 05 05:33:23 PM PDT 24
Peak memory 201812 kb
Host smart-18d86d49-72f0-404d-b686-76b19036ec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443057576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_wi
th_pre_cond.443057576
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest
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