Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1839

1

T2

14

T3

16

T6

6

auto[1]

634

1

T2

3

T6

2

T9

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1819

1

T2

13

T3

12

T9

17

auto[1]

654

1

T2

4

T3

4

T6

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1893

1

T2

13

T3

16

T6

8

auto[1]

580

1

T2

4

T9

8

T80

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1843

1

T2

7

T3

16

T6

6

auto[1]

630

1

T2

10

T6

2

T36

9

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2256

1

T2

17

T3

16

T6

8

auto[1]

217

1

T56

4

T81

1

T82

12

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2278

1

T2

17

T3

16

T6

8

auto[1]

195

1

T36

6

T79

2

T81

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2259

1

T2

17

T3

16

T6

8

auto[1]

214

1

T36

9

T79

4

T56

7

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2265

1

T2

17

T3

12

T6

8

auto[1]

208

1

T3

4

T9

6

T26

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2284

1

T2

17

T3

12

T6

8

auto[1]

189

1

T3

4

T9

11

T36

9

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1900

1

T2

14

T3

16

T9

20

auto[1]

573

1

T2

3

T6

8

T36

9

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	877	1			T2	17		T6	6		T31	19
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	88	1			T56	4		T33	6		T358	9
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	61	1			T9	5		T36	9		T260	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	24	1			T150	5		T358	5		T351	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	72	1			T26	3		T79	3		T260	5
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	16	1			T359	1		T360	1		T361	8
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	26	1			T3	4		T9	6		T150	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T253	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	69	1			T36	9		T79	2		T253	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	27	1			T362	18		T352	6		T363	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	11	1			T364	2		T365	7		T366	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	17	1			T260	4		T352	11		T367	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T165	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	5	1			T368	1		T369	4		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T255	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	31	1			T36	6		T270	2		T370	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	13	1			T82	6		T33	3		T281	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	31	1			T262	4		T358	3		T371	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	24	1			T371	4		T372	4		T373	16
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T81	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T373	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T374	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	18	1			T82	4		T248	2		T33	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	13	1			T89	7		T368	6		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	12	1			T79	2		T375	3		T376	6
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	1	1			T377	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	6	1			T83	3		T359	3		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

97

1

T26

3

T36

6

T82

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

123

1

T79

3

T35

8

T151

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

65

1

T2

3

T260

4

T136

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

115

1

T2

10

T79

2

T113

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T34

7

T74

2

T143

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

34

1

T56

4

T204

4

T33

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T113

4

T136

5

T344

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

101

1

T9

3

T82

3

T260

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

65

1

T9

5

T260

3

T102

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T31

6

T81

1

T151

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T119

1

T35

1

T140

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T82

3

T151

2

T41

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

31

1

T225

4

T298

2

T378

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T101

3

T270

2

T379

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T119

1

T113

2

T370

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

82

1

T3

4

T9

3

T150

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

75

1

T34

7

T204

6

T51

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

73

1

T6

6

T36

9

T79

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T260

5

T140

4

T158

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

101

1

T31

8

T35

6

T74

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T36

9

T98

3

T253

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T380

4

T283

2

T381

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T31

1

T382

2

T383

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T2

4

T32

1

T384

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T150

6

T86

4

T105

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

11

1

T31

4

T119

2

T143

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T143

1

T385

1

T185

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T151

1

T102

2

T136

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T281

2

T298

1

T386

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T136

2

T387

3

T286

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T204

1

T343

2

T388

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded