Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T5

9

T13

8

T7

10

auto[1]

1026

1

T5

11

T13

12

T7

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

486

1

T5

4

T13

4

T7

5

from_0to1

480

1

T5

4

T13

4

T7

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T5

11

T13

10

T7

10

auto[1]

1033

1

T5

9

T13

10

T7

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T5

13

T13

9

T7

8

auto[1]

1043

1

T5

7

T13

11

T7

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T5

1

T13

1

T7

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T77

1

T22

1

T74

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T5

1

T13

1

T22

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T7

2

T22

2

T287

2

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T5

1

T290

1

T395

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T13

1

T287

3

T74

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T22

2

T53

1

T287

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T77

1

T22

2

T74

2

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T5

1

T77

1

T22

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T13

1

T7

1

T77

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T5

1

T13

1

T22

2

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T7

1

T53

1

T287

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T5

2

T13

1

T7

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T22

2

T53

1

T287

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T5

1

T13

2

T7

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T7

2

T77

2

T53

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T5

11

T13

9

T7

12

auto[1]

1051

1

T5

9

T13

11

T7

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

487

1

T5

5

T13

4

T7

2

from_0to1

486

1

T5

4

T13

5

T7

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T5

8

T13

13

T7

13

auto[1]

1023

1

T5

12

T13

7

T7

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T5

12

T13

9

T7

10

auto[1]

1092

1

T5

8

T13

11

T7

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T5

1

T13

1

T7

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T13

1

T74

2

T395

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T7

1

T77

2

T287

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T22

2

T287

1

T74

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T5

1

T22

2

T287

2

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T13

1

T7

1

T77

2

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T13

1

T7

1

T22

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T5

2

T22

4

T287

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T22

1

T53

2

T287

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T5

1

T13

1

T77

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T5

1

T22

2

T287

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T5

2

T13

1

T77

2

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T13

2

T53

1

T151

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T77

1

T22

1

T151

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T5

1

T22

1

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T13

1

T77

1

T74

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T5

11

T13

11

T7

10

auto[1]

1039

1

T5

9

T13

9

T7

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T5

5

T13

5

T7

3

from_0to1

510

1

T5

6

T13

6

T7

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T5

9

T13

11

T7

9

auto[1]

1037

1

T5

11

T13

9

T7

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T5

7

T13

11

T7

10

auto[1]

1059

1

T5

13

T13

9

T7

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T13

2

T7

1

T77

1

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T5

2

T7

1

T77

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T13

1

T22

1

T287

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T5

2

T13

1

T22

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T5

1

T13

1

T7

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T5

1

T287

1

T74

2

auto[0]

from_0to1

auto[1]

auto[0]

51

1

T77

2

T22

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T5

1

T7

1

T22

3

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T77

2

T22

1

T287

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T13

1

T22

1

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T7

1

T77

1

T74

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T5

1

T77

2

T22

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T5

1

T13

2

T7

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T5

1

T77

2

T22

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T5

1

T13

1

T77

1

auto[1]

from_0to1

auto[1]

auto[1]

89

1

T13

2

T53

3

T287

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1046

1

T5

6

T13

10

T7

14

auto[1]

1034

1

T5

14

T13

10

T7

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T5

5

T13

4

T7

6

from_0to1

522

1

T5

5

T13

4

T7

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T5

8

T13

12

T7

9

auto[1]

1053

1

T5

12

T13

8

T7

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T5

12

T13

8

T7

11

auto[1]

1081

1

T5

8

T13

12

T7

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T7

1

T77

1

T22

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T13

1

T22

2

T53

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T7

1

T22

5

T74

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T5

2

T7

2

T77

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T77

1

T22

1

T74

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T7

2

T287

1

T74

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T13

1

T7

3

T22

3

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T7

1

T77

1

T22

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T5

1

T13

1

T7

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T5

1

T22

1

T287

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T13

1

T7

1

T77

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T5

1

T13

1

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T5

3

T13

1

T77

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T13

1

T22

2

T53

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T5

2

T77

1

T22

2

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T13

1

T77

1

T287

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T5

10

T13

8

T7

9

auto[1]

1085

1

T5

10

T13

12

T7

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T5

4

T13

5

T7

4

from_0to1

516

1

T5

4

T13

5

T7

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T5

9

T13

13

T7

11

auto[1]

1051

1

T5

11

T13

7

T7

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T5

17

T13

9

T7

11

auto[1]

1039

1

T5

3

T13

11

T7

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T74

1

T290

2

T151

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T7

1

T77

1

T74

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T5

1

T7

1

T77

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T13

1

T74

3

T290

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T5

2

T13

1

T7

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T5

1

T13

2

T53

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T7

2

T53

1

T287

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T77

3

T74

2

T151

1

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T5

1

T13

2

T7

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T13

1

T22

1

T53

2

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T5

1

T13

1

T77

3

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T5

1

T7

1

T77

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T13

1

T7

1

T22

2

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T13

1

T77

1

T22

2

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T5

1

T287

1

T74

3

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T22

2

T53

1

T287

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T5

12

T13

13

T7

8

auto[1]

1028

1

T5

8

T13

7

T7

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T5

4

T13

6

T7

6

from_0to1

511

1

T5

4

T13

5

T7

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T5

9

T13

8

T7

12

auto[1]

1046

1

T5

11

T13

12

T7

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T5

10

T13

9

T7

9

auto[1]

1036

1

T5

10

T13

11

T7

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T5

1

T13

1

T7

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T77

1

T22

1

T53

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T13

1

T77

2

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T5

3

T13

2

T22

2

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T5

1

T13

1

T7

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T5

1

T13

1

T22

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T7

1

T22

1

T53

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T5

1

T13

1

T7

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T22

1

T290

1

T396

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T7

3

T77

2

T22

2

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T13

1

T7

1

T22

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T13

1

T7

1

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T5

1

T13

1

T74

1

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T7

1

T77

3

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T77

1

T22

2

T287

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T13

1

T7

1

T77

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T5

11

T13

14

T7

8

auto[1]

999

1

T5

9

T13

6

T7

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

521

1

T5

5

T13

5

T7

4

from_0to1

522

1

T5

5

T13

4

T7

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T5

9

T13

13

T7

6

auto[1]

1036

1

T5

11

T13

7

T7

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T5

9

T13

12

T7

11

auto[1]

1005

1

T5

11

T13

8

T7

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T77

1

T22

2

T151

1

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T7

1

T22

1

T74

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T13

1

T7

1

T22

2

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T13

1

T7

1

T77

3

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T5

1

T13

1

T53

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T77

1

T22

3

T287

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T5

1

T7

3

T22

2

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T5

1

T13

2

T77

2

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T5

1

T13

1

T77

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T13

1

T22

2

T53

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T5

3

T13

1

T7

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T5

1

T22

1

T53

2

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T5

1

T13

1

T77

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T5

1

T74

1

T290

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T77

1

T22

1

T53

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T77

1

T287

1

T396

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011

1

T5

10

T13

13

T7

8

auto[1]

1069

1

T5

10

T13

7

T7

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T5

5

T13

5

T7

5

from_0to1

522

1

T5

6

T13

5

T7

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T5

7

T13

12

T7

12

auto[1]

994

1

T5

13

T13

8

T7

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T5

8

T13

8

T7

13

auto[1]

1015

1

T5

12

T13

12

T7

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T5

1

T77

1

T22

2

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T13

1

T77

2

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T13

2

T22

2

T53

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T5

2

T7

2

T53

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T13

1

T77

1

T22

2

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T5

1

T13

2

T7

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T5

1

T77

2

T22

4

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T287

1

T74

1

T151

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T13

1

T7

1

T77

2

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T5

2

T7

1

T22

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T7

1

T22

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T13

1

T77

1

T22

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T5

1

T13

2

T7

3

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T5

1

T77

1

T53

2

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T5

1

T22

2

T287

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T5

1

T7

1

T22

1