Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115878

1

T1

38

T4

2

T2

291

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143247	1			T1	48		T4	5		T2	399
values[0x0]	63625	1			T1	15		T2	76		T12	34
values[0x1]	64472	1			T1	23		T4	1		T2	99

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125431	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145913

1

T1

46

T4

4

T2

344

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1151	1			T1	2		T2	1		T9	1
valid_sources[0x01]	901	1			T1	1		T2	2		T5	1
valid_sources[0x02]	990	1			T1	1		T2	4		T5	2
valid_sources[0x03]	1115	1			T2	1		T5	6		T9	2
valid_sources[0x04]	2220	1			T1	1		T2	2		T3	737
valid_sources[0x05]	913	1			T2	2		T5	2		T9	3
valid_sources[0x06]	946	1			T1	1		T2	1		T5	7
valid_sources[0x07]	988	1			T2	2		T14	1		T21	1
valid_sources[0x08]	1053	1			T2	4		T5	4		T6	2
valid_sources[0x09]	800	1			T1	1		T62	1		T9	1
valid_sources[0x0a]	944	1			T1	2		T2	1		T7	1
valid_sources[0x0b]	981	1			T1	1		T2	2		T5	4
valid_sources[0x0c]	871	1			T2	3		T12	3		T9	4
valid_sources[0x0d]	812	1			T5	2		T9	1		T26	22
valid_sources[0x0e]	757	1			T2	3		T5	1		T6	2
valid_sources[0x0f]	891	1			T2	3		T5	9		T9	2
valid_sources[0x10]	864	1			T2	2		T12	1		T5	3
valid_sources[0x11]	1815	1			T2	1		T6	4		T21	1
valid_sources[0x12]	1251	1			T1	1		T2	4		T8	7
valid_sources[0x13]	820	1			T2	1		T5	6		T7	8
valid_sources[0x14]	1386	1			T2	3		T12	1		T21	1
valid_sources[0x15]	794	1			T2	2		T5	1		T6	3
valid_sources[0x16]	707	1			T2	3		T5	4		T9	2
valid_sources[0x17]	1059	1			T5	1		T14	1		T9	3
valid_sources[0x18]	1237	1			T2	1		T9	4		T26	8
valid_sources[0x19]	1665	1			T2	1		T5	9		T7	1
valid_sources[0x1a]	839	1			T2	1		T5	1		T9	1
valid_sources[0x1b]	797	1			T14	1		T7	2		T21	2
valid_sources[0x1c]	1191	1			T1	1		T2	2		T5	6
valid_sources[0x1d]	782	1			T2	3		T9	2		T63	1
valid_sources[0x1e]	764	1			T2	5		T5	4		T9	1
valid_sources[0x1f]	972	1			T2	1		T5	4		T14	1
valid_sources[0x20]	824	1			T2	3		T5	1		T7	1
valid_sources[0x21]	895	1			T2	2		T5	1		T7	6
valid_sources[0x22]	836	1			T2	1		T12	2		T7	2
valid_sources[0x23]	958	1			T9	3		T69	12		T77	1
valid_sources[0x24]	1296	1			T12	2		T5	1		T9	3
valid_sources[0x25]	978	1			T1	1		T2	2		T12	1
valid_sources[0x26]	829	1			T1	1		T2	3		T5	8
valid_sources[0x27]	896	1			T2	2		T26	6		T36	4
valid_sources[0x28]	831	1			T4	1		T2	7		T5	4
valid_sources[0x29]	871	1			T2	4		T5	5		T7	3
valid_sources[0x2a]	947	1			T2	4		T5	2		T7	2
valid_sources[0x2b]	1353	1			T2	2		T5	3		T9	4
valid_sources[0x2c]	798	1			T2	2		T5	4		T9	4
valid_sources[0x2d]	1111	1			T2	4		T21	1		T9	2
valid_sources[0x2e]	746	1			T2	3		T12	1		T14	2
valid_sources[0x2f]	1269	1			T1	1		T2	6		T12	3
valid_sources[0x30]	1366	1			T1	1		T21	1		T62	1
valid_sources[0x31]	870	1			T2	3		T12	1		T5	8
valid_sources[0x32]	961	1			T2	2		T5	2		T26	9
valid_sources[0x33]	1048	1			T2	1		T9	2		T26	5
valid_sources[0x34]	932	1			T2	1		T9	3		T36	7
valid_sources[0x35]	1297	1			T1	1		T2	4		T5	8
valid_sources[0x36]	958	1			T1	1		T2	6		T12	4
valid_sources[0x37]	796	1			T2	2		T9	3		T26	15
valid_sources[0x38]	1550	1			T2	3		T9	1		T71	1
valid_sources[0x39]	1326	1			T2	2		T5	5		T7	1
valid_sources[0x3a]	1186	1			T2	2		T21	2		T9	2
valid_sources[0x3b]	1086	1			T2	4		T21	1		T9	4
valid_sources[0x3c]	826	1			T1	1		T2	3		T9	3
valid_sources[0x3d]	3142	1			T1	1		T5	5		T7	1
valid_sources[0x3e]	1038	1			T2	1		T62	1		T9	7
valid_sources[0x3f]	987	1			T1	1		T2	3		T9	6
valid_sources[0x40]	948	1			T1	2		T2	4		T5	13
valid_sources[0x41]	1048	1			T2	1		T5	8		T6	16
valid_sources[0x42]	773	1			T2	1		T5	9		T21	1
valid_sources[0x43]	802	1			T1	2		T2	1		T5	1
valid_sources[0x44]	792	1			T2	4		T9	2		T77	2
valid_sources[0x45]	1238	1			T2	5		T7	1		T8	1
valid_sources[0x46]	886	1			T2	1		T5	8		T21	1
valid_sources[0x47]	899	1			T2	2		T5	4		T14	1
valid_sources[0x48]	770	1			T2	3		T14	1		T9	5
valid_sources[0x49]	1096	1			T5	1		T8	7		T21	1
valid_sources[0x4a]	2005	1			T2	4		T5	3		T9	1
valid_sources[0x4b]	789	1			T2	2		T5	2		T7	4
valid_sources[0x4c]	1006	1			T2	2		T5	4		T9	1
valid_sources[0x4d]	1190	1			T5	3		T7	1		T9	2
valid_sources[0x4e]	830	1			T1	1		T2	1		T14	1
valid_sources[0x4f]	1246	1			T1	1		T2	4		T5	4
valid_sources[0x50]	893	1			T2	2		T5	3		T9	1
valid_sources[0x51]	887	1			T1	2		T2	3		T9	2
valid_sources[0x52]	936	1			T1	1		T2	1		T14	2
valid_sources[0x53]	953	1			T2	7		T5	1		T21	2
valid_sources[0x54]	909	1			T2	1		T5	4		T6	26
valid_sources[0x55]	792	1			T2	1		T12	1		T6	9
valid_sources[0x56]	1746	1			T9	4		T71	1		T26	5
valid_sources[0x57]	838	1			T2	1		T5	1		T7	1
valid_sources[0x58]	1529	1			T2	1		T5	3		T7	2
valid_sources[0x59]	2593	1			T8	5		T9	4		T26	3
valid_sources[0x5a]	823	1			T2	3		T7	2		T9	2
valid_sources[0x5b]	862	1			T2	2		T7	1		T9	4
valid_sources[0x5c]	858	1			T1	1		T4	1		T2	2
valid_sources[0x5d]	962	1			T2	6		T15	1		T7	1
valid_sources[0x5e]	1098	1			T2	1		T12	7		T14	2
valid_sources[0x5f]	1008	1			T2	1		T6	16		T9	4
valid_sources[0x60]	1048	1			T2	3		T9	3		T71	1
valid_sources[0x61]	809	1			T2	7		T5	2		T7	2
valid_sources[0x62]	691	1			T2	4		T12	3		T5	3
valid_sources[0x63]	773	1			T2	2		T5	10		T21	4
valid_sources[0x64]	912	1			T2	2		T6	13		T15	1
valid_sources[0x65]	1027	1			T1	1		T2	7		T6	30
valid_sources[0x66]	816	1			T2	1		T12	7		T5	1
valid_sources[0x67]	753	1			T2	1		T12	6		T5	1
valid_sources[0x68]	871	1			T2	2		T6	8		T7	2
valid_sources[0x69]	721	1			T2	3		T14	2		T7	7
valid_sources[0x6a]	972	1			T2	2		T21	1		T9	3
valid_sources[0x6b]	997	1			T2	1		T5	5		T9	1
valid_sources[0x6c]	1472	1			T2	2		T5	9		T9	6
valid_sources[0x6d]	861	1			T1	1		T2	3		T5	1
valid_sources[0x6e]	946	1			T1	1		T2	5		T5	5
valid_sources[0x6f]	1074	1			T1	2		T2	6		T7	2
valid_sources[0x70]	763	1			T1	1		T2	1		T12	1
valid_sources[0x71]	1624	1			T1	1		T2	1		T5	5
valid_sources[0x72]	1288	1			T2	2		T5	8		T14	1
valid_sources[0x73]	1057	1			T2	4		T6	4		T14	1
valid_sources[0x74]	784	1			T1	1		T5	4		T9	4
valid_sources[0x75]	961	1			T2	1		T21	2		T26	1
valid_sources[0x76]	856	1			T1	1		T5	2		T7	1
valid_sources[0x77]	1899	1			T1	1		T2	1		T5	1
valid_sources[0x78]	1079	1			T2	1		T9	1		T26	4
valid_sources[0x79]	919	1			T1	1		T2	5		T7	1
valid_sources[0x7a]	1767	1			T2	1		T6	4		T8	3
valid_sources[0x7b]	2077	1			T2	2		T5	7		T9	5
valid_sources[0x7c]	1279	1			T2	2		T5	1		T9	1
valid_sources[0x7d]	1766	1			T2	2		T5	7		T9	5
valid_sources[0x7e]	937	1			T1	1		T2	3		T7	7
valid_sources[0x7f]	1144	1			T1	1		T2	6		T7	1
valid_sources[0x80]	1566	1			T2	2		T5	3		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63764

1

T1

26

T4

2

T2

204

values[0x0]

all_enables

biggest_size

30524

1

T1

6

T2

43

T12

7

values[0x1]

all_enables

biggest_size

21590

1

T1

6

T2

44

T12

7