Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T22,T24,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T22,T24,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T22,T24,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T22,T24,T20
1	0	Covered	T1,T4,T2
1	1	Covered	T22,T24,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T24,T20
0	1	Covered	T50,T88,T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T24,T20
0	1	Covered	T22,T24,T20
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T22,T24,T20
1	-	Covered	T22,T24,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T22,T24,T20
DetectSt	168	Covered	T22,T24,T20
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T22,T24,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T24,T20
DebounceSt->IdleSt	163	Covered	T22,T96,T124
DetectSt->IdleSt	186	Covered	T50,T88,T109
DetectSt->StableSt	191	Covered	T22,T24,T20
IdleSt->DebounceSt	148	Covered	T22,T24,T20
StableSt->IdleSt	206	Covered	T22,T24,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T22,T24,T20
0	1	Covered	T22,T24,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T22,T24,T20
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T22,T24,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T24,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T96,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T22,T24,T20
DetectSt	-	-	-	-	1	-	-	Covered	T50,T88,T109
DetectSt	-	-	-	-	0	1	-	Covered	T22,T24,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T24,T20
StableSt	-	-	-	-	-	-	0	Covered	T22,T24,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	219	0	0
CntIncr_A	6866773	81591	0	0
CntNoWrap_A	6866773	6204500	0	0
DetectStDropOut_A	6866773	3	0	0
DetectedOut_A	6866773	614	0	0
DetectedPulseOut_A	6866773	98	0	0
DisabledIdleSt_A	6866773	6118002	0	0
DisabledNoDetection_A	6866773	6120312	0	0
EnterDebounceSt_A	6866773	120	0	0
EnterDetectSt_A	6866773	101	0	0
EnterStableSt_A	6866773	98	0	0
PulseIsPulse_A	6866773	98	0	0
StayInStableSt	6866773	516	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6866773	6689	0	0
gen_low_level_sva.LowLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	97	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	219	0	0
T20	0	4	0	0
T22	8506	5	0	0
T24	0	4	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	4	0	0
T48	0	4	0	0
T50	0	6	0	0
T51	0	4	0	0
T52	0	2	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	3	0	0
T97	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	81591	0	0
T20	0	135	0	0
T22	8506	229	0	0
T24	0	160	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	78	0	0
T48	0	169	0	0
T50	0	97	0	0
T51	0	177	0	0
T52	0	100	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	147	0	0
T97	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204500	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	3	0	0
T50	627	1	0	0
T88	0	1	0	0
T109	0	1	0	0
T110	4572	0	0	0
T111	447	0	0	0
T112	490	0	0	0
T113	28658	0	0	0
T114	423	0	0	0
T115	633	0	0	0
T116	494	0	0	0
T117	414	0	0	0
T118	623	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	614	0	0
T20	0	12	0	0
T22	8506	15	0	0
T24	0	11	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	14	0	0
T48	0	15	0	0
T50	0	13	0	0
T51	0	15	0	0
T52	0	12	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	3	0	0
T97	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	98	0	0
T20	0	2	0	0
T22	8506	2	0	0
T24	0	2	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	1	0	0
T97	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6118002	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6120312	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	120	0	0
T20	0	2	0	0
T22	8506	3	0	0
T24	0	2	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	2	0	0
T48	0	2	0	0
T50	0	3	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	2	0	0
T97	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	101	0	0
T20	0	2	0	0
T22	8506	2	0	0
T24	0	2	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	2	0	0
T48	0	2	0	0
T50	0	3	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	1	0	0
T97	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	98	0	0
T20	0	2	0	0
T22	8506	2	0	0
T24	0	2	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	1	0	0
T97	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	98	0	0
T20	0	2	0	0
T22	8506	2	0	0
T24	0	2	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	1	0	0
T97	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	516	0	0
T20	0	10	0	0
T22	8506	13	0	0
T24	0	9	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	12	0	0
T48	0	13	0	0
T50	0	11	0	0
T51	0	13	0	0
T52	0	11	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	2	0	0
T97	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6689	0	0
T1	2325	9	0	0
T2	26978	11	0	0
T3	6426	23	0	0
T4	408	1	0	0
T5	6099	5	0	0
T6	16271	13	0	0
T12	521	4	0	0
T13	502	5	0	0
T14	494	5	0	0
T15	408	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	97	0	0
T20	0	2	0	0
T22	8506	2	0	0
T24	0	2	0	0
T31	16254	0	0	0
T40	590	0	0	0
T41	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	507	0	0	0
T54	523	0	0	0
T55	606	0	0	0
T56	37468	0	0	0
T57	407	0	0	0
T58	523	0	0	0
T59	432	0	0	0
T96	0	1	0	0
T97	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T19,T66

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T19,T20
1	0	Covered	T1,T4,T2
1	1	Covered	T8,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T19,T66
0	1	Covered	T43,T94,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T19,T66
0	1	Unreachable
1	0	Covered	T8,T19,T66

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T19,T20
DetectSt	168	Covered	T8,T19,T66
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T19,T66

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T19,T66
DebounceSt->IdleSt	163	Covered	T20,T43,T120
DetectSt->IdleSt	186	Covered	T43,T94,T95
DetectSt->StableSt	191	Covered	T8,T19,T66
IdleSt->DebounceSt	148	Covered	T8,T19,T20
StableSt->IdleSt	206	Covered	T8,T19,T66

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T19,T20
0	1	Covered	T8,T19,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T19,T66
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T19,T66
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T43,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T43,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T8,T19,T66
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T19,T66
StableSt	-	-	-	-	-	-	0	Covered	T8,T19,T66
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	183	0	0
CntIncr_A	6866773	76835	0	0
CntNoWrap_A	6866773	6204536	0	0
DetectStDropOut_A	6866773	19	0	0
DetectedOut_A	6866773	216018	0	0
DetectedPulseOut_A	6866773	53	0	0
DisabledIdleSt_A	6866773	5341775	0	0
DisabledNoDetection_A	6866773	5344123	0	0
EnterDebounceSt_A	6866773	112	0	0
EnterDetectSt_A	6866773	72	0	0
EnterStableSt_A	6866773	53	0	0
PulseIsPulse_A	6866773	53	0	0
StayInStableSt	6866773	215965	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6866773	6689	0	0
gen_low_level_sva.LowLevelEvent_A	6866773	6207068	0	0
gen_sticky_sva.StableStDropOut_A	6866773	297732	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	183	0	0
T8	1940	2	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	2	0	0
T20	0	4	0	0
T21	1427	0	0	0
T41	0	2	0	0
T43	0	9	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	6	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	2	0	0
T85	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	76835	0	0
T8	1940	72	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	90	0	0
T20	0	216	0	0
T21	1427	0	0	0
T41	0	73	0	0
T43	0	170	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	76	0	0
T67	0	32	0	0
T68	0	177	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	99	0	0
T85	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204536	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	19	0	0
T43	12568	4	0	0
T51	15104	0	0	0
T52	786	0	0	0
T84	1338	0	0	0
T93	0	6	0	0
T94	0	2	0	0
T95	0	3	0	0
T96	760	0	0	0
T98	20494	0	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	422	0	0	0
T130	424	0	0	0
T131	402	0	0	0
T132	527	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	216018	0	0
T8	1940	402	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	377	0	0
T21	1427	0	0	0
T41	0	203	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	273	0	0
T67	0	158	0	0
T68	0	269	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	294	0	0
T85	0	194	0	0
T121	0	72416	0	0
T122	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	53	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5341775	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5344123	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	112	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	5	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	72	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	4	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	53	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	53	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T121	0	2	0	0
T122	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	215965	0	0
T8	1940	401	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	376	0	0
T21	1427	0	0	0
T41	0	202	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	272	0	0
T67	0	157	0	0
T68	0	266	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	293	0	0
T85	0	193	0	0
T121	0	72414	0	0
T122	0	48	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6689	0	0
T1	2325	9	0	0
T2	26978	11	0	0
T3	6426	23	0	0
T4	408	1	0	0
T5	6099	5	0	0
T6	16271	13	0	0
T12	521	4	0	0
T13	502	5	0	0
T14	494	5	0	0
T15	408	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	297732	0	0
T8	1940	110	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	188	0	0
T21	1427	0	0	0
T41	0	54	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	57	0	0
T67	0	231	0	0
T68	0	288	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	50	0	0
T85	0	55	0	0
T121	0	85	0	0
T122	0	244	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T12,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T12,T5
1	1	Covered	T1,T12,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T19,T20
1	0	Covered	T1,T12,T5
1	1	Covered	T8,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T19,T20
0	1	Covered	T91,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T19,T20
0	1	Unreachable
1	0	Covered	T8,T19,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T19,T20
DetectSt	168	Covered	T8,T19,T20
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T19,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T19,T20
DebounceSt->IdleSt	163	Covered	T120,T123,T133
DetectSt->IdleSt	186	Covered	T91,T92,T93
DetectSt->StableSt	191	Covered	T8,T19,T20
IdleSt->DebounceSt	148	Covered	T8,T19,T20
StableSt->IdleSt	206	Covered	T8,T19,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T19,T20
0	1	Covered	T8,T19,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T19,T20
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T12,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T120,T123,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T91,T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T8,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T8,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	171	0	0
CntIncr_A	6866773	422268	0	0
CntNoWrap_A	6866773	6204548	0	0
DetectStDropOut_A	6866773	12	0	0
DetectedOut_A	6866773	9780	0	0
DetectedPulseOut_A	6866773	56	0	0
DisabledIdleSt_A	6866773	5341775	0	0
DisabledNoDetection_A	6866773	5344123	0	0
EnterDebounceSt_A	6866773	104	0	0
EnterDetectSt_A	6866773	68	0	0
EnterStableSt_A	6866773	56	0	0
PulseIsPulse_A	6866773	56	0	0
StayInStableSt	6866773	9724	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_sticky_sva.StableStDropOut_A	6866773	178634	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	171	0	0
T8	1940	2	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T21	1427	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	6	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	2	0	0
T85	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	422268	0	0
T8	1940	49	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	51	0	0
T20	0	39	0	0
T21	1427	0	0	0
T41	0	69	0	0
T43	0	39	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	22	0	0
T67	0	20	0	0
T68	0	45	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	45	0	0
T85	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204548	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	12	0	0
T91	3826	5	0	0
T92	0	2	0	0
T93	0	2	0	0
T125	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	32427	0	0	0
T137	644	0	0	0
T138	431	0	0	0
T139	424	0	0	0
T140	17873	0	0	0
T141	529	0	0	0
T142	662	0	0	0
T143	19941	0	0	0
T144	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	9780	0	0
T8	1940	247	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	255	0	0
T20	0	202	0	0
T21	1427	0	0	0
T41	0	142	0	0
T43	0	330	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	92	0	0
T67	0	85	0	0
T68	0	95	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	70	0	0
T85	0	156	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	56	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5341775	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5344123	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	104	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	68	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	56	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	56	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	9724	0	0
T8	1940	246	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	254	0	0
T20	0	201	0	0
T21	1427	0	0	0
T41	0	141	0	0
T43	0	329	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	91	0	0
T67	0	84	0	0
T68	0	92	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	69	0	0
T85	0	155	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	178634	0	0
T8	1940	288	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	355	0	0
T20	0	385	0	0
T21	1427	0	0	0
T41	0	122	0	0
T43	0	554	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	309	0	0
T67	0	315	0	0
T68	0	608	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	330	0	0
T85	0	108	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T8,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T8,T66,T67

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T19,T20
1	0	Covered	T1,T2,T12
1	1	Covered	T8,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T67,T68
0	1	Covered	T8,T66,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T67,T68
0	1	Unreachable
1	0	Covered	T8,T67,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T19,T20
DetectSt	168	Covered	T8,T66,T67
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T8,T67,T68

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T66,T67
DebounceSt->IdleSt	163	Covered	T19,T20,T66
DetectSt->IdleSt	186	Covered	T8,T66,T90
DetectSt->StableSt	191	Covered	T8,T67,T68
IdleSt->DebounceSt	148	Covered	T8,T19,T20
StableSt->IdleSt	206	Covered	T8,T67,T68

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T19,T20
0	1	Covered	T8,T19,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T66,T67
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T66,T67
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T20,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T8,T66,T90
DetectSt	-	-	-	-	0	1	-	Covered	T8,T67,T68
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T67,T68
StableSt	-	-	-	-	-	-	0	Covered	T8,T67,T68
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	186	0	0
CntIncr_A	6866773	67906	0	0
CntNoWrap_A	6866773	6204533	0	0
DetectStDropOut_A	6866773	20	0	0
DetectedOut_A	6866773	231518	0	0
DetectedPulseOut_A	6866773	52	0	0
DisabledIdleSt_A	6866773	5341775	0	0
DisabledNoDetection_A	6866773	5344123	0	0
EnterDebounceSt_A	6866773	115	0	0
EnterDetectSt_A	6866773	72	0	0
EnterStableSt_A	6866773	52	0	0
PulseIsPulse_A	6866773	52	0	0
StayInStableSt	6866773	231466	0	0
gen_high_event_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_sticky_sva.StableStDropOut_A	6866773	259989	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	186	0	0
T8	1940	10	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	3	0	0
T20	0	4	0	0
T21	1427	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	5	0	0
T67	0	2	0	0
T68	0	6	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	2	0	0
T85	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	67906	0	0
T8	1940	455	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	234	0	0
T20	0	392	0	0
T21	1427	0	0	0
T41	0	41	0	0
T43	0	95	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	63	0	0
T67	0	60	0	0
T68	0	270	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	73	0	0
T85	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204533	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	20	0	0
T8	1940	4	0	0
T9	15043	0	0	0
T10	856	0	0	0
T21	1427	0	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	2	0	0
T69	522	0	0	0
T70	426	0	0	0
T90	0	2	0	0
T92	0	5	0	0
T145	0	1	0	0
T146	0	5	0	0
T147	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	231518	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T21	1427	0	0	0
T41	0	109	0	0
T43	0	782	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T67	0	321	0	0
T68	0	399	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	148	0	0
T85	0	70	0	0
T120	0	150	0	0
T121	0	189	0	0
T123	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	52	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5341775	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5344123	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	115	0	0
T8	1940	5	0	0
T9	15043	0	0	0
T10	856	0	0	0
T19	0	3	0	0
T20	0	4	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	3	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	72	0	0
T8	1940	5	0	0
T9	15043	0	0	0
T10	856	0	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	52	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	52	0	0
T8	1940	1	0	0
T9	15043	0	0	0
T10	856	0	0	0
T21	1427	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T67	0	1	0	0
T68	0	3	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	231466	0	0
T41	0	108	0	0
T43	0	781	0	0
T67	1279	320	0	0
T68	0	396	0	0
T75	493	0	0	0
T76	491	0	0	0
T83	6496	0	0	0
T84	0	147	0	0
T85	0	69	0	0
T120	0	149	0	0
T121	0	187	0	0
T123	0	38	0	0
T133	0	399	0	0
T148	424	0	0	0
T149	526	0	0	0
T150	17937	0	0	0
T151	11980	0	0	0
T152	444	0	0	0
T153	523	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	259989	0	0
T8	1940	37	0	0
T9	15043	0	0	0
T10	856	0	0	0
T21	1427	0	0	0
T41	0	200	0	0
T43	0	50	0	0
T61	874	0	0	0
T62	607	0	0	0
T63	1096	0	0	0
T64	591	0	0	0
T67	0	47	0	0
T68	0	106	0	0
T69	522	0	0	0
T70	426	0	0	0
T84	0	234	0	0
T85	0	195	0	0
T120	0	112	0	0
T121	0	129388	0	0
T123	0	30	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T7,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T7,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T20
0	1	Covered	T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T20
0	1	Covered	T1,T7,T20
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T20
1	-	Covered	T1,T7,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T20
DetectSt	168	Covered	T1,T7,T20
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T7,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T20
DebounceSt->IdleSt	163	Covered	T39,T87,T155
DetectSt->IdleSt	186	Covered	T154
DetectSt->StableSt	191	Covered	T1,T7,T20
IdleSt->DebounceSt	148	Covered	T1,T7,T20
StableSt->IdleSt	206	Covered	T1,T7,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T20
0	1	Covered	T1,T7,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T20
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T20
DetectSt	-	-	-	-	1	-	-	Covered	T154
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T20
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	59	0	0
CntIncr_A	6866773	129045	0	0
CntNoWrap_A	6866773	6204660	0	0
DetectStDropOut_A	6866773	1	0	0
DetectedOut_A	6866773	66033	0	0
DetectedPulseOut_A	6866773	27	0	0
DisabledIdleSt_A	6866773	5809425	0	0
DisabledNoDetection_A	6866773	5811732	0	0
EnterDebounceSt_A	6866773	31	0	0
EnterDetectSt_A	6866773	28	0	0
EnterStableSt_A	6866773	27	0	0
PulseIsPulse_A	6866773	27	0	0
StayInStableSt	6866773	65996	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	59	0	0
T1	2325	4	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	2	0	0
T39	0	1	0	0
T43	0	4	0	0
T60	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	129045	0	0
T1	2325	75	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	81	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	56	0	0
T39	0	67	0	0
T43	0	82	0	0
T60	0	26	0	0
T156	0	65	0	0
T157	0	80	0	0
T158	0	26	0	0
T159	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204660	0	0
T1	2325	718	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1	0	0
T127	4836	0	0	0
T154	872	1	0	0
T160	523	0	0	0
T161	841	0	0	0
T162	543	0	0	0
T163	3095	0	0	0
T164	17275	0	0	0
T165	15810	0	0	0
T166	10111	0	0	0
T167	740	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	66033	0	0
T1	2325	140	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	32	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	101	0	0
T43	0	82	0	0
T60	0	17	0	0
T156	0	39	0	0
T157	0	140	0	0
T158	0	65	0	0
T159	0	298	0	0
T168	0	197	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	27	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T168	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5809425	0	0
T1	2325	99	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1346	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5811732	0	0
T1	2325	100	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1359	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	31	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	28	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T168	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	27	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T168	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	27	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T168	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	65996	0	0
T1	2325	137	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	31	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	100	0	0
T43	0	79	0	0
T60	0	16	0	0
T156	0	37	0	0
T157	0	139	0	0
T158	0	63	0	0
T159	0	297	0	0
T168	0	195	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	16	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T43	0	1	0	0
T95	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T168	0	2	0	0
T169	0	2	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T7,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T7,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T40
0	1	Covered	T43,T171,T172
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T40
0	1	Covered	T1,T7,T42
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T40
1	-	Covered	T1,T7,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T40
DetectSt	168	Covered	T1,T7,T40
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T7,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T40
DebounceSt->IdleSt	163	Covered	T173,T87,T174
DetectSt->IdleSt	186	Covered	T43,T171,T172
DetectSt->StableSt	191	Covered	T1,T7,T40
IdleSt->DebounceSt	148	Covered	T1,T7,T40
StableSt->IdleSt	206	Covered	T1,T7,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T40
0	1	Covered	T1,T7,T40
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T40
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T173,T174,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T40
DetectSt	-	-	-	-	1	-	-	Covered	T43,T171,T172
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T42
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	126	0	0
CntIncr_A	6866773	324472	0	0
CntNoWrap_A	6866773	6204593	0	0
DetectStDropOut_A	6866773	4	0	0
DetectedOut_A	6866773	69711	0	0
DetectedPulseOut_A	6866773	56	0	0
DisabledIdleSt_A	6866773	5421218	0	0
DisabledNoDetection_A	6866773	5423513	0	0
EnterDebounceSt_A	6866773	66	0	0
EnterDetectSt_A	6866773	60	0	0
EnterStableSt_A	6866773	56	0	0
PulseIsPulse_A	6866773	56	0	0
StayInStableSt	6866773	69629	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6866773	2621	0	0
gen_low_level_sva.LowLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	126	0	0
T1	2325	4	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	4	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	4	0	0
T40	0	2	0	0
T42	0	6	0	0
T43	0	6	0	0
T45	0	2	0	0
T176	0	4	0	0
T177	0	2	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	324472	0	0
T1	2325	38	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	162	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	182	0	0
T40	0	57	0	0
T42	0	193761	0	0
T43	0	165	0	0
T45	0	92	0	0
T176	0	138	0	0
T177	0	12	0	0
T178	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204593	0	0
T1	2325	718	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	4	0	0
T43	12568	1	0	0
T51	15104	0	0	0
T52	786	0	0	0
T84	1338	0	0	0
T96	760	0	0	0
T98	20494	0	0	0
T129	422	0	0	0
T130	424	0	0	0
T131	402	0	0	0
T132	527	0	0	0
T171	0	1	0	0
T172	0	1	0	0
T179	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	69711	0	0
T1	2325	101	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	158	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	245	0	0
T40	0	47	0	0
T42	0	65064	0	0
T43	0	294	0	0
T45	0	219	0	0
T176	0	114	0	0
T177	0	68	0	0
T178	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	56	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T45	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5421218	0	0
T1	2325	454	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1346	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5423513	0	0
T1	2325	456	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1359	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	66	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	60	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	56	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T45	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	56	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T45	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	69629	0	0
T1	2325	98	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	155	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	242	0	0
T40	0	45	0	0
T42	0	65060	0	0
T43	0	291	0	0
T45	0	217	0	0
T176	0	112	0	0
T177	0	66	0	0
T178	0	24	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	2621	0	0
T1	2325	9	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	7	0	0
T6	16271	0	0	0
T7	0	9	0	0
T10	0	2	0	0
T12	521	8	0	0
T13	502	7	0	0
T14	494	6	0	0
T15	408	1	0	0
T21	0	10	0	0
T69	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	29	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T176	0	2	0	0
T178	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0