Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T42,T43,T39
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T7
0	1	Covered	T1,T40,T42
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T7
1	-	Covered	T1,T40,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T1,T5,T7
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T5,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T7
DebounceSt->IdleSt	163	Covered	T38,T198,T173
DetectSt->IdleSt	186	Covered	T42,T43,T39
DetectSt->StableSt	191	Covered	T1,T5,T7
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T1,T5,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T198,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T42,T43,T39
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T40,T42
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	128	0	0
CntIncr_A	6866773	132856	0	0
CntNoWrap_A	6866773	6204591	0	0
DetectStDropOut_A	6866773	7	0	0
DetectedOut_A	6866773	4882	0	0
DetectedPulseOut_A	6866773	55	0	0
DisabledIdleSt_A	6866773	5798692	0	0
DisabledNoDetection_A	6866773	5800988	0	0
EnterDebounceSt_A	6866773	67	0	0
EnterDetectSt_A	6866773	62	0	0
EnterStableSt_A	6866773	55	0	0
PulseIsPulse_A	6866773	55	0	0
StayInStableSt	6866773	4808	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	128	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	2	0	0
T6	16271	0	0	0
T7	0	2	0	0
T11	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T55	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	132856	0	0
T1	2325	19	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	34	0	0
T6	16271	0	0	0
T7	0	81	0	0
T11	0	22	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	56	0	0
T37	0	97	0	0
T40	0	57	0	0
T41	0	11	0	0
T42	0	129174	0	0
T55	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204591	0	0
T1	2325	720	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1468	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	7	0	0
T37	986	0	0	0
T39	0	1	0	0
T41	324659	0	0	0
T42	389074	1	0	0
T43	0	1	0	0
T50	627	0	0	0
T110	4572	0	0	0
T154	0	1	0	0
T171	0	2	0	0
T200	858	0	0	0
T201	441	0	0	0
T202	489	0	0	0
T203	402	0	0	0
T204	25580	0	0	0
T219	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	4882	0	0
T1	2325	59	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	38	0	0
T6	16271	0	0	0
T7	0	150	0	0
T11	0	43	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	198	0	0
T37	0	230	0	0
T40	0	19	0	0
T41	0	68	0	0
T42	0	619	0	0
T55	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	55	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T55	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5798692	0	0
T1	2325	99	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1346	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5800988	0	0
T1	2325	100	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1359	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	67	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T55	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	62	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T55	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	55	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T55	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	55	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T55	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	4808	0	0
T1	2325	58	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	36	0	0
T6	16271	0	0	0
T7	0	148	0	0
T11	0	41	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	196	0	0
T37	0	229	0	0
T40	0	18	0	0
T41	0	67	0	0
T42	0	618	0	0
T55	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	35	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T176	0	2	0	0
T181	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T40,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T5,T40,T74

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T5,T40,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T12
1	1	Covered	T5,T40,T74

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T40,T37
0	1	Covered	T127
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T40,T37
0	1	Covered	T5,T43,T123
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T40,T37
1	-	Covered	T5,T43,T123

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T40,T74
DetectSt	168	Covered	T5,T40,T37
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T5,T40,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T40,T37
DebounceSt->IdleSt	163	Covered	T74,T220,T87
DetectSt->IdleSt	186	Covered	T127
DetectSt->StableSt	191	Covered	T5,T40,T37
IdleSt->DebounceSt	148	Covered	T5,T40,T74
StableSt->IdleSt	206	Covered	T5,T43,T123

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T40,T37
0	1	Covered	T5,T40,T74
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T40,T37
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T40,T74
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T40,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T220
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T40,T74
DetectSt	-	-	-	-	1	-	-	Covered	T127
DetectSt	-	-	-	-	0	1	-	Covered	T5,T40,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T43,T123
StableSt	-	-	-	-	-	-	0	Covered	T5,T40,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	80	0	0
CntIncr_A	6866773	35087	0	0
CntNoWrap_A	6866773	6204639	0	0
DetectStDropOut_A	6866773	1	0	0
DetectedOut_A	6866773	2528	0	0
DetectedPulseOut_A	6866773	38	0	0
DisabledIdleSt_A	6866773	6089124	0	0
DisabledNoDetection_A	6866773	6091425	0	0
EnterDebounceSt_A	6866773	42	0	0
EnterDetectSt_A	6866773	39	0	0
EnterStableSt_A	6866773	38	0	0
PulseIsPulse_A	6866773	38	0	0
StayInStableSt	6866773	2470	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6866773	6212	0	0
gen_low_level_sva.LowLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	80	0	0
T5	6099	4	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T43	0	4	0	0
T60	0	2	0	0
T61	874	0	0	0
T62	607	0	0	0
T123	0	2	0	0
T156	0	4	0	0
T157	0	2	0	0
T221	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	35087	0	0
T5	6099	174	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	97	0	0
T38	0	91	0	0
T40	0	57	0	0
T43	0	166	0	0
T60	0	26	0	0
T61	874	0	0	0
T62	607	0	0	0
T74	0	2601	0	0
T123	0	90	0	0
T156	0	130	0	0
T221	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204639	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1466	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1	0	0
T127	4836	1	0	0
T161	841	0	0	0
T162	543	0	0	0
T163	3095	0	0	0
T164	17275	0	0	0
T165	15810	0	0	0
T166	10111	0	0	0
T167	740	0	0	0
T222	25921	0	0	0
T223	641	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	2528	0	0
T5	6099	79	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	151	0	0
T38	0	38	0	0
T40	0	47	0	0
T43	0	297	0	0
T60	0	17	0	0
T61	874	0	0	0
T62	607	0	0	0
T123	0	42	0	0
T156	0	81	0	0
T157	0	19	0	0
T221	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	38	0	0
T5	6099	2	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T123	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T221	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6089124	0	0
T1	2325	367	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	793	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6091425	0	0
T1	2325	369	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	805	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	42	0	0
T5	6099	2	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T74	0	1	0	0
T123	0	1	0	0
T156	0	2	0	0
T221	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	39	0	0
T5	6099	2	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T123	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T221	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	38	0	0
T5	6099	2	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T123	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T221	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	38	0	0
T5	6099	2	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	2	0	0
T60	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T123	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T221	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	2470	0	0
T5	6099	76	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T37	0	149	0	0
T38	0	36	0	0
T40	0	45	0	0
T43	0	294	0	0
T60	0	16	0	0
T61	874	0	0	0
T62	607	0	0	0
T123	0	41	0	0
T156	0	78	0	0
T157	0	18	0	0
T221	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6212	0	0
T1	2325	7	0	0
T2	26978	12	0	0
T3	6426	27	0	0
T4	408	0	0	0
T5	6099	8	0	0
T6	16271	12	0	0
T7	0	7	0	0
T12	521	5	0	0
T13	502	4	0	0
T14	494	8	0	0
T15	408	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	17	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T43	0	1	0	0
T61	874	0	0	0
T62	607	0	0	0
T95	0	2	0	0
T123	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T168	0	2	0	0
T169	0	1	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T7,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T7,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T74
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T7,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T20
0	1	Covered	T1,T7,T20
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T20
1	-	Covered	T1,T7,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T20
DetectSt	168	Covered	T1,T7,T20
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T7,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T20
DebounceSt->IdleSt	163	Covered	T198,T224,T87
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T7,T20
IdleSt->DebounceSt	148	Covered	T1,T7,T20
StableSt->IdleSt	206	Covered	T1,T7,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T20
0	1	Covered	T1,T7,T20
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T20
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T20
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T198,T224,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T20
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	142	0	0
CntIncr_A	6866773	4659	0	0
CntNoWrap_A	6866773	6204577	0	0
DetectStDropOut_A	6866773	0	0	0
DetectedOut_A	6866773	6258	0	0
DetectedPulseOut_A	6866773	68	0	0
DisabledIdleSt_A	6866773	6154673	0	0
DisabledNoDetection_A	6866773	6156964	0	0
EnterDebounceSt_A	6866773	74	0	0
EnterDetectSt_A	6866773	68	0	0
EnterStableSt_A	6866773	68	0	0
PulseIsPulse_A	6866773	68	0	0
StayInStableSt	6866773	6160	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	142	0	0
T1	2325	4	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	6	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	2	0	0
T39	0	4	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T60	0	2	0	0
T176	0	4	0	0
T186	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	4659	0	0
T1	2325	112	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	243	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	56	0	0
T39	0	134	0	0
T41	0	11	0	0
T44	0	70	0	0
T45	0	92	0	0
T60	0	26	0	0
T176	0	138	0	0
T186	0	170	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204577	0	0
T1	2325	718	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6258	0	0
T1	2325	141	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	252	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	100	0	0
T39	0	159	0	0
T41	0	43	0	0
T44	0	48	0	0
T45	0	38	0	0
T60	0	17	0	0
T176	0	114	0	0
T186	0	262	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	68	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T60	0	1	0	0
T176	0	2	0	0
T186	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6154673	0	0
T1	2325	367	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6156964	0	0
T1	2325	369	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	74	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T60	0	1	0	0
T176	0	2	0	0
T186	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	68	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T60	0	1	0	0
T176	0	2	0	0
T186	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	68	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T60	0	1	0	0
T176	0	2	0	0
T186	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	68	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T60	0	1	0	0
T176	0	2	0	0
T186	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6160	0	0
T1	2325	138	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	248	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	99	0	0
T39	0	156	0	0
T41	0	42	0	0
T44	0	47	0	0
T45	0	36	0	0
T60	0	16	0	0
T176	0	111	0	0
T186	0	259	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	37	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T20	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T171	0	1	0	0
T176	0	1	0	0
T186	0	1	0	0
T225	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T74
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T38,T39
0	1	Covered	T187
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T38,T39
0	1	Covered	T39,T196,T95
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T38,T39
1	-	Covered	T39,T196,T95

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T38,T39
DetectSt	168	Covered	T1,T38,T39
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T38,T39
DebounceSt->IdleSt	163	Covered	T87
DetectSt->IdleSt	186	Covered	T187
DetectSt->StableSt	191	Covered	T1,T38,T39
IdleSt->DebounceSt	148	Covered	T1,T38,T39
StableSt->IdleSt	206	Covered	T1,T39,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T38,T39
0	1	Covered	T1,T38,T39
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T38,T39
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T38,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T187
DetectSt	-	-	-	-	0	1	-	Covered	T1,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T60,T196
StableSt	-	-	-	-	-	-	0	Covered	T1,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	61	0	0
CntIncr_A	6866773	65452	0	0
CntNoWrap_A	6866773	6204658	0	0
DetectStDropOut_A	6866773	1	0	0
DetectedOut_A	6866773	125012	0	0
DetectedPulseOut_A	6866773	29	0	0
DisabledIdleSt_A	6866773	5738799	0	0
DisabledNoDetection_A	6866773	5741100	0	0
EnterDebounceSt_A	6866773	31	0	0
EnterDetectSt_A	6866773	30	0	0
EnterStableSt_A	6866773	29	0	0
PulseIsPulse_A	6866773	29	0	0
StayInStableSt	6866773	124964	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6866773	6135	0	0
gen_low_level_sva.LowLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	61	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T60	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0
T171	0	2	0	0
T187	0	2	0	0
T198	0	2	0	0
T226	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	65452	0	0
T1	2325	19	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	91	0	0
T39	0	67	0	0
T60	0	26	0	0
T156	0	65	0	0
T157	0	80	0	0
T171	0	95	0	0
T187	0	58	0	0
T198	0	50	0	0
T226	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204658	0	0
T1	2325	720	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1	0	0
T104	5571	0	0	0
T171	874	0	0	0
T187	9967	1	0	0
T195	576	0	0	0
T227	496	0	0	0
T228	428	0	0	0
T229	4089	0	0	0
T230	33406	0	0	0
T231	536	0	0	0
T232	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	125012	0	0
T1	2325	125	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	38	0	0
T39	0	104	0	0
T60	0	18	0	0
T156	0	38	0	0
T157	0	43	0	0
T171	0	39	0	0
T198	0	222	0	0
T226	0	44	0	0
T233	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	29	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T171	0	1	0	0
T198	0	1	0	0
T226	0	1	0	0
T233	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5738799	0	0
T1	2325	454	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5741100	0	0
T1	2325	456	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	31	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T171	0	1	0	0
T187	0	1	0	0
T198	0	1	0	0
T226	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	30	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T171	0	1	0	0
T187	0	1	0	0
T198	0	1	0	0
T226	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	29	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T171	0	1	0	0
T198	0	1	0	0
T226	0	1	0	0
T233	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	29	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T60	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T171	0	1	0	0
T198	0	1	0	0
T226	0	1	0	0
T233	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	124964	0	0
T1	2325	123	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T38	0	36	0	0
T39	0	103	0	0
T60	0	17	0	0
T156	0	36	0	0
T157	0	41	0	0
T171	0	37	0	0
T198	0	220	0	0
T226	0	42	0	0
T233	0	47	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6135	0	0
T1	2325	8	0	0
T2	26978	12	0	0
T3	6426	29	0	0
T4	408	0	0	0
T5	6099	7	0	0
T6	16271	12	0	0
T7	0	9	0	0
T8	0	1	0	0
T12	521	6	0	0
T13	502	5	0	0
T14	494	5	0	0
T15	408	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	9	0	0
T39	944	1	0	0
T95	0	1	0	0
T97	632	0	0	0
T99	4666	0	0	0
T120	1417	0	0	0
T155	0	1	0	0
T175	0	2	0	0
T196	0	2	0	0
T215	0	1	0	0
T234	0	1	0	0
T235	6212	0	0	0
T236	809	0	0	0
T237	4615	0	0	0
T238	525	0	0	0
T239	729	0	0	0
T240	425	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T11,T20,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T11,T20,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T11,T20,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T20,T45
1	0	Covered	T1,T4,T2
1	1	Covered	T11,T20,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T20,T45
0	1	Covered	T43,T176,T187
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T20,T45
0	1	Covered	T45,T37,T43
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T20,T45
1	-	Covered	T45,T37,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T20,T45
DetectSt	168	Covered	T11,T20,T45
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T11,T20,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T20,T45
DebounceSt->IdleSt	163	Covered	T42,T176,T168
DetectSt->IdleSt	186	Covered	T43,T176,T187
DetectSt->StableSt	191	Covered	T11,T20,T45
IdleSt->DebounceSt	148	Covered	T11,T20,T45
StableSt->IdleSt	206	Covered	T20,T45,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T20,T45
0	1	Covered	T11,T20,T45
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T20,T45
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T20,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T20,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T176,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T20,T45
DetectSt	-	-	-	-	1	-	-	Covered	T43,T176,T187
DetectSt	-	-	-	-	0	1	-	Covered	T11,T20,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T37,T43
StableSt	-	-	-	-	-	-	0	Covered	T11,T20,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	132	0	0
CntIncr_A	6866773	289101	0	0
CntNoWrap_A	6866773	6204587	0	0
DetectStDropOut_A	6866773	6	0	0
DetectedOut_A	6866773	110487	0	0
DetectedPulseOut_A	6866773	57	0	0
DisabledIdleSt_A	6866773	5349390	0	0
DisabledNoDetection_A	6866773	5351686	0	0
EnterDebounceSt_A	6866773	69	0	0
EnterDetectSt_A	6866773	63	0	0
EnterStableSt_A	6866773	57	0	0
PulseIsPulse_A	6866773	57	0	0
StayInStableSt	6866773	110406	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	132	0	0
T11	499	2	0	0
T20	0	2	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	6	0	0
T45	0	2	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T176	0	5	0	0
T177	0	2	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	289101	0	0
T11	499	22	0	0
T20	0	56	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	97	0	0
T38	0	91	0	0
T41	0	11	0	0
T42	0	64587	0	0
T43	0	249	0	0
T45	0	92	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T176	0	207	0	0
T177	0	12	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204587	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6	0	0
T43	12568	1	0	0
T51	15104	0	0	0
T52	786	0	0	0
T84	1338	0	0	0
T96	760	0	0	0
T98	20494	0	0	0
T129	422	0	0	0
T130	424	0	0	0
T131	402	0	0	0
T132	527	0	0	0
T176	0	1	0	0
T187	0	1	0	0
T217	0	1	0	0
T245	0	1	0	0
T246	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	110487	0	0
T11	499	67	0	0
T20	0	199	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	154	0	0
T38	0	351	0	0
T41	0	114	0	0
T43	0	245	0	0
T45	0	88	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T123	0	17	0	0
T176	0	40	0	0
T177	0	74	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	57	0	0
T11	499	1	0	0
T20	0	1	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T123	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5349390	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5351686	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	69	0	0
T11	499	1	0	0
T20	0	1	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T45	0	1	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T176	0	3	0	0
T177	0	1	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	63	0	0
T11	499	1	0	0
T20	0	1	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	3	0	0
T45	0	1	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T123	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	57	0	0
T11	499	1	0	0
T20	0	1	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T123	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	57	0	0
T11	499	1	0	0
T20	0	1	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T123	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	110406	0	0
T11	499	65	0	0
T20	0	197	0	0
T25	468	0	0	0
T26	14290	0	0	0
T37	0	153	0	0
T38	0	349	0	0
T41	0	112	0	0
T43	0	242	0	0
T45	0	87	0	0
T46	1689	0	0	0
T72	496	0	0	0
T77	508	0	0	0
T123	0	16	0	0
T176	0	39	0	0
T177	0	72	0	0
T241	421	0	0	0
T242	401	0	0	0
T243	421	0	0	0
T244	513	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	32	0	0
T37	986	1	0	0
T41	324659	0	0	0
T42	389074	0	0	0
T43	0	1	0	0
T45	721	1	0	0
T123	0	1	0	0
T159	0	2	0	0
T176	0	1	0	0
T182	0	1	0	0
T199	0	1	0	0
T200	858	0	0	0
T201	441	0	0	0
T224	0	1	0	0
T247	0	1	0	0
T248	13974	0	0	0
T249	521	0	0	0
T250	1965	0	0	0
T251	524	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T10,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T1,T10,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T10,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T55
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T10,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T37
0	1	Covered	T183
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T37
0	1	Covered	T1,T10,T224
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T37
1	-	Covered	T1,T10,T224

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T37
DetectSt	168	Covered	T1,T10,T37
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T1,T10,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T37
DebounceSt->IdleSt	163	Covered	T87,T215
DetectSt->IdleSt	186	Covered	T183
DetectSt->StableSt	191	Covered	T1,T10,T37
IdleSt->DebounceSt	148	Covered	T1,T10,T37
StableSt->IdleSt	206	Covered	T1,T10,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T37
0	1	Covered	T1,T10,T37
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T37
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T215
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T37
DetectSt	-	-	-	-	1	-	-	Covered	T183
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T60
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	84	0	0
CntIncr_A	6866773	2151	0	0
CntNoWrap_A	6866773	6204635	0	0
DetectStDropOut_A	6866773	1	0	0
DetectedOut_A	6866773	3546	0	0
DetectedPulseOut_A	6866773	40	0	0
DisabledIdleSt_A	6866773	6187451	0	0
DisabledNoDetection_A	6866773	6189747	0	0
EnterDebounceSt_A	6866773	43	0	0
EnterDetectSt_A	6866773	41	0	0
EnterStableSt_A	6866773	40	0	0
PulseIsPulse_A	6866773	40	0	0
StayInStableSt	6866773	3484	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6866773	6689	0	0
gen_low_level_sva.LowLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	84	0	0
T1	2325	4	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	2	0	0
T60	0	2	0	0
T182	0	2	0	0
T187	0	4	0	0
T199	0	2	0	0
T224	0	2	0	0
T226	0	2	0	0
T233	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	2151	0	0
T1	2325	75	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	87	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	97	0	0
T60	0	26	0	0
T182	0	79	0	0
T187	0	79	0	0
T199	0	23	0	0
T224	0	91	0	0
T226	0	31	0	0
T233	0	49	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6204635	0	0
T1	2325	718	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1	0	0
T183	19597	1	0	0
T206	212696	0	0	0
T207	493	0	0	0
T208	15928	0	0	0
T209	11273	0	0	0
T210	497	0	0	0
T211	3598	0	0	0
T212	5416	0	0	0
T213	2318	0	0	0
T214	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	3546	0	0
T1	2325	160	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	40	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	41	0	0
T60	0	18	0	0
T182	0	439	0	0
T187	0	142	0	0
T199	0	45	0	0
T224	0	44	0	0
T226	0	1	0	0
T233	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	40	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	1	0	0
T60	0	1	0	0
T182	0	1	0	0
T187	0	2	0	0
T199	0	1	0	0
T224	0	1	0	0
T226	0	1	0	0
T233	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6187451	0	0
T1	2325	99	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6189747	0	0
T1	2325	100	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	43	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	1	0	0
T60	0	1	0	0
T182	0	1	0	0
T187	0	2	0	0
T199	0	1	0	0
T224	0	1	0	0
T226	0	1	0	0
T233	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	41	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	1	0	0
T60	0	1	0	0
T182	0	1	0	0
T187	0	2	0	0
T199	0	1	0	0
T224	0	1	0	0
T226	0	1	0	0
T233	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	40	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	1	0	0
T60	0	1	0	0
T182	0	1	0	0
T187	0	2	0	0
T199	0	1	0	0
T224	0	1	0	0
T226	0	1	0	0
T233	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	40	0	0
T1	2325	2	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	1	0	0
T60	0	1	0	0
T182	0	1	0	0
T187	0	2	0	0
T199	0	1	0	0
T224	0	1	0	0
T226	0	1	0	0
T233	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	3484	0	0
T1	2325	157	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	39	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T37	0	39	0	0
T60	0	17	0	0
T173	0	97	0	0
T182	0	437	0	0
T187	0	138	0	0
T199	0	43	0	0
T224	0	43	0	0
T233	0	46	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6689	0	0
T1	2325	9	0	0
T2	26978	11	0	0
T3	6426	23	0	0
T4	408	1	0	0
T5	6099	5	0	0
T6	16271	13	0	0
T12	521	4	0	0
T13	502	5	0	0
T14	494	5	0	0
T15	408	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	17	0	0
T1	2325	1	0	0
T2	26978	0	0	0
T3	6426	0	0	0
T4	408	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T10	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T159	0	1	0	0
T169	0	1	0	0
T173	0	1	0	0
T183	0	1	0	0
T220	0	1	0	0
T224	0	1	0	0
T226	0	1	0	0
T252	0	1	0	0