Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T9,T26
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T25

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T26
1	0	Covered	T9,T26,T36
1	1	Covered	T3,T9,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T25
0	1	Covered	T81,T83,T89
1	0	Covered	T81,T83,T253

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T25
0	1	Covered	T3,T9,T26
1	0	Covered	T254,T87,T255

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T25
1	-	Covered	T3,T9,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T25
DetectSt	168	Covered	T3,T9,T25
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T3,T9,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T25
DebounceSt->IdleSt	163	Covered	T110,T256,T60
DetectSt->IdleSt	186	Covered	T81,T83,T253
DetectSt->StableSt	191	Covered	T3,T9,T25
IdleSt->DebounceSt	148	Covered	T3,T9,T25
StableSt->IdleSt	206	Covered	T3,T9,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T25
0	1	Covered	T3,T9,T25
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T25
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T25
IdleSt	0	-	-	-	-	-	-	Covered	T3,T9,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T110,T256,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T25
DetectSt	-	-	-	-	1	-	-	Covered	T81,T83,T253
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T25
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T25
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T26
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	2920	0	0
CntIncr_A	6866773	95846	0	0
CntNoWrap_A	6866773	6201799	0	0
DetectStDropOut_A	6866773	323	0	0
DetectedOut_A	6866773	85211	0	0
DetectedPulseOut_A	6866773	1034	0	0
DisabledIdleSt_A	6866773	5746843	0	0
DisabledNoDetection_A	6866773	5748984	0	0
EnterDebounceSt_A	6866773	1478	0	0
EnterDetectSt_A	6866773	1443	0	0
EnterStableSt_A	6866773	1034	0	0
PulseIsPulse_A	6866773	1034	0	0
StayInStableSt	6866773	84057	0	0
gen_high_event_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	906	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	2920	0	0
T3	6426	28	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	22	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	2	0	0
T26	0	52	0	0
T36	0	56	0	0
T56	0	10	0	0
T61	874	0	0	0
T79	0	64	0	0
T80	0	46	0	0
T81	0	30	0	0
T82	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	95846	0	0
T3	6426	672	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	759	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	21	0	0
T26	0	1794	0	0
T36	0	1792	0	0
T56	0	1225	0	0
T61	874	0	0	0
T79	0	7200	0	0
T80	0	1679	0	0
T81	0	1132	0	0
T82	0	671	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6201799	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	5997	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	323	0	0
T20	6818	0	0	0
T24	815	0	0	0
T60	0	1	0	0
T65	1051	0	0	0
T66	857	0	0	0
T81	8931	13	0	0
T82	20808	0	0	0
T83	0	9	0	0
T89	0	22	0	0
T99	0	28	0	0
T100	0	11	0	0
T104	0	8	0	0
T106	0	15	0	0
T191	524	0	0	0
T192	422	0	0	0
T193	419	0	0	0
T257	0	16	0	0
T258	0	25	0	0
T259	8444	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	85211	0	0
T3	6426	1313	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	378	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	42	0	0
T26	0	1753	0	0
T36	0	3103	0	0
T56	0	1316	0	0
T61	874	0	0	0
T79	0	2987	0	0
T80	0	2481	0	0
T82	0	2065	0	0
T150	0	948	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1034	0	0
T3	6426	14	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	11	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	1	0	0
T26	0	26	0	0
T36	0	28	0	0
T56	0	5	0	0
T61	874	0	0	0
T79	0	32	0	0
T80	0	23	0	0
T82	0	11	0	0
T150	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5746843	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	2015	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5748984	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	2015	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1478	0	0
T3	6426	14	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	11	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	1	0	0
T26	0	26	0	0
T36	0	28	0	0
T56	0	5	0	0
T61	874	0	0	0
T79	0	32	0	0
T80	0	23	0	0
T81	0	15	0	0
T82	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1443	0	0
T3	6426	14	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	11	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	1	0	0
T26	0	26	0	0
T36	0	28	0	0
T56	0	5	0	0
T61	874	0	0	0
T79	0	32	0	0
T80	0	23	0	0
T81	0	15	0	0
T82	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1034	0	0
T3	6426	14	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	11	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	1	0	0
T26	0	26	0	0
T36	0	28	0	0
T56	0	5	0	0
T61	874	0	0	0
T79	0	32	0	0
T80	0	23	0	0
T82	0	11	0	0
T150	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1034	0	0
T3	6426	14	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	11	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	1	0	0
T26	0	26	0	0
T36	0	28	0	0
T56	0	5	0	0
T61	874	0	0	0
T79	0	32	0	0
T80	0	23	0	0
T82	0	11	0	0
T150	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	84057	0	0
T3	6426	1299	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	366	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T25	0	40	0	0
T26	0	1724	0	0
T36	0	3068	0	0
T56	0	1311	0	0
T61	874	0	0	0
T79	0	2952	0	0
T80	0	2458	0	0
T82	0	2050	0	0
T150	0	928	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	906	0	0
T3	6426	14	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	10	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	23	0	0
T36	0	21	0	0
T56	0	5	0	0
T61	874	0	0	0
T79	0	29	0	0
T80	0	23	0	0
T82	0	7	0	0
T150	0	12	0	0
T260	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T3,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T6,T35,T86
1	0	Covered	T60,T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T5
1	-	Covered	T2,T3,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T5
DetectSt	168	Covered	T2,T3,T5
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T3,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T5
DebounceSt->IdleSt	163	Covered	T2,T25,T46
DetectSt->IdleSt	186	Covered	T6,T35,T86
DetectSt->StableSt	191	Covered	T2,T3,T5
IdleSt->DebounceSt	148	Covered	T2,T3,T5
StableSt->IdleSt	206	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T5
0	1	Covered	T2,T3,T5
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T25,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T5
DetectSt	-	-	-	-	1	-	-	Covered	T6,T35,T86
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T5
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T5
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T5
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	973	0	0
CntIncr_A	6866773	50280	0	0
CntNoWrap_A	6866773	6203746	0	0
DetectStDropOut_A	6866773	66	0	0
DetectedOut_A	6866773	16945	0	0
DetectedPulseOut_A	6866773	379	0	0
DisabledIdleSt_A	6866773	5794222	0	0
DisabledNoDetection_A	6866773	5795822	0	0
EnterDebounceSt_A	6866773	527	0	0
EnterDetectSt_A	6866773	448	0	0
EnterStableSt_A	6866773	379	0	0
PulseIsPulse_A	6866773	379	0	0
StayInStableSt	6866773	16524	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	335	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	973	0	0
T2	26978	21	0	0
T3	6426	8	0	0
T5	6099	2	0	0
T6	16271	6	0	0
T7	2821	0	0	0
T8	1940	2	0	0
T9	0	2	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T25	0	1	0	0
T26	0	6	0	0
T46	0	1	0	0
T47	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	50280	0	0
T2	26978	846	0	0
T3	6426	228	0	0
T5	6099	25	0	0
T6	16271	184	0	0
T7	2821	0	0	0
T8	1940	25	0	0
T9	0	80	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T25	0	20	0	0
T26	0	171	0	0
T46	0	20	0	0
T47	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6203746	0	0
T1	2325	722	0	0
T2	26978	26484	0	0
T3	6426	6017	0	0
T4	408	7	0	0
T5	6099	1468	0	0
T6	16271	15820	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	66	0	0
T6	16271	3	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T35	0	3	0	0
T61	874	0	0	0
T62	607	0	0	0
T86	0	8	0	0
T98	0	3	0	0
T101	0	1	0	0
T102	0	2	0	0
T103	0	3	0	0
T105	0	1	0	0
T107	0	4	0	0
T108	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	16945	0	0
T2	26978	772	0	0
T3	6426	242	0	0
T5	6099	4	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	3	0	0
T9	0	62	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T26	0	175	0	0
T31	0	393	0	0
T36	0	395	0	0
T79	0	208	0	0
T119	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	379	0	0
T2	26978	10	0	0
T3	6426	4	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	1	0	0
T9	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T26	0	3	0	0
T31	0	6	0	0
T36	0	6	0	0
T79	0	3	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5794222	0	0
T1	2325	722	0	0
T2	26978	22160	0	0
T3	6426	4712	0	0
T4	408	7	0	0
T5	6099	1393	0	0
T6	16271	14102	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5795822	0	0
T1	2325	725	0	0
T2	26978	22160	0	0
T3	6426	4713	0	0
T4	408	8	0	0
T5	6099	1406	0	0
T6	16271	14102	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	527	0	0
T2	26978	11	0	0
T3	6426	4	0	0
T5	6099	1	0	0
T6	16271	3	0	0
T7	2821	0	0	0
T8	1940	1	0	0
T9	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T25	0	1	0	0
T26	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	448	0	0
T2	26978	10	0	0
T3	6426	4	0	0
T5	6099	1	0	0
T6	16271	3	0	0
T7	2821	0	0	0
T8	1940	1	0	0
T9	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T26	0	3	0	0
T31	0	6	0	0
T36	0	6	0	0
T79	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	379	0	0
T2	26978	10	0	0
T3	6426	4	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	1	0	0
T9	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T26	0	3	0	0
T31	0	6	0	0
T36	0	6	0	0
T79	0	3	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	379	0	0
T2	26978	10	0	0
T3	6426	4	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	1	0	0
T9	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T26	0	3	0	0
T31	0	6	0	0
T36	0	6	0	0
T79	0	3	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	16524	0	0
T2	26978	760	0	0
T3	6426	238	0	0
T5	6099	3	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	2	0	0
T9	0	61	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T26	0	172	0	0
T31	0	387	0	0
T36	0	384	0	0
T79	0	202	0	0
T119	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	335	0	0
T2	26978	8	0	0
T3	6426	4	0	0
T5	6099	1	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	1	0	0
T9	0	1	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T26	0	3	0	0
T31	0	6	0	0
T34	0	3	0	0
T36	0	1	0	0
T119	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T9,T26
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T26
1	0	Covered	T3,T9,T26
1	1	Covered	T3,T9,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T26
0	1	Covered	T3,T82,T83
1	0	Covered	T3,T82,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T26,T36
0	1	Covered	T9,T26,T36
1	0	Covered	T89,T60,T261

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T26,T36
1	-	Covered	T9,T26,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T26
DetectSt	168	Covered	T3,T9,T26
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T9,T26,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T26
DebounceSt->IdleSt	163	Covered	T110,T256,T60
DetectSt->IdleSt	186	Covered	T3,T82,T83
DetectSt->StableSt	191	Covered	T9,T26,T36
IdleSt->DebounceSt	148	Covered	T3,T9,T26
StableSt->IdleSt	206	Covered	T9,T26,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T26
0	1	Covered	T3,T9,T26
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T26
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T26
IdleSt	0	-	-	-	-	-	-	Covered	T3,T9,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T110,T256,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T26
DetectSt	-	-	-	-	1	-	-	Covered	T3,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T9,T26,T36
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T26
StableSt	-	-	-	-	-	-	1	Covered	T9,T26,T36
StableSt	-	-	-	-	-	-	0	Covered	T9,T26,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	3149	0	0
CntIncr_A	6866773	109494	0	0
CntNoWrap_A	6866773	6201570	0	0
DetectStDropOut_A	6866773	298	0	0
DetectedOut_A	6866773	91660	0	0
DetectedPulseOut_A	6866773	1037	0	0
DisabledIdleSt_A	6866773	5745518	0	0
DisabledNoDetection_A	6866773	5747673	0	0
EnterDebounceSt_A	6866773	1597	0	0
EnterDetectSt_A	6866773	1553	0	0
EnterStableSt_A	6866773	1037	0	0
PulseIsPulse_A	6866773	1037	0	0
StayInStableSt	6866773	90518	0	0
gen_high_event_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	920	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	3149	0	0
T3	6426	50	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	54	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	6	0	0
T36	0	44	0	0
T56	0	46	0	0
T61	874	0	0	0
T79	0	50	0	0
T80	0	46	0	0
T81	0	8	0	0
T82	0	56	0	0
T83	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	109494	0	0
T3	6426	1261	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	1674	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	144	0	0
T36	0	1364	0	0
T56	0	5934	0	0
T61	874	0	0	0
T79	0	5250	0	0
T80	0	2001	0	0
T81	0	228	0	0
T82	0	3310	0	0
T83	0	879	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6201570	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	5975	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	298	0	0
T3	6426	17	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T60	0	1	0	0
T61	874	0	0	0
T82	0	20	0	0
T83	0	10	0	0
T89	0	17	0	0
T99	0	26	0	0
T104	0	12	0	0
T150	0	17	0	0
T235	0	5	0	0
T262	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	91660	0	0
T9	15043	2661	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	97	0	0
T36	0	1547	0	0
T56	0	6579	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	2927	0	0
T80	0	2159	0	0
T81	0	560	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	1889	0	0
T260	0	1837	0	0
T263	0	1650	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1037	0	0
T9	15043	27	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	3	0	0
T36	0	22	0	0
T56	0	23	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	25	0	0
T80	0	23	0	0
T81	0	4	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	23	0	0
T260	0	26	0	0
T263	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5745518	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	3313	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5747673	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	3313	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1597	0	0
T3	6426	25	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	27	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	3	0	0
T36	0	22	0	0
T56	0	23	0	0
T61	874	0	0	0
T79	0	25	0	0
T80	0	23	0	0
T81	0	4	0	0
T82	0	28	0	0
T83	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1553	0	0
T3	6426	25	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	27	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	3	0	0
T36	0	22	0	0
T56	0	23	0	0
T61	874	0	0	0
T79	0	25	0	0
T80	0	23	0	0
T81	0	4	0	0
T82	0	28	0	0
T83	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1037	0	0
T9	15043	27	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	3	0	0
T36	0	22	0	0
T56	0	23	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	25	0	0
T80	0	23	0	0
T81	0	4	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	23	0	0
T260	0	26	0	0
T263	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1037	0	0
T9	15043	27	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	3	0	0
T36	0	22	0	0
T56	0	23	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	25	0	0
T80	0	23	0	0
T81	0	4	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	23	0	0
T260	0	26	0	0
T263	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	90518	0	0
T9	15043	2631	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	94	0	0
T36	0	1521	0	0
T56	0	6552	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	2900	0	0
T80	0	2136	0	0
T81	0	555	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	1866	0	0
T260	0	1807	0	0
T263	0	1625	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	920	0	0
T9	15043	24	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	3	0	0
T36	0	18	0	0
T56	0	19	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	23	0	0
T80	0	23	0	0
T81	0	3	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	23	0	0
T260	0	22	0	0
T263	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T6,T86,T113
1	0	Covered	T60,T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T36
0	1	Covered	T2,T9,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T36
1	-	Covered	T2,T9,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T9
DetectSt	168	Covered	T2,T6,T9
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T9,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T9
DebounceSt->IdleSt	163	Covered	T6,T80,T56
DetectSt->IdleSt	186	Covered	T6,T86,T113
DetectSt->StableSt	191	Covered	T2,T9,T36
IdleSt->DebounceSt	148	Covered	T2,T6,T9
StableSt->IdleSt	206	Covered	T2,T9,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T9
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T80,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T6,T86,T113
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T36
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T9
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	832	0	0
CntIncr_A	6866773	47709	0	0
CntNoWrap_A	6866773	6203887	0	0
DetectStDropOut_A	6866773	33	0	0
DetectedOut_A	6866773	15064	0	0
DetectedPulseOut_A	6866773	358	0	0
DisabledIdleSt_A	6866773	5788048	0	0
DisabledNoDetection_A	6866773	5789713	0	0
EnterDebounceSt_A	6866773	438	0	0
EnterDetectSt_A	6866773	394	0	0
EnterStableSt_A	6866773	358	0	0
PulseIsPulse_A	6866773	358	0	0
StayInStableSt	6866773	14675	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	325	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	832	0	0
T2	26978	8	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	13	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	6	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	16	0	0
T34	0	14	0	0
T35	0	12	0	0
T36	0	6	0	0
T56	0	9	0	0
T80	0	7	0	0
T119	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	47709	0	0
T2	26978	600	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	408	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	279	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	1600	0	0
T34	0	2331	0	0
T35	0	618	0	0
T36	0	213	0	0
T56	0	1305	0	0
T80	0	233	0	0
T119	0	283	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6203887	0	0
T1	2325	722	0	0
T2	26978	26497	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15813	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	33	0	0
T6	16271	6	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T51	0	2	0	0
T61	874	0	0	0
T62	607	0	0	0
T86	0	1	0	0
T113	0	10	0	0
T264	0	2	0	0
T265	0	2	0	0
T266	0	2	0	0
T267	0	2	0	0
T268	0	1	0	0
T269	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	15064	0	0
T2	26978	17	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	148	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	38	0	0
T34	0	123	0	0
T35	0	200	0	0
T36	0	197	0	0
T56	0	251	0	0
T74	0	42	0	0
T80	0	250	0	0
T119	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	358	0	0
T2	26978	4	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	8	0	0
T34	0	7	0	0
T35	0	6	0	0
T36	0	3	0	0
T56	0	4	0	0
T74	0	1	0	0
T80	0	3	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5788048	0	0
T1	2325	722	0	0
T2	26978	22160	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	14102	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5789713	0	0
T1	2325	725	0	0
T2	26978	22160	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	14102	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	438	0	0
T2	26978	4	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	7	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	8	0	0
T34	0	7	0	0
T35	0	6	0	0
T36	0	3	0	0
T56	0	5	0	0
T80	0	4	0	0
T119	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	394	0	0
T2	26978	4	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	6	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	8	0	0
T34	0	7	0	0
T35	0	6	0	0
T36	0	3	0	0
T56	0	4	0	0
T80	0	3	0	0
T119	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	358	0	0
T2	26978	4	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	8	0	0
T34	0	7	0	0
T35	0	6	0	0
T36	0	3	0	0
T56	0	4	0	0
T74	0	1	0	0
T80	0	3	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	358	0	0
T2	26978	4	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	8	0	0
T34	0	7	0	0
T35	0	6	0	0
T36	0	3	0	0
T56	0	4	0	0
T74	0	1	0	0
T80	0	3	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	14675	0	0
T2	26978	13	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	145	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	30	0	0
T34	0	116	0	0
T35	0	194	0	0
T36	0	193	0	0
T56	0	243	0	0
T74	0	41	0	0
T80	0	247	0	0
T119	0	9	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	325	0	0
T2	26978	4	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	3	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	8	0	0
T34	0	7	0	0
T35	0	6	0	0
T36	0	2	0	0
T74	0	1	0	0
T80	0	3	0	0
T119	0	1	0	0
T151	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T9,T26
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T26
1	0	Covered	T3,T9,T26
1	1	Covered	T3,T9,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T26
0	1	Covered	T3,T81,T83
1	0	Covered	T3,T81,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T26,T36
0	1	Covered	T9,T26,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T26,T36
1	-	Covered	T9,T26,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T26
DetectSt	168	Covered	T3,T9,T26
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T9,T26,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T26
DebounceSt->IdleSt	163	Covered	T110,T256,T60
DetectSt->IdleSt	186	Covered	T3,T81,T83
DetectSt->StableSt	191	Covered	T9,T26,T36
IdleSt->DebounceSt	148	Covered	T3,T9,T26
StableSt->IdleSt	206	Covered	T9,T26,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T26
0	1	Covered	T3,T9,T26
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T26
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T26
IdleSt	0	-	-	-	-	-	-	Covered	T3,T9,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T110,T256,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T26
DetectSt	-	-	-	-	1	-	-	Covered	T3,T81,T83
DetectSt	-	-	-	-	0	1	-	Covered	T9,T26,T36
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T26
StableSt	-	-	-	-	-	-	1	Covered	T9,T26,T36
StableSt	-	-	-	-	-	-	0	Covered	T9,T26,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	2828	0	0
CntIncr_A	6866773	96031	0	0
CntNoWrap_A	6866773	6201891	0	0
DetectStDropOut_A	6866773	301	0	0
DetectedOut_A	6866773	73792	0	0
DetectedPulseOut_A	6866773	851	0	0
DisabledIdleSt_A	6866773	5756966	0	0
DisabledNoDetection_A	6866773	5759140	0	0
EnterDebounceSt_A	6866773	1443	0	0
EnterDetectSt_A	6866773	1387	0	0
EnterStableSt_A	6866773	851	0	0
PulseIsPulse_A	6866773	851	0	0
StayInStableSt	6866773	72855	0	0
gen_high_event_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	764	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	2828	0	0
T3	6426	48	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	22	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	14	0	0
T36	0	14	0	0
T56	0	24	0	0
T61	874	0	0	0
T79	0	12	0	0
T80	0	20	0	0
T81	0	46	0	0
T82	0	26	0	0
T83	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	96031	0	0
T3	6426	1211	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	803	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	343	0	0
T36	0	518	0	0
T56	0	2964	0	0
T61	874	0	0	0
T79	0	1212	0	0
T80	0	680	0	0
T81	0	1757	0	0
T82	0	832	0	0
T83	0	761	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6201891	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	5977	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	301	0	0
T3	6426	10	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T60	0	1	0	0
T61	874	0	0	0
T81	0	19	0	0
T83	0	9	0	0
T89	0	5	0	0
T99	0	13	0	0
T100	0	17	0	0
T150	0	3	0	0
T254	0	12	0	0
T270	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	73792	0	0
T9	15043	334	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	340	0	0
T36	0	177	0	0
T56	0	5025	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	254	0	0
T80	0	489	0	0
T82	0	2275	0	0
T110	0	106	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	661	0	0
T260	0	1270	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	851	0	0
T9	15043	11	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	7	0	0
T36	0	7	0	0
T56	0	12	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	6	0	0
T80	0	10	0	0
T82	0	13	0	0
T110	0	5	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	13	0	0
T260	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5756966	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	3314	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5759140	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	3314	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1443	0	0
T3	6426	24	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	11	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	7	0	0
T36	0	7	0	0
T56	0	12	0	0
T61	874	0	0	0
T79	0	6	0	0
T80	0	10	0	0
T81	0	23	0	0
T82	0	13	0	0
T83	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1387	0	0
T3	6426	24	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	11	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	7	0	0
T36	0	7	0	0
T56	0	12	0	0
T61	874	0	0	0
T79	0	6	0	0
T80	0	10	0	0
T81	0	23	0	0
T82	0	13	0	0
T83	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	851	0	0
T9	15043	11	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	7	0	0
T36	0	7	0	0
T56	0	12	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	6	0	0
T80	0	10	0	0
T82	0	13	0	0
T110	0	5	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	13	0	0
T260	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	851	0	0
T9	15043	11	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	7	0	0
T36	0	7	0	0
T56	0	12	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	6	0	0
T80	0	10	0	0
T82	0	13	0	0
T110	0	5	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	13	0	0
T260	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	72855	0	0
T9	15043	322	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	333	0	0
T36	0	170	0	0
T56	0	5013	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	248	0	0
T80	0	479	0	0
T82	0	2259	0	0
T110	0	101	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	648	0	0
T260	0	1254	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	764	0	0
T9	15043	10	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	7	0	0
T36	0	7	0	0
T56	0	12	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	6	0	0
T80	0	10	0	0
T82	0	10	0	0
T110	0	5	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	13	0	0
T260	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T9,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T6,T9,T56

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T6,T9,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T9,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T56
0	1	Covered	T98,T271,T272
1	0	Covered	T60,T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T56
0	1	Covered	T6,T9,T56
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T56
1	-	Covered	T6,T9,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T56
DetectSt	168	Covered	T6,T9,T56
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T6,T9,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T56
DebounceSt->IdleSt	163	Covered	T264,T273,T60
DetectSt->IdleSt	186	Covered	T43,T98,T271
DetectSt->StableSt	191	Covered	T6,T9,T56
IdleSt->DebounceSt	148	Covered	T6,T9,T56
StableSt->IdleSt	206	Covered	T6,T9,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T56
0	1	Covered	T6,T9,T56
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T56
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T56
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T264,T273,T103
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T56
DetectSt	-	-	-	-	1	-	-	Covered	T98,T271,T272
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T56
DetectSt	-	-	-	-	0	0	-	Covered	T6,T9,T56
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T56
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	747	0	0
CntIncr_A	6866773	42205	0	0
CntNoWrap_A	6866773	6203972	0	0
DetectStDropOut_A	6866773	52	0	0
DetectedOut_A	6866773	14430	0	0
DetectedPulseOut_A	6866773	301	0	0
DisabledIdleSt_A	6866773	5807249	0	0
DisabledNoDetection_A	6866773	5808938	0	0
EnterDebounceSt_A	6866773	390	0	0
EnterDetectSt_A	6866773	358	0	0
EnterStableSt_A	6866773	301	0	0
PulseIsPulse_A	6866773	301	0	0
StayInStableSt	6866773	14109	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	275	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	747	0	0
T6	16271	4	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	2	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	8	0	0
T34	0	14	0	0
T35	0	2	0	0
T56	0	10	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	6	0	0
T86	0	8	0	0
T119	0	4	0	0
T151	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	42205	0	0
T6	16271	100	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	79	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	448	0	0
T34	0	1904	0	0
T35	0	129	0	0
T56	0	1295	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	186	0	0
T86	0	408	0	0
T119	0	576	0	0
T151	0	364	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6203972	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15822	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	52	0	0
T44	869	0	0	0
T52	786	0	0	0
T84	1338	0	0	0
T85	1391	0	0	0
T96	760	0	0	0
T98	20494	3	0	0
T107	0	3	0	0
T130	424	0	0	0
T131	402	0	0	0
T132	527	0	0	0
T271	0	1	0	0
T272	0	6	0	0
T274	0	4	0	0
T275	0	2	0	0
T276	0	10	0	0
T277	0	4	0	0
T278	0	5	0	0
T279	0	1	0	0
T280	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	14430	0	0
T6	16271	23	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	65	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	368	0	0
T34	0	549	0	0
T35	0	7	0	0
T56	0	1045	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	220	0	0
T86	0	76	0	0
T119	0	11	0	0
T151	0	140	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	301	0	0
T6	16271	2	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	1	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	4	0	0
T34	0	7	0	0
T35	0	1	0	0
T56	0	5	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	3	0	0
T86	0	4	0	0
T119	0	2	0	0
T151	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5807249	0	0
T1	2325	722	0	0
T2	26978	22160	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	14102	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5808938	0	0
T1	2325	725	0	0
T2	26978	22160	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	14102	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	390	0	0
T6	16271	2	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	1	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	4	0	0
T34	0	7	0	0
T35	0	1	0	0
T56	0	5	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	3	0	0
T86	0	4	0	0
T119	0	2	0	0
T151	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	358	0	0
T6	16271	2	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	1	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	4	0	0
T34	0	7	0	0
T35	0	1	0	0
T56	0	5	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	3	0	0
T86	0	4	0	0
T119	0	2	0	0
T151	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	301	0	0
T6	16271	2	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	1	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	4	0	0
T34	0	7	0	0
T35	0	1	0	0
T56	0	5	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	3	0	0
T86	0	4	0	0
T119	0	2	0	0
T151	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	301	0	0
T6	16271	2	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	1	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	4	0	0
T34	0	7	0	0
T35	0	1	0	0
T56	0	5	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	3	0	0
T86	0	4	0	0
T119	0	2	0	0
T151	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	14109	0	0
T6	16271	21	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	64	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	364	0	0
T34	0	542	0	0
T35	0	6	0	0
T56	0	1040	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	217	0	0
T86	0	72	0	0
T119	0	9	0	0
T151	0	136	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	275	0	0
T6	16271	2	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	15043	1	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T31	0	4	0	0
T34	0	7	0	0
T35	0	1	0	0
T56	0	4	0	0
T61	874	0	0	0
T62	607	0	0	0
T82	0	3	0	0
T86	0	4	0	0
T119	0	2	0	0
T151	0	4	0	0