Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T9,T26
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T9,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T26
1	0	Covered	T3,T9,T26
1	1	Covered	T3,T9,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T26
0	1	Covered	T3,T9,T81
1	0	Covered	T3,T9,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T36,T79
0	1	Covered	T26,T36,T79
1	0	Covered	T9,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T26,T36
1	-	Covered	T26,T36,T79

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T26
DetectSt	168	Covered	T3,T9,T26
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T9,T26,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T26
DebounceSt->IdleSt	163	Covered	T110,T256,T60
DetectSt->IdleSt	186	Covered	T3,T9,T80
DetectSt->StableSt	191	Covered	T9,T26,T36
IdleSt->DebounceSt	148	Covered	T3,T9,T26
StableSt->IdleSt	206	Covered	T9,T26,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T26
0	1	Covered	T3,T9,T26
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T26
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T26
IdleSt	0	-	-	-	-	-	-	Covered	T3,T9,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T110,T256,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T26
DetectSt	-	-	-	-	1	-	-	Covered	T3,T9,T80
DetectSt	-	-	-	-	0	1	-	Covered	T9,T26,T36
DetectSt	-	-	-	-	0	0	-	Covered	T3,T9,T26
StableSt	-	-	-	-	-	-	1	Covered	T9,T26,T36
StableSt	-	-	-	-	-	-	0	Covered	T26,T36,T79
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	2697	0	0
CntIncr_A	6866773	89708	0	0
CntNoWrap_A	6866773	6202022	0	0
DetectStDropOut_A	6866773	267	0	0
DetectedOut_A	6866773	69521	0	0
DetectedPulseOut_A	6866773	786	0	0
DisabledIdleSt_A	6866773	5762024	0	0
DisabledNoDetection_A	6866773	5764195	0	0
EnterDebounceSt_A	6866773	1376	0	0
EnterDetectSt_A	6866773	1321	0	0
EnterStableSt_A	6866773	786	0	0
PulseIsPulse_A	6866773	786	0	0
StayInStableSt	6866773	68644	0	0
gen_high_event_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	675	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	2697	0	0
T3	6426	8	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	20	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	34	0	0
T36	0	42	0	0
T56	0	54	0	0
T61	874	0	0	0
T79	0	12	0	0
T80	0	22	0	0
T81	0	46	0	0
T82	0	26	0	0
T83	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	89708	0	0
T3	6426	201	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	873	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	986	0	0
T36	0	1386	0	0
T56	0	7020	0	0
T61	874	0	0	0
T79	0	1278	0	0
T80	0	1263	0	0
T81	0	1757	0	0
T82	0	819	0	0
T83	0	260	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6202022	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	6017	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	267	0	0
T3	6426	2	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	5	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T60	0	1	0	0
T61	874	0	0	0
T81	0	19	0	0
T99	0	35	0	0
T100	0	11	0	0
T104	0	13	0	0
T110	0	12	0	0
T270	0	4	0	0
T281	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	69521	0	0
T9	15043	2	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	1108	0	0
T36	0	1719	0	0
T56	0	4851	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	1363	0	0
T82	0	2288	0	0
T83	0	954	0	0
T150	0	2269	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	1346	0	0
T260	0	1681	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	786	0	0
T9	15043	2	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	17	0	0
T36	0	21	0	0
T56	0	27	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	6	0	0
T82	0	13	0	0
T83	0	5	0	0
T150	0	17	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	16	0	0
T260	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5762024	0	0
T1	2325	722	0	0
T2	26978	26505	0	0
T3	6426	3317	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15826	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5764195	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	3317	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1376	0	0
T3	6426	4	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	10	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	17	0	0
T36	0	21	0	0
T56	0	27	0	0
T61	874	0	0	0
T79	0	6	0	0
T80	0	11	0	0
T81	0	23	0	0
T82	0	13	0	0
T83	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	1321	0	0
T3	6426	4	0	0
T5	6099	0	0	0
T6	16271	0	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T9	0	10	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T21	1427	0	0	0
T26	0	17	0	0
T36	0	21	0	0
T56	0	27	0	0
T61	874	0	0	0
T79	0	6	0	0
T80	0	11	0	0
T81	0	23	0	0
T82	0	13	0	0
T83	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	786	0	0
T9	15043	2	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	17	0	0
T36	0	21	0	0
T56	0	27	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	6	0	0
T82	0	13	0	0
T83	0	5	0	0
T150	0	17	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	16	0	0
T260	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	786	0	0
T9	15043	2	0	0
T10	856	0	0	0
T11	499	0	0	0
T26	0	17	0	0
T36	0	21	0	0
T56	0	27	0	0
T63	1096	0	0	0
T64	591	0	0	0
T69	522	0	0	0
T70	426	0	0	0
T71	496	0	0	0
T79	0	6	0	0
T82	0	13	0	0
T83	0	5	0	0
T150	0	17	0	0
T241	421	0	0	0
T242	401	0	0	0
T248	0	16	0	0
T260	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	68644	0	0
T22	8506	0	0	0
T26	14290	1091	0	0
T36	30668	1692	0	0
T40	590	0	0	0
T47	437	0	0	0
T53	507	0	0	0
T56	0	4824	0	0
T78	522	0	0	0
T79	29388	1355	0	0
T80	9895	0	0	0
T82	0	2272	0	0
T83	0	949	0	0
T150	0	2247	0	0
T248	0	1328	0	0
T260	0	1653	0	0
T263	0	142	0	0
T282	425	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	675	0	0
T22	8506	0	0	0
T26	14290	17	0	0
T36	30668	15	0	0
T40	590	0	0	0
T47	437	0	0	0
T53	507	0	0	0
T56	0	10	0	0
T78	522	0	0	0
T79	29388	4	0	0
T80	9895	0	0	0
T82	0	10	0	0
T83	0	5	0	0
T150	0	12	0	0
T248	0	14	0	0
T260	0	24	0	0
T263	0	5	0	0
T282	425	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T6
1	Covered	T1,T4,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T6,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T2	VC_COV_UNR
1	Covered	T2,T6,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T2,T6,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T36
0	1	Covered	T119,T94,T283
1	0	Covered	T60,T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T36
0	1	Covered	T2,T6,T36
1	0	Covered	T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T36
1	-	Covered	T2,T6,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T36
DetectSt	168	Covered	T2,T6,T36
IdleSt	163	Covered	T1,T4,T2
StableSt	191	Covered	T2,T6,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T36
DebounceSt->IdleSt	163	Covered	T2,T6,T31
DetectSt->IdleSt	186	Covered	T119,T60,T94
DetectSt->StableSt	191	Covered	T2,T6,T36
IdleSt->DebounceSt	148	Covered	T2,T6,T36
StableSt->IdleSt	206	Covered	T2,T6,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T36
0	1	Covered	T2,T6,T36
0	0	Excluded	T1,T4,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T36
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T60,T87
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T6,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T36
DetectSt	-	-	-	-	1	-	-	Covered	T119,T60,T94
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T36
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T36
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6866773	826	0	0
CntIncr_A	6866773	44581	0	0
CntNoWrap_A	6866773	6203893	0	0
DetectStDropOut_A	6866773	39	0	0
DetectedOut_A	6866773	16248	0	0
DetectedPulseOut_A	6866773	342	0	0
DisabledIdleSt_A	6866773	5808196	0	0
DisabledNoDetection_A	6866773	5809880	0	0
EnterDebounceSt_A	6866773	442	0	0
EnterDetectSt_A	6866773	385	0	0
EnterStableSt_A	6866773	342	0	0
PulseIsPulse_A	6866773	342	0	0
StayInStableSt	6866773	15871	0	0
gen_high_level_sva.HighLevelEvent_A	6866773	6207068	0	0
gen_not_sticky_sva.StableStDropOut_A	6866773	305	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	826	0	0
T2	26978	8	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	13	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	3	0	0
T34	0	1	0	0
T35	0	18	0	0
T36	0	8	0	0
T79	0	4	0	0
T82	0	6	0	0
T83	0	6	0	0
T119	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	44581	0	0
T2	26978	507	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	354	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	213	0	0
T34	0	233	0	0
T35	0	1020	0	0
T36	0	336	0	0
T79	0	412	0	0
T82	0	147	0	0
T83	0	159	0	0
T119	0	587	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6203893	0	0
T1	2325	722	0	0
T2	26978	26497	0	0
T3	6426	6025	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	15813	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	39	0	0
T19	1102	0	0	0
T34	24908	0	0	0
T35	30022	0	0	0
T73	499	0	0	0
T74	46093	0	0	0
T94	0	1	0	0
T119	17029	2	0	0
T158	0	1	0	0
T185	0	4	0	0
T275	0	6	0	0
T279	0	1	0	0
T283	0	4	0	0
T284	0	12	0	0
T285	0	4	0	0
T286	0	4	0	0
T287	506	0	0	0
T288	812	0	0	0
T289	448	0	0	0
T290	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	16248	0	0
T2	26978	90	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	50	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	82	0	0
T35	0	238	0	0
T36	0	211	0	0
T79	0	170	0	0
T82	0	258	0	0
T83	0	275	0	0
T150	0	164	0	0
T151	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	342	0	0
T2	26978	3	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	6	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	1	0	0
T35	0	8	0	0
T36	0	4	0	0
T79	0	2	0	0
T82	0	3	0	0
T83	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5808196	0	0
T1	2325	722	0	0
T2	26978	22160	0	0
T3	6426	6024	0	0
T4	408	7	0	0
T5	6099	1470	0	0
T6	16271	14102	0	0
T12	521	120	0	0
T13	502	101	0	0
T14	494	93	0	0
T15	408	7	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	5809880	0	0
T1	2325	725	0	0
T2	26978	22160	0	0
T3	6426	6025	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	14102	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	442	0	0
T2	26978	5	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	7	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	2	0	0
T34	0	1	0	0
T35	0	10	0	0
T36	0	4	0	0
T79	0	2	0	0
T82	0	3	0	0
T83	0	3	0	0
T119	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	385	0	0
T2	26978	3	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	6	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	1	0	0
T35	0	8	0	0
T36	0	4	0	0
T79	0	2	0	0
T82	0	3	0	0
T83	0	3	0	0
T119	0	2	0	0
T150	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	342	0	0
T2	26978	3	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	6	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	1	0	0
T35	0	8	0	0
T36	0	4	0	0
T79	0	2	0	0
T82	0	3	0	0
T83	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	342	0	0
T2	26978	3	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	6	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	1	0	0
T35	0	8	0	0
T36	0	4	0	0
T79	0	2	0	0
T82	0	3	0	0
T83	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	15871	0	0
T2	26978	87	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	44	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	81	0	0
T35	0	230	0	0
T36	0	207	0	0
T79	0	166	0	0
T82	0	255	0	0
T83	0	272	0	0
T150	0	158	0	0
T151	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	6207068	0	0
T1	2325	725	0	0
T2	26978	26516	0	0
T3	6426	6026	0	0
T4	408	8	0	0
T5	6099	1484	0	0
T6	16271	15833	0	0
T12	521	121	0	0
T13	502	102	0	0
T14	494	94	0	0
T15	408	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6866773	305	0	0
T2	26978	3	0	0
T3	6426	0	0	0
T5	6099	0	0	0
T6	16271	6	0	0
T7	2821	0	0	0
T8	1940	0	0	0
T12	521	0	0	0
T13	502	0	0	0
T14	494	0	0	0
T15	408	0	0	0
T31	0	1	0	0
T35	0	8	0	0
T36	0	4	0	0
T82	0	3	0	0
T83	0	3	0	0
T86	0	6	0	0
T151	0	1	0	0
T260	0	1	0	0