Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1182511193	11175	0	0
auto_block_debounce_ctl_rd_A	1182511193	1903	0	0
auto_block_out_ctl_rd_A	1182511193	2701	0	0
com_det_ctl_0_rd_A	1182511193	3784	0	0
com_det_ctl_1_rd_A	1182511193	3909	0	0
com_det_ctl_2_rd_A	1182511193	3881	0	0
com_det_ctl_3_rd_A	1182511193	3989	0	0
com_out_ctl_0_rd_A	1182511193	4274	0	0
com_out_ctl_1_rd_A	1182511193	4425	0	0
com_out_ctl_2_rd_A	1182511193	4389	0	0
com_out_ctl_3_rd_A	1182511193	4447	0	0
com_pre_det_ctl_0_rd_A	1182511193	1587	0	0
com_pre_det_ctl_1_rd_A	1182511193	1589	0	0
com_pre_det_ctl_2_rd_A	1182511193	1592	0	0
com_pre_det_ctl_3_rd_A	1182511193	1447	0	0
com_pre_sel_ctl_0_rd_A	1182511193	4663	0	0
com_pre_sel_ctl_1_rd_A	1182511193	4790	0	0
com_pre_sel_ctl_2_rd_A	1182511193	4717	0	0
com_pre_sel_ctl_3_rd_A	1182511193	4802	0	0
com_sel_ctl_0_rd_A	1182511193	4705	0	0
com_sel_ctl_1_rd_A	1182511193	4643	0	0
com_sel_ctl_2_rd_A	1182511193	4633	0	0
com_sel_ctl_3_rd_A	1182511193	4620	0	0
ec_rst_ctl_rd_A	1182511193	2702	0	0
intr_enable_rd_A	1182511193	2275	0	0
key_intr_ctl_rd_A	1182511193	4036	0	0
key_intr_debounce_ctl_rd_A	1182511193	1569	0	0
key_invert_ctl_rd_A	1182511193	5088	0	0
pin_allowed_ctl_rd_A	1182511193	6468	0	0
pin_out_ctl_rd_A	1182511193	4494	0	0
pin_out_value_rd_A	1182511193	4969	0	0
regwen_rd_A	1182511193	1656	0	0
ulp_ac_debounce_ctl_rd_A	1182511193	1925	0	0
ulp_ctl_rd_A	1182511193	1656	0	0
ulp_lid_debounce_ctl_rd_A	1182511193	1690	0	0
ulp_pwrb_debounce_ctl_rd_A	1182511193	1812	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	11175	0	0
T5	292790	12	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	8	0	0
T21	171263	0	0	0
T22	0	4	0	0
T32	0	6	0	0
T41	0	7	0	0
T43	0	1	0	0
T51	0	11	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T74	0	14	0	0
T151	0	3	0	0
T237	0	5	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1903	0	0
T20	0	24	0	0
T22	200754	19	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	46	0	0
T49	0	12	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T74	0	18	0	0
T108	0	22	0	0
T142	0	9	0	0
T151	0	16	0	0
T187	0	49	0	0
T311	0	21	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	2701	0	0
T20	0	19	0	0
T22	200754	20	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	39	0	0
T49	0	7	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T74	0	19	0	0
T108	0	31	0	0
T142	0	9	0	0
T151	0	14	0	0
T187	0	47	0	0
T311	0	21	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	3784	0	0
T3	674743	44	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	9	0	0
T21	171263	0	0	0
T22	0	9	0	0
T34	0	58	0	0
T36	0	89	0	0
T61	122504	0	0	0
T74	0	55	0	0
T80	0	17	0	0
T81	0	3	0	0
T151	0	22	0	0
T260	0	18	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	3909	0	0
T3	674743	59	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	13	0	0
T21	171263	0	0	0
T22	0	7	0	0
T34	0	76	0	0
T36	0	106	0	0
T61	122504	0	0	0
T74	0	38	0	0
T80	0	13	0	0
T81	0	19	0	0
T151	0	30	0	0
T260	0	38	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	3881	0	0
T3	674743	44	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	11	0	0
T21	171263	0	0	0
T22	0	3	0	0
T34	0	59	0	0
T36	0	103	0	0
T61	122504	0	0	0
T74	0	41	0	0
T80	0	14	0	0
T81	0	15	0	0
T151	0	24	0	0
T260	0	32	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	3989	0	0
T3	674743	25	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	9	0	0
T21	171263	0	0	0
T22	0	2	0	0
T34	0	54	0	0
T36	0	95	0	0
T61	122504	0	0	0
T74	0	27	0	0
T80	0	16	0	0
T81	0	14	0	0
T151	0	48	0	0
T260	0	16	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4274	0	0
T3	674743	32	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	13	0	0
T21	171263	0	0	0
T22	0	13	0	0
T34	0	73	0	0
T36	0	88	0	0
T61	122504	0	0	0
T74	0	40	0	0
T80	0	26	0	0
T81	0	21	0	0
T151	0	19	0	0
T260	0	33	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4425	0	0
T3	674743	39	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	8	0	0
T21	171263	0	0	0
T22	0	10	0	0
T34	0	68	0	0
T36	0	113	0	0
T61	122504	0	0	0
T74	0	41	0	0
T80	0	16	0	0
T81	0	24	0	0
T151	0	40	0	0
T260	0	52	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4389	0	0
T3	674743	46	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	12	0	0
T21	171263	0	0	0
T22	0	7	0	0
T34	0	57	0	0
T36	0	102	0	0
T61	122504	0	0	0
T74	0	30	0	0
T80	0	24	0	0
T81	0	21	0	0
T151	0	32	0	0
T260	0	28	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4447	0	0
T3	674743	54	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	16	0	0
T21	171263	0	0	0
T22	0	1	0	0
T34	0	63	0	0
T36	0	109	0	0
T61	122504	0	0	0
T74	0	54	0	0
T80	0	4	0	0
T81	0	30	0	0
T151	0	23	0	0
T260	0	59	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1587	0	0
T20	0	4	0	0
T22	200754	10	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	32	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T74	0	6	0	0
T95	0	10	0	0
T108	0	22	0	0
T151	0	11	0	0
T187	0	36	0	0
T197	0	12	0	0
T312	0	30	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1589	0	0
T20	0	3	0	0
T22	200754	2	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	32	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T74	0	15	0	0
T95	0	15	0	0
T108	0	28	0	0
T151	0	13	0	0
T187	0	27	0	0
T197	0	5	0	0
T312	0	42	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1592	0	0
T20	0	8	0	0
T22	200754	11	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	18	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T74	0	12	0	0
T95	0	9	0	0
T108	0	23	0	0
T151	0	6	0	0
T187	0	44	0	0
T197	0	8	0	0
T312	0	31	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1447	0	0
T20	0	11	0	0
T22	200754	5	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	21	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T74	0	18	0	0
T95	0	17	0	0
T108	0	1	0	0
T151	0	13	0	0
T187	0	31	0	0
T197	0	10	0	0
T312	0	19	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4663	0	0
T3	674743	55	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T21	171263	0	0	0
T22	0	4	0	0
T34	0	77	0	0
T36	0	132	0	0
T61	122504	0	0	0
T74	0	48	0	0
T80	0	16	0	0
T81	0	22	0	0
T151	0	51	0	0
T248	0	61	0	0
T260	0	26	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4790	0	0
T3	674743	31	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	18	0	0
T21	171263	0	0	0
T22	0	1	0	0
T34	0	73	0	0
T36	0	112	0	0
T61	122504	0	0	0
T74	0	42	0	0
T80	0	38	0	0
T81	0	12	0	0
T151	0	48	0	0
T260	0	31	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4717	0	0
T3	674743	40	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	11	0	0
T21	171263	0	0	0
T22	0	8	0	0
T34	0	62	0	0
T36	0	122	0	0
T61	122504	0	0	0
T74	0	51	0	0
T80	0	25	0	0
T81	0	19	0	0
T151	0	34	0	0
T260	0	18	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4802	0	0
T3	674743	42	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	13	0	0
T21	171263	0	0	0
T22	0	8	0	0
T34	0	75	0	0
T36	0	109	0	0
T61	122504	0	0	0
T74	0	39	0	0
T80	0	28	0	0
T81	0	27	0	0
T151	0	45	0	0
T260	0	20	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4705	0	0
T3	674743	30	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	7	0	0
T21	171263	0	0	0
T22	0	9	0	0
T34	0	84	0	0
T36	0	135	0	0
T61	122504	0	0	0
T74	0	50	0	0
T80	0	24	0	0
T81	0	16	0	0
T151	0	31	0	0
T260	0	51	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4643	0	0
T3	674743	42	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	13	0	0
T21	171263	0	0	0
T22	0	15	0	0
T34	0	73	0	0
T36	0	131	0	0
T61	122504	0	0	0
T74	0	44	0	0
T80	0	18	0	0
T81	0	32	0	0
T151	0	37	0	0
T260	0	33	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4633	0	0
T3	674743	33	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	16	0	0
T21	171263	0	0	0
T22	0	4	0	0
T34	0	70	0	0
T36	0	109	0	0
T61	122504	0	0	0
T74	0	65	0	0
T80	0	15	0	0
T81	0	22	0	0
T151	0	43	0	0
T260	0	30	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4620	0	0
T3	674743	37	0	0
T5	292790	0	0	0
T6	813558	0	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T13	243442	0	0	0
T14	59407	0	0	0
T15	101940	0	0	0
T20	0	7	0	0
T21	171263	0	0	0
T22	0	4	0	0
T34	0	67	0	0
T36	0	101	0	0
T61	122504	0	0	0
T74	0	30	0	0
T80	0	11	0	0
T81	0	11	0	0
T151	0	23	0	0
T260	0	28	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	2702	0	0
T11	110411	0	0	0
T20	0	13	0	0
T22	0	12	0	0
T34	0	21	0	0
T36	0	21	0	0
T63	525843	4	0	0
T64	65088	0	0	0
T70	51251	0	0	0
T71	59554	0	0	0
T72	62060	0	0	0
T74	0	33	0	0
T81	0	13	0	0
T151	0	38	0	0
T241	211034	0	0	0
T242	193081	0	0	0
T243	210856	0	0	0
T244	246516	0	0	0
T248	0	16	0	0
T260	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	2275	0	0
T7	129987	31	0	0
T8	169626	0	0	0
T9	714606	0	0	0
T10	107149	0	0	0
T20	0	16	0	0
T21	171263	0	0	0
T41	0	56	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T63	525843	0	0	0
T64	65088	0	0	0
T69	260762	0	0	0
T74	0	48	0	0
T95	0	86	0	0
T108	0	8	0	0
T151	0	23	0	0
T187	0	27	0	0
T197	0	7	0	0
T312	0	28	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4036	0	0
T7	129987	4	0	0
T8	169626	0	0	0
T9	714606	0	0	0
T10	107149	0	0	0
T20	0	13	0	0
T21	171263	0	0	0
T22	0	8	0	0
T38	0	2	0	0
T40	0	4	0	0
T41	0	16	0	0
T42	0	6	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T63	525843	0	0	0
T64	65088	0	0	0
T69	260762	0	0	0
T74	0	23	0	0
T151	0	6	0	0
T178	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1569	0	0
T20	0	4	0	0
T22	200754	13	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	29	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T74	0	31	0	0
T95	0	11	0	0
T108	0	31	0	0
T151	0	5	0	0
T187	0	43	0	0
T197	0	9	0	0
T312	0	27	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	5088	0	0
T7	129987	0	0	0
T8	169626	0	0	0
T9	714606	0	0	0
T10	107149	0	0	0
T14	59407	61	0	0
T15	101940	0	0	0
T20	0	9	0	0
T21	171263	0	0	0
T22	0	67	0	0
T41	0	146	0	0
T49	0	64	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T69	260762	0	0	0
T72	0	48	0	0
T74	0	149	0	0
T151	0	9	0	0
T313	0	64	0	0
T314	0	81	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	6468	0	0
T7	129987	53	0	0
T8	169626	0	0	0
T9	714606	0	0	0
T10	107149	0	0	0
T20	0	6	0	0
T21	171263	0	0	0
T22	0	168	0	0
T41	0	31	0	0
T53	0	45	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T63	525843	0	0	0
T64	65088	0	0	0
T69	260762	0	0	0
T74	0	156	0	0
T77	0	62	0	0
T102	0	127	0	0
T151	0	89	0	0
T315	0	29	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4494	0	0
T7	129987	65	0	0
T8	169626	0	0	0
T9	714606	0	0	0
T10	107149	0	0	0
T20	0	5	0	0
T21	171263	0	0	0
T22	0	171	0	0
T41	0	19	0	0
T53	0	39	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T63	525843	0	0	0
T64	65088	0	0	0
T69	260762	0	0	0
T74	0	158	0	0
T77	0	57	0	0
T102	0	126	0	0
T151	0	89	0	0
T315	0	39	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	4969	0	0
T7	129987	80	0	0
T8	169626	0	0	0
T9	714606	0	0	0
T10	107149	0	0	0
T20	0	3	0	0
T21	171263	0	0	0
T22	0	148	0	0
T41	0	24	0	0
T53	0	54	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T63	525843	0	0	0
T64	65088	0	0	0
T69	260762	0	0	0
T74	0	160	0	0
T77	0	66	0	0
T102	0	136	0	0
T151	0	61	0	0
T315	0	40	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1656	0	0
T20	686124	12	0	0
T23	90891	0	0	0
T24	391148	0	0	0
T41	0	20	0	0
T74	250496	16	0	0
T81	107182	0	0	0
T82	239297	0	0	0
T95	0	19	0	0
T108	0	11	0	0
T151	0	5	0	0
T187	0	29	0	0
T191	128492	0	0	0
T192	202718	0	0	0
T197	0	3	0	0
T259	591110	0	0	0
T290	60604	0	0	0
T312	0	31	0	0
T316	0	40	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1925	0	0
T20	0	28	0	0
T22	200754	18	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	41	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T66	0	10	0	0
T67	0	9	0	0
T74	0	22	0	0
T85	0	10	0	0
T146	0	13	0	0
T151	0	10	0	0
T187	0	47	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1656	0	0
T20	0	13	0	0
T22	200754	12	0	0
T31	780180	0	0	0
T40	51281	0	0	0
T41	0	22	0	0
T53	50760	0	0	0
T54	130925	0	0	0
T55	101809	0	0	0
T56	181722	0	0	0
T57	50895	0	0	0
T58	128223	0	0	0
T59	51952	0	0	0
T67	0	9	0	0
T74	0	13	0	0
T85	0	5	0	0
T146	0	17	0	0
T151	0	7	0	0
T187	0	31	0	0
T317	0	8	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1690	0	0
T8	169626	4	0	0
T9	714606	0	0	0
T10	107149	0	0	0
T20	0	14	0	0
T21	171263	0	0	0
T22	0	13	0	0
T41	0	37	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T63	525843	0	0	0
T64	65088	0	0	0
T66	0	6	0	0
T67	0	12	0	0
T69	260762	0	0	0
T70	51251	0	0	0
T74	0	29	0	0
T85	0	11	0	0
T146	0	9	0	0
T151	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182511193	1812	0	0
T8	169626	1	0	0
T9	714606	0	0	0
T10	107149	0	0	0
T20	0	24	0	0
T21	171263	0	0	0
T22	0	16	0	0
T41	0	38	0	0
T61	122504	0	0	0
T62	88189	0	0	0
T63	525843	0	0	0
T64	65088	0	0	0
T67	0	9	0	0
T69	260762	0	0	0
T70	51251	0	0	0
T74	0	17	0	0
T85	0	10	0	0
T146	0	13	0	0
T151	0	17	0	0
T187	0	39	0	0