Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T18,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T18,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T18,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T18,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T11
0	1	Covered	T1,T18,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T18,T11
1	-	Covered	T1,T18,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T18,T11
DetectSt	168	Covered	T1,T18,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T18,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T18,T11
DebounceSt->IdleSt	163	Covered	T42,T63,T77
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T18,T11
IdleSt->DebounceSt	148	Covered	T1,T18,T11
StableSt->IdleSt	206	Covered	T1,T18,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T18,T11
0	1	Covered	T1,T18,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T18,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T18,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T18,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T100,T101
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T18,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T18,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T18,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T18,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	258	0	0
CntIncr_A	7906335	195092	0	0
CntNoWrap_A	7906335	7292135	0	0
DetectStDropOut_A	7906335	0	0	0
DetectedOut_A	7906335	840	0	0
DetectedPulseOut_A	7906335	121	0	0
DisabledIdleSt_A	7906335	7091224	0	0
DisabledNoDetection_A	7906335	7093476	0	0
EnterDebounceSt_A	7906335	138	0	0
EnterDetectSt_A	7906335	121	0	0
EnterStableSt_A	7906335	121	0	0
PulseIsPulse_A	7906335	121	0	0
StayInStableSt	7906335	719	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7906335	6689	0	0
gen_low_level_sva.LowLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	258	0	0
T1	15218	4	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	4	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	4	0	0
T44	0	6	0	0
T61	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	195092	0	0
T1	15218	192	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	96	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	93	0	0
T38	0	102	0	0
T39	0	84	0	0
T40	0	85	0	0
T42	0	11	0	0
T43	0	180	0	0
T44	0	96920	0	0
T61	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292135	0	0
T1	15218	9756	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	840	0	0
T1	15218	6	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	14	0	0
T38	0	20	0	0
T39	0	8	0	0
T40	0	6	0	0
T43	0	11	0	0
T44	0	17	0	0
T61	0	15	0	0
T77	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	121	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T61	0	2	0	0
T77	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7091224	0	0
T1	15218	9476	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7093476	0	0
T1	15218	9494	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	138	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T61	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	121	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T61	0	2	0	0
T77	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	121	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T61	0	2	0	0
T77	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	121	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T61	0	2	0	0
T77	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	719	0	0
T1	15218	4	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	12	0	0
T38	0	18	0	0
T39	0	6	0	0
T40	0	5	0	0
T43	0	9	0	0
T44	0	14	0	0
T61	0	13	0	0
T77	0	1	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6689	0	0
T1	15218	36	0	0
T2	2227	18	0	0
T3	578	0	0	0
T4	422	1	0	0
T5	501	6	0	0
T6	8611	28	0	0
T7	7367	25	0	0
T8	249850	32	0	0
T13	581	0	0	0
T14	8246	26	0	0
T18	0	3	0	0
T46	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	121	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T61	0	2	0	0
T77	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T8,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T8,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T8,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T8,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T48
0	1	Covered	T74,T75,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T48
0	1	Unreachable
1	0	Covered	T2,T8,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T48
DetectSt	168	Covered	T2,T8,T48
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T8,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T48
DebounceSt->IdleSt	163	Covered	T50,T42,T60
DetectSt->IdleSt	186	Covered	T74,T75,T76
DetectSt->StableSt	191	Covered	T2,T8,T48
IdleSt->DebounceSt	148	Covered	T2,T8,T48
StableSt->IdleSt	206	Covered	T2,T8,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T48
0	1	Covered	T2,T8,T48
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T48
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T48
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T60,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T48
DetectSt	-	-	-	-	1	-	-	Covered	T74,T75,T76
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	200	0	0
CntIncr_A	7906335	219323	0	0
CntNoWrap_A	7906335	7292193	0	0
DetectStDropOut_A	7906335	18	0	0
DetectedOut_A	7906335	549898	0	0
DetectedPulseOut_A	7906335	56	0	0
DisabledIdleSt_A	7906335	5152566	0	0
DisabledNoDetection_A	7906335	5154859	0	0
EnterDebounceSt_A	7906335	127	0	0
EnterDetectSt_A	7906335	74	0	0
EnterStableSt_A	7906335	56	0	0
PulseIsPulse_A	7906335	56	0	0
StayInStableSt	7906335	549842	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7906335	6689	0	0
gen_low_level_sva.LowLevelEvent_A	7906335	7294690	0	0
gen_sticky_sva.StableStDropOut_A	7906335	978853	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	200	0	0
T2	2227	2	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	4	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	3	0	0
T51	0	4	0	0
T60	0	5	0	0
T61	0	2	0	0
T63	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	219323	0	0
T2	2227	83	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	41315	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T42	0	58	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	76	0	0
T49	0	67	0	0
T50	0	96	0	0
T51	0	35400	0	0
T60	0	385	0	0
T61	0	74	0	0
T63	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292193	0	0
T1	15218	9760	0	0
T2	2227	622	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244260	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	18	0	0
T33	1008	0	0	0
T64	8490	0	0	0
T68	18616	0	0	0
T74	6846	2	0	0
T75	0	4	0	0
T76	0	3	0	0
T80	35440	0	0	0
T102	2989	0	0	0
T103	0	4	0	0
T104	0	3	0	0
T105	0	2	0	0
T106	493	0	0	0
T107	35764	0	0	0
T108	499	0	0	0
T109	408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	549898	0	0
T2	2227	199	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	200694	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	173	0	0
T49	0	181	0	0
T51	0	100978	0	0
T61	0	319	0	0
T69	0	105	0	0
T72	0	349	0	0
T74	0	111	0	0
T99	0	32	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	56	0	0
T2	2227	1	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T74	0	1	0	0
T99	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	5152566	0	0
T1	15218	9569	0	0
T2	2227	214	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	1767	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	5154859	0	0
T1	15218	9587	0	0
T2	2227	217	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	1780	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	127	0	0
T2	2227	1	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T42	0	2	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T51	0	2	0	0
T60	0	5	0	0
T61	0	1	0	0
T63	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	74	0	0
T2	2227	1	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T74	0	3	0	0
T99	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	56	0	0
T2	2227	1	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T74	0	1	0	0
T99	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	56	0	0
T2	2227	1	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0
T74	0	1	0	0
T99	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	549842	0	0
T2	2227	198	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	200692	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	172	0	0
T49	0	180	0	0
T51	0	100976	0	0
T61	0	318	0	0
T69	0	103	0	0
T72	0	348	0	0
T74	0	110	0	0
T99	0	31	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6689	0	0
T1	15218	36	0	0
T2	2227	18	0	0
T3	578	0	0	0
T4	422	1	0	0
T5	501	6	0	0
T6	8611	28	0	0
T7	7367	25	0	0
T8	249850	32	0	0
T13	581	0	0	0
T14	8246	26	0	0
T18	0	3	0	0
T46	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	978853	0	0
T2	2227	113	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	456	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	70	0	0
T49	0	52	0	0
T51	0	101	0	0
T61	0	181	0	0
T69	0	297	0	0
T72	0	237355	0	0
T74	0	150	0	0
T99	0	237	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T69,T72,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Unreachable
1	0	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T8,T42,T60
DetectSt->IdleSt	186	Covered	T69,T72,T73
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T60,T69
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T69,T72,T73
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	202	0	0
CntIncr_A	7906335	103236	0	0
CntNoWrap_A	7906335	7292191	0	0
DetectStDropOut_A	7906335	9	0	0
DetectedOut_A	7906335	388237	0	0
DetectedPulseOut_A	7906335	58	0	0
DisabledIdleSt_A	7906335	5152566	0	0
DisabledNoDetection_A	7906335	5154859	0	0
EnterDebounceSt_A	7906335	136	0	0
EnterDetectSt_A	7906335	67	0	0
EnterStableSt_A	7906335	58	0	0
PulseIsPulse_A	7906335	58	0	0
StayInStableSt	7906335	388179	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_sticky_sva.StableStDropOut_A	7906335	1257584	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	202	0	0
T1	15218	2	0	0
T2	2227	2	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	7	0	0
T13	581	0	0	0
T14	8246	0	0	0
T42	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T51	0	4	0	0
T60	0	5	0	0
T61	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	103236	0	0
T1	15218	48	0	0
T2	2227	88	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	203	0	0
T13	581	0	0	0
T14	8246	0	0	0
T42	0	59	0	0
T48	0	56	0	0
T49	0	41	0	0
T50	0	166	0	0
T51	0	144	0	0
T60	0	415	0	0
T61	0	85	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292191	0	0
T1	15218	9758	0	0
T2	2227	622	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244257	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	9	0	0
T33	1008	0	0	0
T64	8490	0	0	0
T68	18616	0	0	0
T69	1080	3	0	0
T72	428378	2	0	0
T73	0	1	0	0
T74	6846	0	0	0
T102	2989	0	0	0
T105	0	1	0	0
T106	493	0	0	0
T107	35764	0	0	0
T110	0	2	0	0
T111	3119	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	388237	0	0
T1	15218	41	0	0
T2	2227	114	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	262	0	0
T13	581	0	0	0
T14	8246	0	0	0
T48	0	139	0	0
T49	0	49	0	0
T50	0	282	0	0
T51	0	259	0	0
T61	0	554	0	0
T69	0	13	0	0
T72	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	58	0	0
T1	15218	1	0	0
T2	2227	1	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	5152566	0	0
T1	15218	9569	0	0
T2	2227	214	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	1767	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	5154859	0	0
T1	15218	9587	0	0
T2	2227	217	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	1780	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	136	0	0
T1	15218	1	0	0
T2	2227	1	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	6	0	0
T13	581	0	0	0
T14	8246	0	0	0
T42	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T60	0	5	0	0
T61	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	67	0	0
T1	15218	1	0	0
T2	2227	1	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T61	0	1	0	0
T69	0	5	0	0
T72	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	58	0	0
T1	15218	1	0	0
T2	2227	1	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	58	0	0
T1	15218	1	0	0
T2	2227	1	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	388179	0	0
T1	15218	40	0	0
T2	2227	113	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	261	0	0
T13	581	0	0	0
T14	8246	0	0	0
T48	0	138	0	0
T49	0	48	0	0
T50	0	280	0	0
T51	0	257	0	0
T61	0	553	0	0
T69	0	11	0	0
T72	0	45	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1257584	0	0
T1	15218	78	0	0
T2	2227	190	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	59	0	0
T13	581	0	0	0
T14	8246	0	0	0
T48	0	119	0	0
T49	0	207	0	0
T50	0	146	0	0
T51	0	136087	0	0
T61	0	94	0	0
T69	0	144	0	0
T72	0	95001	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T48
0	1	Covered	T1,T69,T70
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T48
0	1	Unreachable
1	0	Covered	T2,T8,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T8,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T8,T42,T63
DetectSt->IdleSt	186	Covered	T1,T69,T70
DetectSt->StableSt	191	Covered	T2,T8,T48
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T2,T8,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T69,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T1,T69,T70
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T48
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	209	0	0
CntIncr_A	7906335	324985	0	0
CntNoWrap_A	7906335	7292184	0	0
DetectStDropOut_A	7906335	18	0	0
DetectedOut_A	7906335	575907	0	0
DetectedPulseOut_A	7906335	57	0	0
DisabledIdleSt_A	7906335	5152566	0	0
DisabledNoDetection_A	7906335	5154859	0	0
EnterDebounceSt_A	7906335	135	0	0
EnterDetectSt_A	7906335	75	0	0
EnterStableSt_A	7906335	57	0	0
PulseIsPulse_A	7906335	57	0	0
StayInStableSt	7906335	575850	0	0
gen_high_event_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_sticky_sva.StableStDropOut_A	7906335	956334	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	209	0	0
T1	15218	2	0	0
T2	2227	2	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	7	0	0
T13	581	0	0	0
T14	8246	0	0	0
T42	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T51	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	324985	0	0
T1	15218	91	0	0
T2	2227	92	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	304	0	0
T13	581	0	0	0
T14	8246	0	0	0
T42	0	60	0	0
T48	0	23	0	0
T49	0	50	0	0
T50	0	124	0	0
T51	0	108	0	0
T60	0	88	0	0
T61	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292184	0	0
T1	15218	9758	0	0
T2	2227	622	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244257	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	18	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T69	0	2	0	0
T70	0	3	0	0
T112	0	1	0	0
T113	0	2	0	0
T114	0	1	0	0
T115	0	5	0	0
T116	0	2	0	0
T117	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	575907	0	0
T2	2227	272	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	88	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	113	0	0
T49	0	115	0	0
T50	0	90	0	0
T51	0	406	0	0
T60	0	693	0	0
T61	0	593	0	0
T69	0	2	0	0
T72	0	207294	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	57	0	0
T2	2227	1	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	5152566	0	0
T1	15218	9569	0	0
T2	2227	214	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	1767	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	5154859	0	0
T1	15218	9587	0	0
T2	2227	217	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	1780	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	135	0	0
T1	15218	1	0	0
T2	2227	1	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	6	0	0
T13	581	0	0	0
T14	8246	0	0	0
T42	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	75	0	0
T1	15218	1	0	0
T2	2227	1	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	57	0	0
T2	2227	1	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	57	0	0
T2	2227	1	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T69	0	2	0	0
T72	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	575850	0	0
T2	2227	271	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	87	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	112	0	0
T49	0	114	0	0
T50	0	88	0	0
T51	0	404	0	0
T60	0	692	0	0
T61	0	592	0	0
T72	0	207293	0	0
T74	0	404	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	956334	0	0
T2	2227	40	0	0
T3	578	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	273	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T48	0	186	0	0
T49	0	137	0	0
T50	0	405	0	0
T51	0	135997	0	0
T60	0	308	0	0
T61	0	62	0	0
T69	0	58	0	0
T72	0	64	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T27,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T27,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T27,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T27,T34
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T27,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T27,T34
0	1	Covered	T116
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T27,T34
0	1	Covered	T27,T29,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T27,T34
1	-	Covered	T27,T29,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T27,T34
DetectSt	168	Covered	T1,T27,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T27,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T27,T34
DebounceSt->IdleSt	163	Covered	T42,T63,T118
DetectSt->IdleSt	186	Covered	T116
DetectSt->StableSt	191	Covered	T1,T27,T34
IdleSt->DebounceSt	148	Covered	T1,T27,T34
StableSt->IdleSt	206	Covered	T1,T27,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T27,T34
0	1	Covered	T1,T27,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T27,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T27,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T27,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T118,T119,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T27,T34
DetectSt	-	-	-	-	1	-	-	Covered	T116
DetectSt	-	-	-	-	0	1	-	Covered	T1,T27,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T29,T30
StableSt	-	-	-	-	-	-	0	Covered	T1,T27,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	89	0	0
CntIncr_A	7906335	31731	0	0
CntNoWrap_A	7906335	7292304	0	0
DetectStDropOut_A	7906335	1	0	0
DetectedOut_A	7906335	3605	0	0
DetectedPulseOut_A	7906335	41	0	0
DisabledIdleSt_A	7906335	7106814	0	0
DisabledNoDetection_A	7906335	7109050	0	0
EnterDebounceSt_A	7906335	47	0	0
EnterDetectSt_A	7906335	42	0	0
EnterStableSt_A	7906335	41	0	0
PulseIsPulse_A	7906335	41	0	0
StayInStableSt	7906335	3539	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	89	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	4	0	0
T29	0	4	0	0
T30	0	4	0	0
T33	0	4	0	0
T34	0	2	0	0
T42	0	1	0	0
T63	0	1	0	0
T66	0	2	0	0
T121	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	31731	0	0
T1	15218	59	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	74	0	0
T29	0	168	0	0
T30	0	32	0	0
T33	0	188	0	0
T34	0	43	0	0
T42	0	18	0	0
T63	0	17	0	0
T66	0	49	0	0
T121	0	29475	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292304	0	0
T1	15218	9758	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1	0	0
T116	8258	1	0	0
T119	665	0	0	0
T122	1118	0	0	0
T123	7515	0	0	0
T124	522	0	0	0
T125	522	0	0	0
T126	65756	0	0	0
T127	28222	0	0	0
T128	410	0	0	0
T129	527	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	3605	0	0
T1	15218	106	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	116	0	0
T29	0	85	0	0
T30	0	82	0	0
T33	0	89	0	0
T34	0	284	0	0
T66	0	39	0	0
T121	0	42	0	0
T130	0	72	0	0
T131	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	41	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T29	0	2	0	0
T30	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T66	0	1	0	0
T121	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7106814	0	0
T1	15218	9402	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7109050	0	0
T1	15218	9419	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	47	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T29	0	2	0	0
T30	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T42	0	1	0	0
T63	0	1	0	0
T66	0	1	0	0
T121	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	42	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T29	0	2	0	0
T30	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T66	0	1	0	0
T121	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	41	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T29	0	2	0	0
T30	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T66	0	1	0	0
T121	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	41	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T29	0	2	0	0
T30	0	2	0	0
T33	0	2	0	0
T34	0	1	0	0
T66	0	1	0	0
T121	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	3539	0	0
T1	15218	104	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	114	0	0
T29	0	82	0	0
T30	0	79	0	0
T33	0	86	0	0
T34	0	282	0	0
T66	0	37	0	0
T121	0	41	0	0
T130	0	70	0	0
T131	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	16	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	2	0	0
T29	0	1	0	0
T30	0	1	0	0
T33	0	1	0	0
T34	752	0	0	0
T42	6182	0	0	0
T50	1705	0	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T114	0	1	0	0
T118	0	1	0	0
T121	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	528	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T35,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T35,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T35,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T27
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T35,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T35,T31
0	1	Covered	T65,T136,T137
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T35,T31
0	1	Covered	T1,T31,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T35,T31
1	-	Covered	T1,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T35,T42
DetectSt	168	Covered	T1,T35,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T35,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T35,T31
DebounceSt->IdleSt	163	Covered	T42,T63,T32
DetectSt->IdleSt	186	Covered	T65,T136,T137
DetectSt->StableSt	191	Covered	T1,T35,T31
IdleSt->DebounceSt	148	Covered	T1,T35,T42
StableSt->IdleSt	206	Covered	T1,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T35,T42
0	1	Covered	T1,T35,T42
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T35,T31
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T35,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T35,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T30,T118
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T35,T42
DetectSt	-	-	-	-	1	-	-	Covered	T65,T136,T137
DetectSt	-	-	-	-	0	1	-	Covered	T1,T35,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T1,T35,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	149	0	0
CntIncr_A	7906335	155575	0	0
CntNoWrap_A	7906335	7292244	0	0
DetectStDropOut_A	7906335	3	0	0
DetectedOut_A	7906335	81067	0	0
DetectedPulseOut_A	7906335	67	0	0
DisabledIdleSt_A	7906335	6915920	0	0
DisabledNoDetection_A	7906335	6918155	0	0
EnterDebounceSt_A	7906335	79	0	0
EnterDetectSt_A	7906335	70	0	0
EnterStableSt_A	7906335	67	0	0
PulseIsPulse_A	7906335	67	0	0
StayInStableSt	7906335	80970	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7906335	2434	0	0
gen_low_level_sva.LowLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	149	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	3	0	0
T31	0	4	0	0
T32	0	3	0	0
T33	0	4	0	0
T35	0	2	0	0
T42	0	1	0	0
T63	0	1	0	0
T65	0	2	0	0
T111	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	155575	0	0
T1	15218	59	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	32	0	0
T31	0	112	0	0
T32	0	38	0	0
T33	0	188	0	0
T35	0	98	0	0
T42	0	18	0	0
T63	0	17	0	0
T65	0	91	0	0
T111	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292244	0	0
T1	15218	9758	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	3	0	0
T30	641	0	0	0
T65	634	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	770	0	0	0
T139	679	0	0	0
T140	2170	0	0	0
T141	417	0	0	0
T142	535	0	0	0
T143	13434	0	0	0
T144	521	0	0	0
T145	20783	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	81067	0	0
T1	15218	128	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	4	0	0
T31	0	317	0	0
T32	0	105	0	0
T33	0	130	0	0
T35	0	145	0	0
T101	0	906	0	0
T111	0	140	0	0
T121	0	74892	0	0
T146	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	67	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T101	0	1	0	0
T111	0	1	0	0
T121	0	2	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6915920	0	0
T1	15218	9402	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6918155	0	0
T1	15218	9419	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	79	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	1	0	0
T42	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T111	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	70	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T65	0	1	0	0
T101	0	1	0	0
T111	0	1	0	0
T121	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	67	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T101	0	1	0	0
T111	0	1	0	0
T121	0	2	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	67	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T101	0	1	0	0
T111	0	1	0	0
T121	0	2	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	80970	0	0
T1	15218	127	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	3	0	0
T31	0	314	0	0
T32	0	104	0	0
T33	0	128	0	0
T35	0	143	0	0
T101	0	904	0	0
T111	0	138	0	0
T121	0	74889	0	0
T146	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2434	0	0
T1	15218	21	0	0
T2	2227	11	0	0
T3	578	1	0	0
T4	422	3	0	0
T5	501	7	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	27	0	0
T9	0	49	0	0
T10	0	33	0	0
T11	0	9	0	0
T13	581	0	0	0
T14	8246	0	0	0
T93	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	37	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T67	0	1	0	0
T75	0	1	0	0
T121	0	1	0	0
T130	0	1	0	0
T132	0	1	0	0