Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T27,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T27,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T28,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T35,T27
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T27,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T28,T32
0	1	Covered	T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T28,T32
0	1	Covered	T3,T75,T147
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T28,T32
1	-	Covered	T3,T75,T147

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T27,T42
DetectSt	168	Covered	T3,T28,T32
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T28,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T28,T32
DebounceSt->IdleSt	163	Covered	T27,T42,T63
DetectSt->IdleSt	186	Covered	T114
DetectSt->StableSt	191	Covered	T3,T28,T32
IdleSt->DebounceSt	148	Covered	T3,T27,T42
StableSt->IdleSt	206	Covered	T3,T32,T111

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T27,T42
0	1	Covered	T3,T27,T42
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T28,T32
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T27,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T28,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T132
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T27,T42
DetectSt	-	-	-	-	1	-	-	Covered	T114
DetectSt	-	-	-	-	0	1	-	Covered	T3,T28,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T75,T147
StableSt	-	-	-	-	-	-	0	Covered	T3,T28,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	76	0	0
CntIncr_A	7906335	41012	0	0
CntNoWrap_A	7906335	7292317	0	0
DetectStDropOut_A	7906335	1	0	0
DetectedOut_A	7906335	53189	0	0
DetectedPulseOut_A	7906335	35	0	0
DisabledIdleSt_A	7906335	7073812	0	0
DisabledNoDetection_A	7906335	7076060	0	0
EnterDebounceSt_A	7906335	40	0	0
EnterDetectSt_A	7906335	36	0	0
EnterStableSt_A	7906335	35	0	0
PulseIsPulse_A	7906335	35	0	0
StayInStableSt	7906335	53134	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	76	0	0
T3	578	4	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T32	0	2	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	1	0	0
T65	0	2	0	0
T111	0	2	0	0
T121	0	2	0	0
T148	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	41012	0	0
T3	578	40	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T27	0	37	0	0
T28	0	42	0	0
T32	0	82	0	0
T42	0	18	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	16	0	0
T65	0	91	0	0
T111	0	19	0	0
T121	0	29475	0	0
T148	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292317	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	173	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1	0	0
T86	95234	0	0	0
T114	81145	1	0	0
T115	1596	0	0	0
T149	694	0	0	0
T150	402	0	0	0
T151	27928	0	0	0
T152	526	0	0	0
T153	403	0	0	0
T154	504	0	0	0
T155	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	53189	0	0
T3	578	86	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T28	0	70	0	0
T32	0	245	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T65	0	41	0	0
T75	0	83	0	0
T111	0	112	0	0
T121	0	50680	0	0
T147	0	10	0	0
T148	0	45	0	0
T156	0	114	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	35	0	0
T3	578	2	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T111	0	1	0	0
T121	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T156	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7073812	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	3	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7076060	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	3	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	40	0	0
T3	578	2	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T32	0	1	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	1	0	0
T65	0	1	0	0
T111	0	1	0	0
T121	0	1	0	0
T148	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	36	0	0
T3	578	2	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T111	0	1	0	0
T121	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T156	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	35	0	0
T3	578	2	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T111	0	1	0	0
T121	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T156	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	35	0	0
T3	578	2	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T111	0	1	0	0
T121	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T156	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	53134	0	0
T3	578	83	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T28	0	68	0	0
T32	0	243	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T65	0	39	0	0
T75	0	81	0	0
T111	0	110	0	0
T121	0	50678	0	0
T147	0	9	0	0
T148	0	43	0	0
T156	0	112	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	15	0	0
T3	578	1	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T75	0	2	0	0
T86	0	1	0	0
T114	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T27,T42,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T27,T42,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T27,T28,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T42,T28
1	0	Covered	T1,T4,T5
1	1	Covered	T27,T42,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T29
0	1	Covered	T66,T162
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28,T29
0	1	Covered	T28,T29,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T28,T29
1	-	Covered	T28,T29,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T42,T28
DetectSt	168	Covered	T27,T28,T29
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T27,T28,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T28,T29
DebounceSt->IdleSt	163	Covered	T42,T63,T75
DetectSt->IdleSt	186	Covered	T66,T162
DetectSt->StableSt	191	Covered	T27,T28,T29
IdleSt->DebounceSt	148	Covered	T27,T42,T28
StableSt->IdleSt	206	Covered	T27,T28,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T27,T42,T28
0	1	Covered	T27,T42,T28
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T27,T28,T29
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T42,T28
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T28,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T86,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T42,T28
DetectSt	-	-	-	-	1	-	-	Covered	T66,T162
DetectSt	-	-	-	-	0	1	-	Covered	T27,T28,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T29,T32
StableSt	-	-	-	-	-	-	0	Covered	T27,T28,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	145	0	0
CntIncr_A	7906335	91863	0	0
CntNoWrap_A	7906335	7292248	0	0
DetectStDropOut_A	7906335	2	0	0
DetectedOut_A	7906335	70069	0	0
DetectedPulseOut_A	7906335	68	0	0
DisabledIdleSt_A	7906335	6993098	0	0
DisabledNoDetection_A	7906335	6995336	0	0
EnterDebounceSt_A	7906335	75	0	0
EnterDetectSt_A	7906335	70	0	0
EnterStableSt_A	7906335	68	0	0
PulseIsPulse_A	7906335	68	0	0
StayInStableSt	7906335	69964	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7906335	2761	0	0
gen_low_level_sva.LowLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	145	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	2	0	0
T28	0	2	0	0
T29	0	4	0	0
T30	0	4	0	0
T32	0	4	0	0
T34	752	0	0	0
T42	6182	1	0	0
T50	1705	0	0	0
T63	0	1	0	0
T65	0	2	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T111	0	4	0	0
T121	0	2	0	0
T135	528	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	91863	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	82	0	0
T28	0	42	0	0
T29	0	168	0	0
T30	0	32	0	0
T32	0	38	0	0
T34	752	0	0	0
T42	6182	19	0	0
T50	1705	0	0	0
T63	0	17	0	0
T65	0	91	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T111	0	110	0	0
T121	0	29475	0	0
T135	528	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292248	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2	0	0
T66	702	1	0	0
T70	2194	0	0	0
T81	5118	0	0	0
T82	5266	0	0	0
T101	32292	0	0	0
T162	0	1	0	0
T163	4540	0	0	0
T164	653	0	0	0
T165	791	0	0	0
T166	1964	0	0	0
T167	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	70069	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	185	0	0
T28	0	39	0	0
T29	0	162	0	0
T30	0	111	0	0
T32	0	51	0	0
T34	752	0	0	0
T42	6182	0	0	0
T50	1705	0	0	0
T65	0	1	0	0
T66	0	14	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T101	0	1106	0	0
T111	0	223	0	0
T121	0	53729	0	0
T135	528	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	68	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	1	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	752	0	0	0
T42	6182	0	0	0
T50	1705	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T101	0	2	0	0
T111	0	2	0	0
T121	0	1	0	0
T135	528	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6993098	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6995336	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	75	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	1	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	752	0	0	0
T42	6182	1	0	0
T50	1705	0	0	0
T63	0	1	0	0
T65	0	1	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T111	0	2	0	0
T121	0	1	0	0
T135	528	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	70	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	1	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	752	0	0	0
T42	6182	0	0	0
T50	1705	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T101	0	2	0	0
T111	0	2	0	0
T121	0	1	0	0
T135	528	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	68	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	1	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	752	0	0	0
T42	6182	0	0	0
T50	1705	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T101	0	2	0	0
T111	0	2	0	0
T121	0	1	0	0
T135	528	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	68	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	1	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	752	0	0	0
T42	6182	0	0	0
T50	1705	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T101	0	2	0	0
T111	0	2	0	0
T121	0	1	0	0
T135	528	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	69964	0	0
T22	25205	0	0	0
T24	14316	0	0	0
T27	5873	183	0	0
T28	0	38	0	0
T29	0	159	0	0
T30	0	108	0	0
T32	0	49	0	0
T34	752	0	0	0
T42	6182	0	0	0
T50	1705	0	0	0
T66	0	13	0	0
T78	935	0	0	0
T94	407	0	0	0
T95	542	0	0	0
T101	0	1102	0	0
T111	0	220	0	0
T121	0	53728	0	0
T135	528	0	0	0
T146	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2761	0	0
T1	15218	16	0	0
T2	2227	10	0	0
T3	578	2	0	0
T4	422	2	0	0
T5	501	6	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	29	0	0
T9	0	57	0	0
T13	581	2	0	0
T14	8246	0	0	0
T47	0	5	0	0
T93	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	31	0	0
T25	12315	0	0	0
T28	655	1	0	0
T29	1118	1	0	0
T30	0	1	0	0
T31	937	0	0	0
T32	0	2	0	0
T60	1972	0	0	0
T65	0	1	0	0
T66	0	1	0	0
T75	0	1	0	0
T111	0	1	0	0
T121	0	1	0	0
T131	0	1	0	0
T168	427	0	0	0
T169	431	0	0	0
T170	507	0	0	0
T171	422	0	0	0
T172	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T113,T86,T173
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T1,T27,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T11
1	-	Covered	T1,T27,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T1,T3,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T11
DebounceSt->IdleSt	163	Covered	T34,T42,T63
DetectSt->IdleSt	186	Covered	T113,T86,T173
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T1,T27,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T67,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T113,T86,T173
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T27,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	162	0	0
CntIncr_A	7906335	103582	0	0
CntNoWrap_A	7906335	7292231	0	0
DetectStDropOut_A	7906335	5	0	0
DetectedOut_A	7906335	66620	0	0
DetectedPulseOut_A	7906335	71	0	0
DisabledIdleSt_A	7906335	7073485	0	0
DisabledNoDetection_A	7906335	7075721	0	0
EnterDebounceSt_A	7906335	87	0	0
EnterDetectSt_A	7906335	76	0	0
EnterStableSt_A	7906335	71	0	0
PulseIsPulse_A	7906335	71	0	0
StayInStableSt	7906335	66518	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	162	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	2	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T29	0	4	0	0
T31	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T42	0	1	0	0
T63	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	103582	0	0
T1	15218	59	0	0
T2	2227	0	0	0
T3	578	20	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	54	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	82	0	0
T29	0	168	0	0
T31	0	56	0	0
T34	0	43	0	0
T35	0	98	0	0
T42	0	17	0	0
T63	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292231	0	0
T1	15218	9758	0	0
T2	2227	624	0	0
T3	578	175	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	5	0	0
T86	0	1	0	0
T113	31709	1	0	0
T162	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T176	31815	0	0	0
T177	433	0	0	0
T178	14360	0	0	0
T179	405	0	0	0
T180	526	0	0	0
T181	423	0	0	0
T182	60779	0	0	0
T183	543	0	0	0
T184	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	66620	0	0
T1	15218	129	0	0
T2	2227	0	0	0
T3	578	63	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	227	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	63	0	0
T29	0	328	0	0
T30	0	83	0	0
T31	0	316	0	0
T35	0	46	0	0
T66	0	78	0	0
T111	0	196	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	71	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T66	0	2	0	0
T111	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7073485	0	0
T1	15218	9402	0	0
T2	2227	624	0	0
T3	578	3	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7075721	0	0
T1	15218	9419	0	0
T2	2227	627	0	0
T3	578	3	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	87	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T31	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T42	0	1	0	0
T63	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	76	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T66	0	2	0	0
T111	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	71	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T66	0	2	0	0
T111	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	71	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T66	0	2	0	0
T111	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	66518	0	0
T1	15218	128	0	0
T2	2227	0	0	0
T3	578	61	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	225	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	62	0	0
T29	0	325	0	0
T30	0	81	0	0
T31	0	315	0	0
T35	0	44	0	0
T66	0	75	0	0
T111	0	194	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	40	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T132	0	1	0	0
T147	0	1	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T27,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T27,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T34,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T27,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T34,T31
0	1	Covered	T66,T133
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T34,T31
0	1	Covered	T32,T30,T185
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T34,T31
1	-	Covered	T32,T30,T185

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T27,T34
DetectSt	168	Covered	T1,T34,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T34,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T34,T31
DebounceSt->IdleSt	163	Covered	T27,T42,T63
DetectSt->IdleSt	186	Covered	T66,T133
DetectSt->StableSt	191	Covered	T1,T34,T31
IdleSt->DebounceSt	148	Covered	T1,T27,T34
StableSt->IdleSt	206	Covered	T1,T32,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T27,T34
0	1	Covered	T1,T27,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T34,T31
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T27,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T34,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T27,T34
DetectSt	-	-	-	-	1	-	-	Covered	T66,T133
DetectSt	-	-	-	-	0	1	-	Covered	T1,T34,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T30,T185
StableSt	-	-	-	-	-	-	0	Covered	T1,T34,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	72	0	0
CntIncr_A	7906335	1848	0	0
CntNoWrap_A	7906335	7292321	0	0
DetectStDropOut_A	7906335	2	0	0
DetectedOut_A	7906335	2959	0	0
DetectedPulseOut_A	7906335	32	0	0
DisabledIdleSt_A	7906335	6976990	0	0
DisabledNoDetection_A	7906335	6979237	0	0
EnterDebounceSt_A	7906335	38	0	0
EnterDetectSt_A	7906335	34	0	0
EnterStableSt_A	7906335	32	0	0
PulseIsPulse_A	7906335	32	0	0
StayInStableSt	7906335	2911	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7906335	6362	0	0
gen_low_level_sva.LowLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	72	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	1	0	0
T30	0	4	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T42	0	1	0	0
T63	0	1	0	0
T66	0	2	0	0
T131	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1848	0	0
T1	15218	59	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	37	0	0
T30	0	32	0	0
T31	0	56	0	0
T32	0	82	0	0
T34	0	43	0	0
T42	0	17	0	0
T63	0	17	0	0
T66	0	49	0	0
T131	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292321	0	0
T1	15218	9758	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2	0	0
T66	702	1	0	0
T70	2194	0	0	0
T81	5118	0	0	0
T82	5266	0	0	0
T101	32292	0	0	0
T133	0	1	0	0
T163	4540	0	0	0
T164	653	0	0	0
T165	791	0	0	0
T166	1964	0	0	0
T167	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2959	0	0
T1	15218	106	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	82	0	0
T31	0	99	0	0
T32	0	40	0	0
T34	0	42	0	0
T113	0	314	0	0
T131	0	44	0	0
T133	0	42	0	0
T185	0	225	0	0
T187	0	170	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	32	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T113	0	4	0	0
T131	0	1	0	0
T133	0	1	0	0
T185	0	2	0	0
T187	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6976990	0	0
T1	15218	9402	0	0
T2	2227	624	0	0
T3	578	3	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6979237	0	0
T1	15218	9419	0	0
T2	2227	627	0	0
T3	578	3	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	38	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	1	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T42	0	1	0	0
T63	0	1	0	0
T66	0	1	0	0
T131	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	34	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T66	0	1	0	0
T131	0	1	0	0
T133	0	2	0	0
T185	0	2	0	0
T187	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	32	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T113	0	4	0	0
T131	0	1	0	0
T133	0	1	0	0
T185	0	2	0	0
T187	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	32	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T113	0	4	0	0
T131	0	1	0	0
T133	0	1	0	0
T185	0	2	0	0
T187	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2911	0	0
T1	15218	104	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T30	0	79	0	0
T31	0	97	0	0
T32	0	39	0	0
T34	0	40	0	0
T113	0	309	0	0
T131	0	42	0	0
T133	0	40	0	0
T185	0	222	0	0
T187	0	167	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6362	0	0
T1	15218	24	0	0
T2	2227	14	0	0
T3	578	0	0	0
T4	422	2	0	0
T5	501	3	0	0
T6	8611	28	0	0
T7	7367	29	0	0
T8	249850	34	0	0
T9	0	45	0	0
T13	581	0	0	0
T14	8246	22	0	0
T46	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	16	0	0
T30	0	1	0	0
T32	11068	1	0	0
T65	634	0	0	0
T76	0	1	0	0
T113	0	3	0	0
T138	770	0	0	0
T139	679	0	0	0
T161	0	1	0	0
T175	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T189	0	1	0	0
T190	403	0	0	0
T191	522	0	0	0
T192	505	0	0	0
T193	51147	0	0	0
T194	6669	0	0	0
T195	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T71,T86,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T11
0	1	Covered	T11,T27,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T11
1	-	Covered	T11,T27,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T11
DetectSt	168	Covered	T1,T3,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T11
DebounceSt->IdleSt	163	Covered	T42,T63,T32
DetectSt->IdleSt	186	Covered	T71,T86,T196
DetectSt->StableSt	191	Covered	T1,T3,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T11
StableSt->IdleSt	206	Covered	T1,T11,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T11
0	1	Covered	T1,T3,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T118,T197
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T71,T86,T196
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T27,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	150	0	0
CntIncr_A	7906335	160270	0	0
CntNoWrap_A	7906335	7292243	0	0
DetectStDropOut_A	7906335	3	0	0
DetectedOut_A	7906335	69550	0	0
DetectedPulseOut_A	7906335	69	0	0
DisabledIdleSt_A	7906335	6925347	0	0
DisabledNoDetection_A	7906335	6927581	0	0
EnterDebounceSt_A	7906335	79	0	0
EnterDetectSt_A	7906335	72	0	0
EnterStableSt_A	7906335	69	0	0
PulseIsPulse_A	7906335	69	0	0
StayInStableSt	7906335	69448	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	150	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	2	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	4	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	4	0	0
T31	0	2	0	0
T32	0	3	0	0
T42	0	1	0	0
T63	0	1	0	0
T65	0	2	0	0
T111	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	160270	0	0
T1	15218	59	0	0
T2	2227	0	0	0
T3	578	20	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	108	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	74	0	0
T31	0	56	0	0
T32	0	38	0	0
T42	0	19	0	0
T63	0	16	0	0
T65	0	91	0	0
T111	0	110	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292243	0	0
T1	15218	9758	0	0
T2	2227	624	0	0
T3	578	175	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	3	0	0
T71	3175	1	0	0
T86	0	1	0	0
T147	74843	0	0	0
T185	15801	0	0	0
T196	0	1	0	0
T198	1074	0	0	0
T199	6609	0	0	0
T200	522	0	0	0
T201	4404	0	0	0
T202	733	0	0	0
T203	1169	0	0	0
T204	686	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	69550	0	0
T1	15218	209	0	0
T2	2227	0	0	0
T3	578	64	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	191	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	195	0	0
T31	0	141	0	0
T32	0	10	0	0
T33	0	272	0	0
T65	0	134	0	0
T101	0	905	0	0
T111	0	151	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	69	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T65	0	1	0	0
T101	0	1	0	0
T111	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6925347	0	0
T1	15218	9402	0	0
T2	2227	624	0	0
T3	578	3	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6927581	0	0
T1	15218	9419	0	0
T2	2227	627	0	0
T3	578	3	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	79	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T42	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T111	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	72	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T65	0	1	0	0
T101	0	1	0	0
T111	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	69	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T65	0	1	0	0
T101	0	1	0	0
T111	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	69	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	1	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	2	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T65	0	1	0	0
T101	0	1	0	0
T111	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	69448	0	0
T1	15218	207	0	0
T2	2227	0	0	0
T3	578	62	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T11	0	188	0	0
T13	581	0	0	0
T14	8246	0	0	0
T27	0	192	0	0
T31	0	140	0	0
T32	0	9	0	0
T33	0	269	0	0
T65	0	132	0	0
T101	0	903	0	0
T111	0	147	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	36	0	0
T11	3368	1	0	0
T12	2846	0	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	758	0	0	0
T52	495	0	0	0
T53	494	0	0	0
T57	1331	0	0	0
T58	539	0	0	0
T67	0	1	0	0
T75	0	1	0	0
T97	409	0	0	0
T132	0	1	0	0
T147	0	2	0	0
T185	0	1	0	0
T205	578	0	0	0
T206	403	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T42,T31,T63

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T42,T31,T63

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T31,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T42,T31
1	0	Covered	T1,T4,T5
1	1	Covered	T42,T31,T63

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T33
0	1	Covered	T32,T33,T187
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T32,T33
1	-	Covered	T32,T33,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T31,T63
DetectSt	168	Covered	T31,T32,T33
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T31,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T32,T33
DebounceSt->IdleSt	163	Covered	T42,T63,T133
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T31,T32,T33
IdleSt->DebounceSt	148	Covered	T42,T31,T63
StableSt->IdleSt	206	Covered	T32,T33,T131

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T31,T63
0	1	Covered	T42,T31,T63
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T33
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T31,T63
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T133
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T31,T63
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T31,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T187
StableSt	-	-	-	-	-	-	0	Covered	T31,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	73	0	0
CntIncr_A	7906335	31395	0	0
CntNoWrap_A	7906335	7292320	0	0
DetectStDropOut_A	7906335	0	0	0
DetectedOut_A	7906335	2632	0	0
DetectedPulseOut_A	7906335	35	0	0
DisabledIdleSt_A	7906335	6996072	0	0
DisabledNoDetection_A	7906335	6998318	0	0
EnterDebounceSt_A	7906335	38	0	0
EnterDetectSt_A	7906335	35	0	0
EnterStableSt_A	7906335	35	0	0
PulseIsPulse_A	7906335	35	0	0
StayInStableSt	7906335	2577	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7906335	5966	0	0
gen_low_level_sva.LowLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	73	0	0
T31	0	2	0	0
T32	0	8	0	0
T33	0	2	0	0
T42	6182	1	0	0
T51	136984	0	0	0
T63	0	1	0	0
T71	0	2	0	0
T94	407	0	0	0
T95	542	0	0	0
T96	504	0	0	0
T121	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T207	0	2	0	0
T208	423	0	0	0
T209	423	0	0	0
T210	522	0	0	0
T211	526	0	0	0
T212	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	31395	0	0
T31	0	56	0	0
T32	0	202	0	0
T33	0	94	0	0
T42	6182	19	0	0
T51	136984	0	0	0
T63	0	16	0	0
T71	0	91	0	0
T94	407	0	0	0
T95	542	0	0	0
T96	504	0	0	0
T121	0	29475	0	0
T131	0	25	0	0
T132	0	86	0	0
T207	0	19	0	0
T208	423	0	0	0
T209	423	0	0	0
T210	522	0	0	0
T211	526	0	0	0
T212	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7292320	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2632	0	0
T26	19358	0	0	0
T29	1118	0	0	0
T31	937	100	0	0
T32	0	491	0	0
T33	0	43	0	0
T60	1972	0	0	0
T61	2564	0	0	0
T71	0	43	0	0
T98	25440	0	0	0
T121	0	42	0	0
T131	0	44	0	0
T132	0	39	0	0
T172	426	0	0	0
T185	0	115	0	0
T187	0	173	0	0
T207	0	39	0	0
T213	413	0	0	0
T214	4402	0	0	0
T215	26744	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	35	0	0
T26	19358	0	0	0
T29	1118	0	0	0
T31	937	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T60	1972	0	0	0
T61	2564	0	0	0
T71	0	1	0	0
T98	25440	0	0	0
T121	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T172	426	0	0	0
T185	0	1	0	0
T187	0	1	0	0
T207	0	1	0	0
T213	413	0	0	0
T214	4402	0	0	0
T215	26744	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6996072	0	0
T1	15218	9402	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6998318	0	0
T1	15218	9419	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	38	0	0
T31	0	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T42	6182	1	0	0
T51	136984	0	0	0
T63	0	1	0	0
T71	0	1	0	0
T94	407	0	0	0
T95	542	0	0	0
T96	504	0	0	0
T121	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T207	0	1	0	0
T208	423	0	0	0
T209	423	0	0	0
T210	522	0	0	0
T211	526	0	0	0
T212	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	35	0	0
T26	19358	0	0	0
T29	1118	0	0	0
T31	937	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T60	1972	0	0	0
T61	2564	0	0	0
T71	0	1	0	0
T98	25440	0	0	0
T121	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T172	426	0	0	0
T185	0	1	0	0
T187	0	1	0	0
T207	0	1	0	0
T213	413	0	0	0
T214	4402	0	0	0
T215	26744	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	35	0	0
T26	19358	0	0	0
T29	1118	0	0	0
T31	937	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T60	1972	0	0	0
T61	2564	0	0	0
T71	0	1	0	0
T98	25440	0	0	0
T121	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T172	426	0	0	0
T185	0	1	0	0
T187	0	1	0	0
T207	0	1	0	0
T213	413	0	0	0
T214	4402	0	0	0
T215	26744	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	35	0	0
T26	19358	0	0	0
T29	1118	0	0	0
T31	937	1	0	0
T32	0	4	0	0
T33	0	1	0	0
T60	1972	0	0	0
T61	2564	0	0	0
T71	0	1	0	0
T98	25440	0	0	0
T121	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T172	426	0	0	0
T185	0	1	0	0
T187	0	1	0	0
T207	0	1	0	0
T213	413	0	0	0
T214	4402	0	0	0
T215	26744	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2577	0	0
T26	19358	0	0	0
T29	1118	0	0	0
T31	937	98	0	0
T32	0	485	0	0
T33	0	42	0	0
T60	1972	0	0	0
T61	2564	0	0	0
T71	0	41	0	0
T98	25440	0	0	0
T121	0	40	0	0
T131	0	42	0	0
T132	0	37	0	0
T172	426	0	0	0
T185	0	113	0	0
T187	0	172	0	0
T207	0	37	0	0
T213	413	0	0	0
T214	4402	0	0	0
T215	26744	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	5966	0	0
T1	15218	22	0	0
T2	2227	13	0	0
T3	578	0	0	0
T4	422	3	0	0
T5	501	6	0	0
T6	8611	23	0	0
T7	7367	36	0	0
T8	249850	23	0	0
T9	0	48	0	0
T13	581	0	0	0
T14	8246	21	0	0
T46	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	15	0	0
T32	11068	2	0	0
T33	0	1	0	0
T65	634	0	0	0
T105	0	1	0	0
T113	0	1	0	0
T116	0	1	0	0
T118	0	1	0	0
T138	770	0	0	0
T139	679	0	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T187	0	1	0	0
T190	403	0	0	0
T191	522	0	0	0
T192	505	0	0	0
T193	51147	0	0	0
T194	6669	0	0	0
T195	402	0	0	0