Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T14
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T14
1	0	Covered	T6,T7,T36
1	1	Covered	T6,T7,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T14
0	1	Covered	T7,T41,T25
1	0	Covered	T7,T23,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T14,T36
0	1	Covered	T6,T14,T36
1	0	Covered	T63,T232

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T14,T36
1	-	Covered	T6,T14,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T14
DetectSt	168	Covered	T6,T7,T14
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T14,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T14
DebounceSt->IdleSt	163	Covered	T14,T42,T63
DetectSt->IdleSt	186	Covered	T7,T23,T41
DetectSt->StableSt	191	Covered	T6,T14,T36
IdleSt->DebounceSt	148	Covered	T6,T7,T14
StableSt->IdleSt	206	Covered	T6,T14,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T14
0	1	Covered	T6,T7,T14
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T14
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T14
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T42,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T14
DetectSt	-	-	-	-	1	-	-	Covered	T7,T23,T41
DetectSt	-	-	-	-	0	1	-	Covered	T6,T14,T36
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T14
StableSt	-	-	-	-	-	-	1	Covered	T6,T14,T36
StableSt	-	-	-	-	-	-	0	Covered	T6,T14,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	3069	0	0
CntIncr_A	7906335	118056	0	0
CntNoWrap_A	7906335	7289324	0	0
DetectStDropOut_A	7906335	396	0	0
DetectedOut_A	7906335	83763	0	0
DetectedPulseOut_A	7906335	916	0	0
DisabledIdleSt_A	7906335	6799848	0	0
DisabledNoDetection_A	7906335	6801900	0	0
EnterDebounceSt_A	7906335	1545	0	0
EnterDetectSt_A	7906335	1525	0	0
EnterStableSt_A	7906335	916	0	0
PulseIsPulse_A	7906335	916	0	0
StayInStableSt	7906335	82693	0	0
gen_high_event_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	760	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	3069	0	0
T6	8611	12	0	0
T7	7367	28	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	15	0	0
T18	686	0	0	0
T23	0	24	0	0
T24	0	34	0	0
T25	0	26	0	0
T36	0	56	0	0
T41	0	52	0	0
T42	0	15	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	118056	0	0
T6	8611	234	0	0
T7	7367	910	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	3571	0	0
T18	686	0	0	0
T23	0	656	0	0
T24	0	850	0	0
T25	0	831	0	0
T36	0	2632	0	0
T41	0	1275	0	0
T42	0	227	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1392	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7289324	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8193	0	0
T7	7367	6938	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7830	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	396	0	0
T7	7367	5	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T25	0	7	0	0
T41	0	26	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	1	0	0
T79	0	27	0	0
T81	0	17	0	0
T82	0	4	0	0
T83	0	18	0	0
T84	0	18	0	0
T85	0	14	0	0
T93	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	83763	0	0
T6	8611	221	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	18	0	0
T18	686	0	0	0
T24	0	1151	0	0
T36	0	2111	0	0
T42	0	287	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1713	0	0
T63	0	305	0	0
T98	0	1745	0	0
T233	0	290	0	0
T234	0	3643	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	916	0	0
T6	8611	6	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T24	0	17	0	0
T36	0	28	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	24	0	0
T63	0	5	0	0
T98	0	19	0	0
T233	0	7	0	0
T234	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6799848	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	4917	0	0
T7	7367	3513	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6801900	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	4917	0	0
T7	7367	3513	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1545	0	0
T6	8611	6	0	0
T7	7367	14	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	12	0	0
T18	686	0	0	0
T23	0	12	0	0
T24	0	17	0	0
T25	0	13	0	0
T36	0	28	0	0
T41	0	26	0	0
T42	0	9	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1525	0	0
T6	8611	6	0	0
T7	7367	14	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T23	0	12	0	0
T24	0	17	0	0
T25	0	13	0	0
T36	0	28	0	0
T41	0	26	0	0
T42	0	6	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	916	0	0
T6	8611	6	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T24	0	17	0	0
T36	0	28	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	24	0	0
T63	0	5	0	0
T98	0	19	0	0
T233	0	7	0	0
T234	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	916	0	0
T6	8611	6	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T24	0	17	0	0
T36	0	28	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	24	0	0
T63	0	5	0	0
T98	0	19	0	0
T233	0	7	0	0
T234	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	82693	0	0
T6	8611	214	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	14	0	0
T18	686	0	0	0
T24	0	1132	0	0
T36	0	2080	0	0
T42	0	282	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1688	0	0
T63	0	300	0	0
T98	0	1720	0	0
T233	0	282	0	0
T234	0	3613	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	760	0	0
T6	8611	5	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T24	0	15	0	0
T36	0	25	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	23	0	0
T63	0	4	0	0
T98	0	13	0	0
T233	0	6	0	0
T234	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T8
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T10
0	1	Covered	T1,T62,T80
1	0	Covered	T42,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T37
0	1	Covered	T9,T10,T37
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T37
1	-	Covered	T9,T10,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T10
DetectSt	168	Covered	T1,T9,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T10,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T10
DebounceSt->IdleSt	163	Covered	T9,T11,T36
DetectSt->IdleSt	186	Covered	T1,T42,T62
DetectSt->StableSt	191	Covered	T9,T10,T37
IdleSt->DebounceSt	148	Covered	T1,T9,T10
StableSt->IdleSt	206	Covered	T9,T10,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T10
0	1	Covered	T1,T9,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T11,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T1,T42,T62
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T37
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T10
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T37
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	1061	0	0
CntIncr_A	7906335	56092	0	0
CntNoWrap_A	7906335	7291332	0	0
DetectStDropOut_A	7906335	100	0	0
DetectedOut_A	7906335	16814	0	0
DetectedPulseOut_A	7906335	380	0	0
DisabledIdleSt_A	7906335	6923953	0	0
DisabledNoDetection_A	7906335	6925457	0	0
EnterDebounceSt_A	7906335	578	0	0
EnterDetectSt_A	7906335	484	0	0
EnterStableSt_A	7906335	380	0	0
PulseIsPulse_A	7906335	380	0	0
StayInStableSt	7906335	16381	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	325	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1061	0	0
T1	15218	8	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	0	4	0	0
T10	0	2	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	581	0	0	0
T14	8246	0	0	0
T21	0	1	0	0
T22	0	14	0	0
T24	0	6	0	0
T36	0	8	0	0
T37	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	56092	0	0
T1	15218	171	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	0	65	0	0
T10	0	25	0	0
T11	0	20	0	0
T12	0	25	0	0
T13	581	0	0	0
T14	8246	0	0	0
T21	0	45	0	0
T22	0	1296	0	0
T24	0	114	0	0
T36	0	312	0	0
T37	0	268	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7291332	0	0
T1	15218	9752	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	100	0	0
T1	15218	4	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T62	0	2	0	0
T80	0	7	0	0
T86	0	3	0	0
T87	0	4	0	0
T88	0	15	0	0
T89	0	2	0	0
T90	0	7	0	0
T91	0	1	0	0
T92	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	16814	0	0
T9	8652	4	0	0
T10	5718	3	0	0
T11	3368	0	0	0
T12	2846	3	0	0
T22	0	28	0	0
T24	0	230	0	0
T26	0	108	0	0
T36	0	217	0	0
T37	18637	44	0	0
T42	0	113	0	0
T52	495	0	0	0
T53	494	0	0	0
T57	1331	0	0	0
T59	0	119	0	0
T93	423	0	0	0
T97	409	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	380	0	0
T9	8652	1	0	0
T10	5718	1	0	0
T11	3368	0	0	0
T12	2846	1	0	0
T22	0	6	0	0
T24	0	3	0	0
T26	0	2	0	0
T36	0	3	0	0
T37	18637	2	0	0
T42	0	1	0	0
T52	495	0	0	0
T53	494	0	0	0
T57	1331	0	0	0
T59	0	2	0	0
T93	423	0	0	0
T97	409	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6923953	0	0
T1	15218	9322	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	7985	0	0
T7	7367	6966	0	0
T8	249850	244241	0	0
T13	581	180	0	0
T14	8246	7827	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6925457	0	0
T1	15218	9338	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	7986	0	0
T7	7367	6967	0	0
T8	249850	244253	0	0
T13	581	181	0	0
T14	8246	7828	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	578	0	0
T1	15218	4	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T21	0	1	0	0
T22	0	8	0	0
T24	0	3	0	0
T36	0	5	0	0
T37	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	484	0	0
T1	15218	4	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	6	0	0
T24	0	3	0	0
T36	0	3	0	0
T37	0	2	0	0
T42	0	3	0	0
T59	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	380	0	0
T9	8652	1	0	0
T10	5718	1	0	0
T11	3368	0	0	0
T12	2846	1	0	0
T22	0	6	0	0
T24	0	3	0	0
T26	0	2	0	0
T36	0	3	0	0
T37	18637	2	0	0
T42	0	1	0	0
T52	495	0	0	0
T53	494	0	0	0
T57	1331	0	0	0
T59	0	2	0	0
T93	423	0	0	0
T97	409	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	380	0	0
T9	8652	1	0	0
T10	5718	1	0	0
T11	3368	0	0	0
T12	2846	1	0	0
T22	0	6	0	0
T24	0	3	0	0
T26	0	2	0	0
T36	0	3	0	0
T37	18637	2	0	0
T42	0	1	0	0
T52	495	0	0	0
T53	494	0	0	0
T57	1331	0	0	0
T59	0	2	0	0
T93	423	0	0	0
T97	409	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	16381	0	0
T9	8652	3	0	0
T10	5718	2	0	0
T11	3368	0	0	0
T12	2846	2	0	0
T22	0	22	0	0
T24	0	227	0	0
T26	0	106	0	0
T36	0	211	0	0
T37	18637	42	0	0
T42	0	112	0	0
T52	495	0	0	0
T53	494	0	0	0
T57	1331	0	0	0
T59	0	117	0	0
T93	423	0	0	0
T97	409	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	325	0	0
T9	8652	1	0	0
T10	5718	1	0	0
T11	3368	0	0	0
T12	2846	1	0	0
T22	0	6	0	0
T24	0	3	0	0
T26	0	2	0	0
T37	18637	2	0	0
T42	0	1	0	0
T52	495	0	0	0
T53	494	0	0	0
T57	1331	0	0	0
T59	0	2	0	0
T93	423	0	0	0
T97	409	0	0	0
T98	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T14
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T14
1	0	Covered	T6,T7,T36
1	1	Covered	T6,T7,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T14
0	1	Covered	T7,T23,T41
1	0	Covered	T7,T23,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T14,T36
0	1	Covered	T6,T14,T36
1	0	Covered	T68,T235,T236

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T14,T36
1	-	Covered	T6,T14,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T14
DetectSt	168	Covered	T6,T7,T14
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T14,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T14
DebounceSt->IdleSt	163	Covered	T14,T42,T63
DetectSt->IdleSt	186	Covered	T7,T23,T41
DetectSt->StableSt	191	Covered	T6,T14,T36
IdleSt->DebounceSt	148	Covered	T6,T7,T14
StableSt->IdleSt	206	Covered	T6,T14,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T14
0	1	Covered	T6,T7,T14
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T14
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T14
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T42,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T14
DetectSt	-	-	-	-	1	-	-	Covered	T7,T23,T41
DetectSt	-	-	-	-	0	1	-	Covered	T6,T14,T36
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T14
StableSt	-	-	-	-	-	-	1	Covered	T6,T14,T36
StableSt	-	-	-	-	-	-	0	Covered	T6,T14,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	2985	0	0
CntIncr_A	7906335	111322	0	0
CntNoWrap_A	7906335	7289408	0	0
DetectStDropOut_A	7906335	423	0	0
DetectedOut_A	7906335	71591	0	0
DetectedPulseOut_A	7906335	867	0	0
DisabledIdleSt_A	7906335	6808428	0	0
DisabledNoDetection_A	7906335	6810535	0	0
EnterDebounceSt_A	7906335	1499	0	0
EnterDetectSt_A	7906335	1487	0	0
EnterStableSt_A	7906335	867	0	0
PulseIsPulse_A	7906335	867	0	0
StayInStableSt	7906335	70625	0	0
gen_high_event_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	747	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2985	0	0
T6	8611	38	0	0
T7	7367	22	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	19	0	0
T18	686	0	0	0
T23	0	22	0	0
T24	0	50	0	0
T25	0	24	0	0
T36	0	16	0	0
T41	0	36	0	0
T42	0	16	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	111322	0	0
T6	8611	950	0	0
T7	7367	716	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	3989	0	0
T18	686	0	0	0
T23	0	602	0	0
T24	0	1000	0	0
T25	0	765	0	0
T36	0	640	0	0
T41	0	874	0	0
T42	0	324	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	453	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7289408	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8167	0	0
T7	7367	6944	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7826	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	423	0	0
T7	7367	6	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	1	0	0
T25	0	7	0	0
T41	0	18	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	1	0	0
T64	0	13	0	0
T68	0	16	0	0
T79	0	23	0	0
T81	0	26	0	0
T93	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	71591	0	0
T6	8611	312	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	42	0	0
T18	686	0	0	0
T24	0	2222	0	0
T36	0	201	0	0
T42	0	367	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	279	0	0
T98	0	1125	0	0
T194	0	554	0	0
T233	0	1728	0	0
T234	0	1149	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	867	0	0
T6	8611	19	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	7	0	0
T18	686	0	0	0
T24	0	25	0	0
T36	0	8	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	5	0	0
T98	0	11	0	0
T194	0	13	0	0
T233	0	15	0	0
T234	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6808428	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	4880	0	0
T7	7367	3513	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6810535	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	4880	0	0
T7	7367	3513	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1499	0	0
T6	8611	19	0	0
T7	7367	11	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	13	0	0
T18	686	0	0	0
T23	0	11	0	0
T24	0	25	0	0
T25	0	12	0	0
T36	0	8	0	0
T41	0	18	0	0
T42	0	9	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1487	0	0
T6	8611	19	0	0
T7	7367	11	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	7	0	0
T18	686	0	0	0
T23	0	11	0	0
T24	0	25	0	0
T25	0	12	0	0
T36	0	8	0	0
T41	0	18	0	0
T42	0	7	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	867	0	0
T6	8611	19	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	7	0	0
T18	686	0	0	0
T24	0	25	0	0
T36	0	8	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	5	0	0
T98	0	11	0	0
T194	0	13	0	0
T233	0	15	0	0
T234	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	867	0	0
T6	8611	19	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	7	0	0
T18	686	0	0	0
T24	0	25	0	0
T36	0	8	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	5	0	0
T98	0	11	0	0
T194	0	13	0	0
T233	0	15	0	0
T234	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	70625	0	0
T6	8611	292	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	35	0	0
T18	686	0	0	0
T24	0	2195	0	0
T36	0	193	0	0
T42	0	362	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	274	0	0
T98	0	1110	0	0
T194	0	541	0	0
T233	0	1709	0	0
T234	0	1139	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	747	0	0
T6	8611	18	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	7	0	0
T18	686	0	0	0
T24	0	23	0	0
T36	0	8	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	5	0	0
T98	0	7	0	0
T194	0	13	0	0
T233	0	11	0	0
T234	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T21,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T21,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T21,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T14
1	0	Covered	T1,T2,T6
1	1	Covered	T6,T21,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T24
0	1	Covered	T42,T178,T86
1	0	Covered	T42,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T21,T24
0	1	Covered	T6,T21,T24
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T21,T24
1	-	Covered	T6,T21,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T21,T24
DetectSt	168	Covered	T6,T21,T24
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T21,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T21,T24
DebounceSt->IdleSt	163	Covered	T22,T42,T62
DetectSt->IdleSt	186	Covered	T42,T63,T178
DetectSt->StableSt	191	Covered	T6,T21,T24
IdleSt->DebounceSt	148	Covered	T6,T21,T24
StableSt->IdleSt	206	Covered	T6,T21,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T21,T24
0	1	Covered	T6,T21,T24
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T21,T24
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T21,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T21,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T62,T26
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T21,T24
DetectSt	-	-	-	-	1	-	-	Covered	T42,T63,T178
DetectSt	-	-	-	-	0	1	-	Covered	T6,T21,T24
DetectSt	-	-	-	-	0	0	-	Covered	T6,T21,T24
StableSt	-	-	-	-	-	-	1	Covered	T6,T21,T24
StableSt	-	-	-	-	-	-	0	Covered	T6,T21,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	851	0	0
CntIncr_A	7906335	47216	0	0
CntNoWrap_A	7906335	7291542	0	0
DetectStDropOut_A	7906335	35	0	0
DetectedOut_A	7906335	12697	0	0
DetectedPulseOut_A	7906335	368	0	0
DisabledIdleSt_A	7906335	6931158	0	0
DisabledNoDetection_A	7906335	6932757	0	0
EnterDebounceSt_A	7906335	445	0	0
EnterDetectSt_A	7906335	406	0	0
EnterStableSt_A	7906335	368	0	0
PulseIsPulse_A	7906335	368	0	0
StayInStableSt	7906335	12310	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	347	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	851	0	0
T6	8611	2	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	2	0	0
T22	0	11	0	0
T24	0	4	0	0
T26	0	5	0	0
T42	0	8	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	7	0	0
T63	0	8	0	0
T98	0	4	0	0
T215	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	47216	0	0
T6	8611	47	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	74	0	0
T22	0	703	0	0
T24	0	74	0	0
T26	0	340	0	0
T42	0	185	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	298	0	0
T63	0	140	0	0
T98	0	122	0	0
T215	0	405	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7291542	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8203	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	35	0	0
T42	6182	1	0	0
T51	136984	0	0	0
T86	0	2	0	0
T87	0	2	0	0
T89	0	2	0	0
T94	407	0	0	0
T95	542	0	0	0
T96	504	0	0	0
T161	0	5	0	0
T178	0	4	0	0
T208	423	0	0	0
T209	423	0	0	0
T210	522	0	0	0
T211	526	0	0	0
T212	402	0	0	0
T237	0	5	0	0
T238	0	10	0	0
T239	0	1	0	0
T240	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	12697	0	0
T6	8611	28	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	50	0	0
T22	0	338	0	0
T24	0	156	0	0
T26	0	80	0	0
T42	0	113	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	14	0	0
T63	0	74	0	0
T98	0	140	0	0
T215	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	368	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	1	0	0
T22	0	5	0	0
T24	0	2	0	0
T26	0	2	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	3	0	0
T63	0	1	0	0
T98	0	2	0	0
T215	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6931158	0	0
T1	15218	9322	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	7894	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7803	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6932757	0	0
T1	15218	9338	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	7895	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7804	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	445	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	1	0	0
T22	0	6	0	0
T24	0	2	0	0
T26	0	3	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	4	0	0
T63	0	5	0	0
T98	0	2	0	0
T215	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	406	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	1	0	0
T22	0	5	0	0
T24	0	2	0	0
T26	0	2	0	0
T42	0	3	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	3	0	0
T63	0	3	0	0
T98	0	2	0	0
T215	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	368	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	1	0	0
T22	0	5	0	0
T24	0	2	0	0
T26	0	2	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	3	0	0
T63	0	1	0	0
T98	0	2	0	0
T215	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	368	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	1	0	0
T22	0	5	0	0
T24	0	2	0	0
T26	0	2	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	3	0	0
T63	0	1	0	0
T98	0	2	0	0
T215	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	12310	0	0
T6	8611	27	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	49	0	0
T22	0	333	0	0
T24	0	153	0	0
T26	0	78	0	0
T42	0	112	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	11	0	0
T63	0	73	0	0
T98	0	138	0	0
T215	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	347	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	1	0	0
T22	0	5	0	0
T24	0	1	0	0
T26	0	2	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T62	0	3	0	0
T98	0	2	0	0
T143	0	3	0	0
T215	0	3	0	0
T234	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T14
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T14
1	0	Covered	T6,T36,T23
1	1	Covered	T6,T7,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T14
0	1	Covered	T6,T41,T42
1	0	Covered	T6,T42,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T14,T36
0	1	Covered	T7,T14,T36
1	0	Covered	T6,T241

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T7,T14
1	-	Covered	T7,T14,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T14
DetectSt	168	Covered	T6,T7,T14
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T7,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T14
DebounceSt->IdleSt	163	Covered	T14,T42,T63
DetectSt->IdleSt	186	Covered	T6,T41,T42
DetectSt->StableSt	191	Covered	T6,T7,T14
IdleSt->DebounceSt	148	Covered	T6,T7,T14
StableSt->IdleSt	206	Covered	T6,T7,T14

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T14
0	1	Covered	T6,T7,T14
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T14
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T14
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T42,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T14
DetectSt	-	-	-	-	1	-	-	Covered	T6,T41,T42
DetectSt	-	-	-	-	0	1	-	Covered	T6,T7,T14
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T14
StableSt	-	-	-	-	-	-	1	Covered	T6,T7,T14
StableSt	-	-	-	-	-	-	0	Covered	T7,T14,T36
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	2926	0	0
CntIncr_A	7906335	108048	0	0
CntNoWrap_A	7906335	7289467	0	0
DetectStDropOut_A	7906335	371	0	0
DetectedOut_A	7906335	86149	0	0
DetectedPulseOut_A	7906335	952	0	0
DisabledIdleSt_A	7906335	6798147	0	0
DisabledNoDetection_A	7906335	6800238	0	0
EnterDebounceSt_A	7906335	1473	0	0
EnterDetectSt_A	7906335	1454	0	0
EnterStableSt_A	7906335	952	0	0
PulseIsPulse_A	7906335	952	0	0
StayInStableSt	7906335	85081	0	0
gen_high_event_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	832	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	2926	0	0
T6	8611	18	0	0
T7	7367	30	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	14	0	0
T18	686	0	0	0
T23	0	24	0	0
T24	0	26	0	0
T25	0	24	0	0
T36	0	12	0	0
T41	0	30	0	0
T42	0	16	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	108048	0	0
T6	8611	535	0	0
T7	7367	900	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	3372	0	0
T18	686	0	0	0
T23	0	636	0	0
T24	0	767	0	0
T25	0	708	0	0
T36	0	348	0	0
T41	0	732	0	0
T42	0	318	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	522	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7289467	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8187	0	0
T7	7367	6936	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7831	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	371	0	0
T6	8611	3	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T41	0	15	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	1	0	0
T68	0	10	0	0
T79	0	23	0	0
T81	0	21	0	0
T82	0	2	0	0
T83	0	15	0	0
T84	0	27	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	86149	0	0
T6	8611	1	0	0
T7	7367	1559	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	39	0	0
T18	686	0	0	0
T23	0	178	0	0
T24	0	766	0	0
T25	0	1287	0	0
T36	0	284	0	0
T42	0	370	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	311	0	0
T98	0	1367	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	952	0	0
T6	8611	1	0	0
T7	7367	15	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T23	0	12	0	0
T24	0	13	0	0
T25	0	12	0	0
T36	0	6	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	9	0	0
T98	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6798147	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	5026	0	0
T7	7367	2015	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	2015	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6800238	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	5027	0	0
T7	7367	2015	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	2015	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1473	0	0
T6	8611	9	0	0
T7	7367	15	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	11	0	0
T18	686	0	0	0
T23	0	12	0	0
T24	0	13	0	0
T25	0	12	0	0
T36	0	6	0	0
T41	0	15	0	0
T42	0	9	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1454	0	0
T6	8611	9	0	0
T7	7367	15	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T23	0	12	0	0
T24	0	13	0	0
T25	0	12	0	0
T36	0	6	0	0
T41	0	15	0	0
T42	0	7	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	952	0	0
T6	8611	1	0	0
T7	7367	15	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T23	0	12	0	0
T24	0	13	0	0
T25	0	12	0	0
T36	0	6	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	9	0	0
T98	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	952	0	0
T6	8611	1	0	0
T7	7367	15	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T23	0	12	0	0
T24	0	13	0	0
T25	0	12	0	0
T36	0	6	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	9	0	0
T98	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	85081	0	0
T7	7367	1544	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	35	0	0
T18	686	0	0	0
T23	0	165	0	0
T24	0	752	0	0
T25	0	1273	0	0
T36	0	278	0	0
T42	0	365	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	302	0	0
T63	0	327	0	0
T93	423	0	0	0
T98	0	1352	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	832	0	0
T7	7367	15	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T23	0	11	0	0
T24	0	12	0	0
T25	0	10	0	0
T36	0	6	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	9	0	0
T63	0	5	0	0
T93	423	0	0	0
T98	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T7,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T7,T37

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T7,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T7,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T37
0	1	Covered	T242,T88,T134
1	0	Covered	T42,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T37
0	1	Covered	T1,T7,T37
1	0	Covered	T42

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T37
1	-	Covered	T1,T7,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T37
DetectSt	168	Covered	T1,T7,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T7,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T37
DebounceSt->IdleSt	163	Covered	T37,T22,T42
DetectSt->IdleSt	186	Covered	T42,T63,T242
DetectSt->StableSt	191	Covered	T1,T7,T37
IdleSt->DebounceSt	148	Covered	T1,T7,T37
StableSt->IdleSt	206	Covered	T1,T7,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T37
0	1	Covered	T1,T7,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T22,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T37
DetectSt	-	-	-	-	1	-	-	Covered	T42,T63,T242
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T37
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T37
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T37
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	804	0	0
CntIncr_A	7906335	44473	0	0
CntNoWrap_A	7906335	7291589	0	0
DetectStDropOut_A	7906335	62	0	0
DetectedOut_A	7906335	15289	0	0
DetectedPulseOut_A	7906335	316	0	0
DisabledIdleSt_A	7906335	6918204	0	0
DisabledNoDetection_A	7906335	6919794	0	0
EnterDebounceSt_A	7906335	422	0	0
EnterDetectSt_A	7906335	382	0	0
EnterStableSt_A	7906335	316	0	0
PulseIsPulse_A	7906335	316	0	0
StayInStableSt	7906335	14952	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	804	0	0
T1	15218	4	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	6	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	15	0	0
T23	0	2	0	0
T24	0	2	0	0
T25	0	2	0	0
T26	0	5	0	0
T37	0	15	0	0
T42	0	8	0	0
T62	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	44473	0	0
T1	15218	66	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	204	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	1031	0	0
T23	0	58	0	0
T24	0	67	0	0
T25	0	42	0	0
T26	0	250	0	0
T37	0	1059	0	0
T42	0	187	0	0
T62	0	292	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7291589	0	0
T1	15218	9756	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8205	0	0
T7	7367	6960	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	62	0	0
T73	1139	0	0	0
T88	0	3	0	0
T90	0	13	0	0
T100	619	0	0	0
T121	163770	0	0	0
T134	0	2	0	0
T161	0	1	0	0
T196	0	9	0	0
T239	0	2	0	0
T242	13121	2	0	0
T243	0	10	0	0
T244	0	11	0	0
T245	0	4	0	0
T246	16072	0	0	0
T247	406	0	0	0
T248	34440	0	0	0
T249	426	0	0	0
T250	522	0	0	0
T251	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	15289	0	0
T1	15218	18	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	212	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	389	0	0
T23	0	71	0	0
T24	0	165	0	0
T25	0	152	0	0
T26	0	170	0	0
T37	0	51	0	0
T42	0	113	0	0
T62	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	316	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	3	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	7	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	2	0	0
T37	0	6	0	0
T42	0	1	0	0
T62	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6918204	0	0
T1	15218	9322	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8204	0	0
T7	7367	5407	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7806	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6919794	0	0
T1	15218	9338	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8206	0	0
T7	7367	5408	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7807	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	422	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	3	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	8	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	3	0	0
T37	0	9	0	0
T42	0	5	0	0
T62	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	382	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	3	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	7	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	2	0	0
T37	0	6	0	0
T42	0	3	0	0
T62	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	316	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	3	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	7	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	2	0	0
T37	0	6	0	0
T42	0	1	0	0
T62	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	316	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	3	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	7	0	0
T23	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	2	0	0
T37	0	6	0	0
T42	0	1	0	0
T62	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	14952	0	0
T1	15218	16	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	209	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	382	0	0
T23	0	70	0	0
T24	0	164	0	0
T25	0	151	0	0
T26	0	168	0	0
T37	0	45	0	0
T42	0	112	0	0
T62	0	16	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	292	0	0
T1	15218	2	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	0	0	0
T7	7367	3	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T22	0	7	0	0
T23	0	1	0	0
T25	0	1	0	0
T26	0	2	0	0
T37	0	6	0	0
T62	0	3	0	0
T98	0	3	0	0
T215	0	5	0	0