Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T14
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T14

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T7,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T14
1	0	Covered	T6,T7,T36
1	1	Covered	T6,T7,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T36
0	1	Covered	T7,T41,T42
1	0	Covered	T7,T42,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T36,T23
0	1	Covered	T6,T36,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T36,T23
1	-	Covered	T6,T36,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T7,T14
DetectSt	168	Covered	T6,T7,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T36,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T7,T36
DebounceSt->IdleSt	163	Covered	T14,T42,T63
DetectSt->IdleSt	186	Covered	T7,T41,T42
DetectSt->StableSt	191	Covered	T6,T36,T23
IdleSt->DebounceSt	148	Covered	T6,T7,T14
StableSt->IdleSt	206	Covered	T6,T36,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T14
0	1	Covered	T6,T7,T14
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T7,T14
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T7,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T42,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T7,T14
DetectSt	-	-	-	-	1	-	-	Covered	T7,T41,T42
DetectSt	-	-	-	-	0	1	-	Covered	T6,T36,T23
DetectSt	-	-	-	-	0	0	-	Covered	T6,T7,T36
StableSt	-	-	-	-	-	-	1	Covered	T6,T36,T23
StableSt	-	-	-	-	-	-	0	Covered	T6,T36,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	3060	0	0
CntIncr_A	7906335	106992	0	0
CntNoWrap_A	7906335	7289333	0	0
DetectStDropOut_A	7906335	325	0	0
DetectedOut_A	7906335	90659	0	0
DetectedPulseOut_A	7906335	1095	0	0
DisabledIdleSt_A	7906335	6793037	0	0
DisabledNoDetection_A	7906335	6795113	0	0
EnterDebounceSt_A	7906335	1538	0	0
EnterDetectSt_A	7906335	1522	0	0
EnterStableSt_A	7906335	1095	0	0
PulseIsPulse_A	7906335	1095	0	0
StayInStableSt	7906335	89434	0	0
gen_high_event_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	965	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	3060	0	0
T6	8611	48	0	0
T7	7367	16	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T23	0	52	0	0
T24	0	26	0	0
T25	0	22	0	0
T36	0	50	0	0
T41	0	4	0	0
T42	0	16	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	106992	0	0
T6	8611	1056	0	0
T7	7367	516	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	1184	0	0
T18	686	0	0	0
T23	0	884	0	0
T24	0	923	0	0
T25	0	572	0	0
T36	0	2175	0	0
T41	0	96	0	0
T42	0	317	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1350	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7289333	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8157	0	0
T7	7367	6950	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7841	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	325	0	0
T7	7367	4	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	1	0	0
T79	0	18	0	0
T81	0	29	0	0
T82	0	7	0	0
T83	0	10	0	0
T84	0	18	0	0
T93	423	0	0	0
T252	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	90659	0	0
T6	8611	1299	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	2046	0	0
T24	0	610	0	0
T25	0	2135	0	0
T36	0	917	0	0
T42	0	343	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1597	0	0
T63	0	270	0	0
T98	0	1389	0	0
T233	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1095	0	0
T6	8611	24	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	26	0	0
T24	0	13	0	0
T25	0	11	0	0
T36	0	25	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	27	0	0
T63	0	5	0	0
T98	0	12	0	0
T233	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6793037	0	0
T1	15218	9760	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	4081	0	0
T7	7367	3513	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	2016	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6795113	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	4081	0	0
T7	7367	3513	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	2016	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1538	0	0
T6	8611	24	0	0
T7	7367	8	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	4	0	0
T18	686	0	0	0
T23	0	26	0	0
T24	0	13	0	0
T25	0	11	0	0
T36	0	25	0	0
T41	0	2	0	0
T42	0	9	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1522	0	0
T6	8611	24	0	0
T7	7367	8	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	26	0	0
T24	0	13	0	0
T25	0	11	0	0
T36	0	25	0	0
T41	0	2	0	0
T42	0	7	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	27	0	0
T98	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1095	0	0
T6	8611	24	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	26	0	0
T24	0	13	0	0
T25	0	11	0	0
T36	0	25	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	27	0	0
T63	0	5	0	0
T98	0	12	0	0
T233	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	1095	0	0
T6	8611	24	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	26	0	0
T24	0	13	0	0
T25	0	11	0	0
T36	0	25	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	27	0	0
T63	0	5	0	0
T98	0	12	0	0
T233	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	89434	0	0
T6	8611	1274	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	2019	0	0
T24	0	596	0	0
T25	0	2123	0	0
T36	0	892	0	0
T42	0	338	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1569	0	0
T63	0	265	0	0
T98	0	1373	0	0
T233	0	34	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	965	0	0
T6	8611	23	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	25	0	0
T24	0	12	0	0
T25	0	10	0	0
T36	0	25	0	0
T42	0	5	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	26	0	0
T63	0	5	0	0
T98	0	8	0	0
T233	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T7
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T6,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T6,T37

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T37,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T37
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T6,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T37,T21
0	1	Covered	T21,T22,T42
1	0	Covered	T42,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T37,T23
0	1	Covered	T6,T37,T23
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T37,T23
1	-	Covered	T6,T37,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T37
DetectSt	168	Covered	T6,T37,T21
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T37,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T37,T21
DebounceSt->IdleSt	163	Covered	T1,T36,T21
DetectSt->IdleSt	186	Covered	T21,T22,T42
DetectSt->StableSt	191	Covered	T6,T37,T23
IdleSt->DebounceSt	148	Covered	T1,T6,T37
StableSt->IdleSt	206	Covered	T6,T37,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T37
0	1	Covered	T1,T6,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T37,T21
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T42,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T37,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T36,T21
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T37
DetectSt	-	-	-	-	1	-	-	Covered	T21,T22,T42
DetectSt	-	-	-	-	0	1	-	Covered	T6,T37,T23
DetectSt	-	-	-	-	0	0	-	Covered	T6,T37,T21
StableSt	-	-	-	-	-	-	1	Covered	T6,T37,T23
StableSt	-	-	-	-	-	-	0	Covered	T6,T37,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7906335	877	0	0
CntIncr_A	7906335	47296	0	0
CntNoWrap_A	7906335	7291516	0	0
DetectStDropOut_A	7906335	57	0	0
DetectedOut_A	7906335	13934	0	0
DetectedPulseOut_A	7906335	354	0	0
DisabledIdleSt_A	7906335	6911219	0	0
DisabledNoDetection_A	7906335	6912784	0	0
EnterDebounceSt_A	7906335	463	0	0
EnterDetectSt_A	7906335	414	0	0
EnterStableSt_A	7906335	354	0	0
PulseIsPulse_A	7906335	354	0	0
StayInStableSt	7906335	13536	0	0
gen_high_level_sva.HighLevelEvent_A	7906335	7294690	0	0
gen_not_sticky_sva.StableStDropOut_A	7906335	305	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	877	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	2	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T21	0	6	0	0
T22	0	14	0	0
T23	0	12	0	0
T24	0	2	0	0
T36	0	1	0	0
T37	0	16	0	0
T42	0	8	0	0
T59	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	47296	0	0
T1	15218	10	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	52	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T21	0	339	0	0
T22	0	1326	0	0
T23	0	390	0	0
T24	0	69	0	0
T36	0	48	0	0
T37	0	832	0	0
T42	0	160	0	0
T59	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7291516	0	0
T1	15218	9759	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	8203	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	57	0	0
T21	9264	2	0	0
T22	0	6	0	0
T23	8901	0	0	0
T42	0	1	0	0
T49	1046	0	0	0
T56	492	0	0	0
T62	0	7	0	0
T80	0	2	0	0
T107	0	1	0	0
T131	0	3	0	0
T215	0	2	0	0
T224	403	0	0	0
T225	402	0	0	0
T226	551	0	0	0
T228	0	3	0	0
T253	0	4	0	0
T254	639	0	0	0
T255	1304	0	0	0
T256	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	13934	0	0
T6	8611	22	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	381	0	0
T24	0	45	0	0
T25	0	123	0	0
T26	0	52	0	0
T37	0	419	0	0
T42	0	112	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	53	0	0
T63	0	75	0	0
T98	0	198	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	354	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	5	0	0
T37	0	8	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1	0	0
T63	0	1	0	0
T98	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6911219	0	0
T1	15218	9322	0	0
T2	2227	624	0	0
T3	578	177	0	0
T4	422	21	0	0
T5	501	100	0	0
T6	8611	6907	0	0
T7	7367	6966	0	0
T8	249850	244264	0	0
T13	581	180	0	0
T14	8246	7845	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	6912784	0	0
T1	15218	9338	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	6908	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	463	0	0
T1	15218	1	0	0
T2	2227	0	0	0
T3	578	0	0	0
T4	422	0	0	0
T5	501	0	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T21	0	4	0	0
T22	0	8	0	0
T23	0	6	0	0
T24	0	1	0	0
T36	0	1	0	0
T37	0	8	0	0
T42	0	5	0	0
T59	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	414	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T21	0	2	0	0
T22	0	6	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T37	0	8	0	0
T42	0	3	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1	0	0
T62	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	354	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	5	0	0
T37	0	8	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1	0	0
T63	0	1	0	0
T98	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	354	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	5	0	0
T37	0	8	0	0
T42	0	1	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	1	0	0
T63	0	1	0	0
T98	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	13536	0	0
T6	8611	21	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	375	0	0
T24	0	44	0	0
T25	0	122	0	0
T26	0	47	0	0
T37	0	411	0	0
T42	0	111	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T59	0	51	0	0
T63	0	74	0	0
T98	0	189	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	7294690	0	0
T1	15218	9778	0	0
T2	2227	627	0	0
T3	578	178	0	0
T4	422	22	0	0
T5	501	101	0	0
T6	8611	8207	0	0
T7	7367	6967	0	0
T8	249850	244277	0	0
T13	581	181	0	0
T14	8246	7846	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7906335	305	0	0
T6	8611	1	0	0
T7	7367	0	0	0
T8	249850	0	0	0
T9	8652	0	0	0
T13	581	0	0	0
T14	8246	0	0	0
T18	686	0	0	0
T23	0	4	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	5	0	0
T37	0	8	0	0
T45	405	0	0	0
T46	416	0	0	0
T47	554	0	0	0
T63	0	1	0	0
T98	0	1	0	0
T143	0	1	0	0
T145	0	2	0	0